Variable bit-width adder tree generation system based on multiple types of approximate computing units

Abstract

The application relates to a variable bit width adder tree generation system based on multiple types of approximate calculation units, which comprises a signal input module, an adder tree construction module and a calculation and result output module. The input end A of the signal input module receives two groups of addends and defines the bit width; the input end B receives the required precision bit number and initializes the precision comparison module. The input end of the adder tree construction module receives two groups of addends; the approximate calculation unit library and the Boolean gate logic unit library are initialized and called respectively; in the iteration process, different types of approximate calculation units are selected in different levels according to the precision requirement input by the user. The calculation and result output module performs approximate addition operation on the approximate adder tree module generated in the last stage, and finally completes the approximate calculation task. The application realizes dynamic configuration of the bit width of the approximate addition operation, makes the selection of the precision and the power consumption more flexible, and solves the technical problem of poor precision of the existing approximate addition dynamic configuration scheme.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and manufacturing technology, and in particular to a variable bit-width adder tree generation system based on multiple types of approximate computing units. Background Technology

[0002] To improve adder performance, approximate computation incorporates accuracy into the trade-off, intentionally sacrificing a certain amount of accuracy to achieve a significant performance boost. We call adders employing this approximate computation approach approximate adders. Some typical approximate adders include low-order OR gate adders, fault-tolerant adders, accuracy-configurable adders, carry-predictive selection adders, and carry-skip adders. These approximate adders are all used for multi-bit computation, performing precise calculations on bits with higher weights while using approximation methods for bits with lower weights.

[0003] In addition to the approximate adders mentioned above for multi-bit calculations, the traditional implementation of full adders, namely mirror adders, is modified. While ensuring the circuit does not open or short-circuit, three approximate mirror adders are obtained by gradually removing transistors from the full adder, named AMA1, AMA2, and AMA3 respectively.

[0004] In recent years, energy-saving design has received increasing attention because numerous applications require low-power custom designs. However, the amount of data these hardware devices need to process is increasing dramatically. To simultaneously meet power consumption and performance requirements, there are two existing dynamic configuration schemes for approximate addition: one method controls the calculation accuracy by configuring the number of iterations, which requires repeated iterations, has a long configuration time, and cannot guarantee real-time calculation; the other method configures the approximate number of bits based on the data bit width, but the adjustable range and results are somewhat arbitrary. Therefore, there is a need to design an adder tree generation system that can overcome the shortcomings of existing dynamic configuration schemes that only perform addition. Summary of the Invention

[0005] To address the existing technical problems, this invention provides a variable bit-width adder tree generation system based on multiple types of approximation calculation units.

[0006] The specific content of the present invention is as follows: A variable bit-width adder tree generation system based on multiple types of approximation calculation units, comprising: a variable bit-width signal input module, wherein its input terminal A receives two sets of n1 bit-width addends and defines the bit width of the input terminal of the iterative adder as n1 bit; its input terminal B receives the number of bits n2 required by the user for precision; and initializes the precision comparison module; the value of n2 is between 1 and n1.

[0007] The adder tree construction module receives two sets of n1-bit wide addends from the input module. Its initialization process calls the approximate calculation unit library and the Boolean gate logic unit library. During iteration, it selects different types of approximate calculation units for different levels based on user input precision requirements. It utilizes the convergence characteristics between different calculation units to meet computational objectives with varying precision and performance requirements. After multiple iterations, the approximate adder tree model is transferred to the approximate calculation unit module to complete the final computation. The approximate adder library and basic logic gate units in this module can be user-defined to meet specific performance requirements under different process libraries and design specifications.

[0008] The calculation and result output module performs approximate addition operations on the approximate adder tree module generated in the previous stage to complete the final approximate calculation task. At the same time, this module transmits the accuracy requirement data in the input signal to the accuracy control module to reasonably control the accuracy in the approximate calculation process. Finally, the output link completes the data output.

[0009] Furthermore, the variable bit-width signal input module includes:

[0010] The first-bit counting circuit submodule can determine the number of bits of the first 1 in the received signal, and then determine that the input data bit width is n bits.

[0011] The continuous / single-bit 0 counter circuit submodule receives the input signal at its input terminal, determines the number of 0s, and buffers them.

[0012] The continuous / single-bit 1 counter circuit submodule receives the input signal at its input terminal, determines the number of 1s, and buffers them.

[0013] Its working process specifically includes steps 101 to 105, as follows:

[0014] Step 101: Define the bit width signal based on the input data, and initialize the system's bit width unit based on the bit width length n1 of the input data.

[0015] Step 102: Input the precision data n2 as the control signal for subsequent calculations to complete the precision control signal initialization.

[0016] Step 103: Accuracy compliance check. The required accuracy length n2 is judged to check whether it meets the data bit width requirement. If it does, it will be passed to the next level. If it does not meet the requirement, it will be required to re-enter.

[0017] Step 104: Determine whether the bit widths of the two sets of addition data are the same. If they are the same, proceed directly to the next level. If they are different, the shorter data will be reorganized based on the number of additions with the longer bit width to increase its effective number of bits and make the calculation vector uniform.

[0018] Step 105: The final integration module will integrate the three sets of data that have been processed and output them to the next level system.

[0019] Furthermore, the adder tree construction generation module includes:

[0020] The probabilistically compensated adder unit: The input data unit of the probabilistically compensated adder is a basic adder model with a probability distribution of variable parameters (0-1). After multiple iterations under specific parameters, the probabilistically compensated adder can provide an approximate probabilistically compensated adder with a very close accuracy to the error.

[0021] The truth table regression-based adder unit: The truth table regression adder is generated based on the truth table error in the previous iteration cycle as the output signal for the next iteration cycle. After iteration with specific correction parameters, the truth table regression adder can provide an adder sequence that is very close to the error accuracy.

[0022] User-defined approximation calculation unit library: This unit library integrates multiple types of basic approximation calculation units to implement basic logic units for approximation calculation under different process parameter requirements.

[0023] User-defined basic Boolean logic gate unit library: This unit library integrates multiple types of basic Boolean logic operation units to realize approximate calculation of basic Boolean logic calculation functions under different process parameter requirements.

[0024] The specific steps in its working process include 201 to 205, as follows:

[0025] Step 201: The adder number generation module receives the input data and accuracy requirement data passed from the previous level to this level, and first preloads the approximate calculation units that may be called.

[0026] Step 202: Use the preloaded approximation calculation module to perform a preliminary construction of the target adder tree, and output a model with the highest possible accuracy under the fastest iteration conditions.

[0027] Step 203: Judge the approximate adder tree constructed in the above manner. If it meets the required accuracy, the construction result is directly sent to the calculation module.

[0028] Step 204: If an approximate adder that meets the requirements cannot be constructed under the fast construction condition, the remaining approximate calculation module will be activated and re-participate in the whole process iteration. This will consume a longer iteration time, but will improve the accuracy to a higher level than fast construction.

[0029] Step 205: The approximate adder tree module constructed in steps 203 and 204 will be finally integrated at this level and then transferred to the next level of calculation and precision control unit.

[0030] Furthermore, the calculation and result output module includes:

[0031] Approximate Calculation Unit Module: This module uses the adder library generated in the previous level approximate adder spanning tree module to complete the approximate addition calculation.

[0032] Precision control module: This module reshapes the bit width of the calculated data according to the required precision of the input, retaining the required n1 precision bit width.

[0033] Approximate calculation result output module: This module is used to connect with other subsequent circuits to complete the data transmission function; it has basic logic transmission and level isolation functions.

[0034] Its working process specifically includes steps 301 to 305, as follows:

[0035] Step 301: Receive the initial computation data passed to this level after the first two groups of modules have completed their iterations, activate the parallel computing interface, and prepare for computation.

[0036] Step 302: Perform parallel computing. During this process, the precision control array of the preceding stage is called to control the precision of the calculation results in real time, ensuring that the calculation process matches the expected settings.

[0037] Step 303: Activate the output port. Activate and isolate the output of the port connected to the downstream circuit or peripheral device.

[0038] Step 304: The synchronous timing control module detects the timing of the output signal to ensure that the data output of the current cycle has been completed before writing the data for the next cycle, thus avoiding logical conflicts.

[0039] Step 305: Final output module. The data from the final calculation will be output to the final peripheral unit via this module.

[0040] To address the shortcomings of the aforementioned background technology, this invention proposes an adaptive approximate adder tree generation system based on a multi-type approximate computation unit library. In the approximate computation technology, the configuration of the approximate multiplication operation is dynamically adjusted according to the effective bit width of the input system data. Within the allowable error range, the most suitable approximate configuration scheme is found, realizing the dynamic configuration of the bit width of the approximate addition operation. This makes the selection of accuracy and power consumption more flexible and solves the technical problem of poor accuracy in existing dynamic configuration schemes for approximate addition. Attached Figure Description

[0041] The specific embodiments of the present invention will be further explained below with reference to the accompanying drawings.

[0042] Figure 1 This is an overall architecture diagram of the variable bit-width adder tree generation system based on multiple types of approximation calculation units of the present invention;

[0043] Figure 2 This is a flowchart illustrating the operation of the variable bit-width signal input module of the present invention.

[0044] Figure 3 This is a flowchart of the adder tree construction and generation module of the present invention;

[0045] Figure 4 This is a flowchart of the calculation and result output module in this invention. Detailed Implementation

[0046] Combination Figures 1-4 This invention, based on existing approximation calculation modules, newly designs an adder tree generation system with dynamically configurable data bit width. For each set of data to be calculated, it finds the most suitable approximation scheme according to its data characteristics, ensuring that the approximation error for each set of data is within an acceptable range, greatly improving the reliability of the approximation scheme. The core modules of this invention are a variable bit width signal input module, an adder tree construction and generation module, and a calculation and result output module.

[0047] The variable bit width signal input module has two sets of n1 bit width addends at its input terminal A, and defines the bit width of the input terminal of the iterative adder as n1 bit; its input terminal B receives the number of bits n2 required by the user for precision; and initializes the precision comparison module; the value of n2 is between 1 and n1.

[0048] The variable bit-width signal input module includes:

[0049] The first-bit counting circuit submodule can determine the number of bits of the first 1 in the received signal, and then determine that the input data bit width is n bits.

[0050] The continuous / single-bit 0 counter circuit submodule receives the input signal at its input terminal, determines the number of 0s, and buffers them.

[0051] The continuous / single-bit 1 counter circuit submodule receives the input signal at its input terminal, determines the number of 1s, and buffers them.

[0052] like Figure 2 As shown, the workflow of the variable bit-width signal input module specifically includes steps 101 to 105. (See below:)

[0053] Step 101: Define the bit width signal based on the input data, and initialize the system's bit width unit based on the bit width length n1 of the input data.

[0054] Step 102: Input the precision data n2 as the control signal for subsequent calculations to complete the precision control signal initialization.

[0055] Step 103: Accuracy compliance check. The required accuracy length n2 is judged to check whether it meets the data bit width requirement. If it does, it will be passed to the next level. If it does not meet the requirement, it will be required to re-enter.

[0056] Step 104: Determine whether the bit widths of the two sets of addition data are the same. If they are the same, proceed directly to the next level. If they are different, the shorter data will be reorganized based on the number of additions with the longer bit width to increase its effective number of bits and make the calculation vector uniform.

[0057] Step 105: The final integration module will integrate the three sets of data that have been processed and output them to the next level system.

[0058] The adder tree construction module receives two sets of n1-bit wide addends from the input module. Its initialization process calls the approximate calculation unit library and the Boolean gate logic unit library. During iteration, it selects different types of approximate calculation units for different levels based on user input precision requirements. It utilizes the convergence characteristics between different calculation units to meet computational objectives with varying precision and performance requirements. After multiple iterations, the approximate adder tree model is transferred to the approximate calculation unit module to complete the final computation. The approximate adder library and basic logic gate units in this module can be user-defined to meet specific performance requirements under different process libraries and design specifications.

[0059] It includes:

[0060] The probabilistically compensated adder unit: The input data unit of the probabilistically compensated adder is a basic adder model with a probability distribution of variable parameters (0-1). After multiple iterations under specific parameters, the probabilistically compensated adder can provide an approximate probabilistically compensated adder with a very close accuracy to the error.

[0061] The truth table regression-based adder unit: The truth table regression adder is generated based on the truth table error in the previous iteration cycle as the output signal for the next iteration cycle. After iteration with specific correction parameters, the truth table regression adder can provide an adder sequence that is very close to the error accuracy.

[0062] User-defined approximation calculation unit library: This unit library integrates multiple types of basic approximation calculation units to implement basic logic units for approximation calculation under different process parameter requirements.

[0063] User-defined basic Boolean logic gate unit library: This unit library integrates multiple types of basic Boolean logic operation units to realize approximate calculation of basic Boolean logic calculation functions under different process parameter requirements.

[0064] like Figure 3 As shown, the specific steps in the adder tree construction module's workflow include steps 201 to 205. (See below:)

[0065] Step 201: The adder number generation module receives the input data and accuracy requirement data passed from the previous level to this level, and first preloads the approximate calculation units that may be called.

[0066] Step 202: Use the preloaded approximation calculation module to perform a preliminary construction of the target adder tree, and output a model with the highest possible accuracy under the fastest iteration conditions.

[0067] Step 203: Judge the approximate adder tree constructed in the above manner. If it meets the required accuracy, the construction result is directly sent to the calculation module.

[0068] Step 204: If an approximate adder that meets the requirements cannot be constructed under the fast construction condition, the remaining approximate calculation module will be activated and re-participate in the whole process iteration. This will consume a longer iteration time, but will improve the accuracy to a higher level than fast construction.

[0069] Step 205: The approximate adder tree module constructed in steps 203 and 204 will be finally integrated at this level and then transferred to the next level of calculation and precision control unit.

[0070] The calculation and result output module performs approximate addition operations on the approximate adder tree module generated in the previous stage to complete the final approximate calculation task. At the same time, this module transmits the accuracy requirement data in the input signal to the accuracy control module to reasonably control the accuracy in the approximate calculation process. Finally, the output link completes the data output.

[0071] It includes:

[0072] Approximate Calculation Unit Module: This module uses the adder library generated in the previous level approximate adder spanning tree module to complete the approximate addition calculation.

[0073] Precision control module: This module reshapes the bit width of the calculated data according to the required precision of the input, retaining the required n1 precision bit width.

[0074] Approximate calculation result output module: This module is used to interconnect with other subsequent circuits to complete data transmission; it has basic logic transmission and level isolation functions.

[0075] like Figure 4 As shown, the workflow of the calculation and result output module specifically includes steps 301 to 305. (See below:)

[0076] Step 301: Receive the initial computation data passed to this level after the first two groups of modules have completed their iterations, activate the parallel computing interface, and prepare for computation.

[0077] Step 302: Perform parallel computing. During this process, the precision control array of the preceding stage is called to control the precision of the calculation results in real time, ensuring that the calculation process matches the expected settings.

[0078] Step 303: Activate the output port. Activate and isolate the output of the port connected to the downstream circuit or peripheral device.

[0079] Step 304: The synchronous timing control module detects the timing of the output signal to ensure that the data output of the current cycle has been completed before writing the data for the next cycle, thus avoiding logical conflicts.

[0080] Step 305: Final output module. The data from the final calculation will be output to the final peripheral unit via this module.

[0081] The adder of this invention features variable bit width and adaptive adder tree generation. Its basic function is to achieve low-power, high-precision approximate addition calculations, specifically implementing the following functions: preprocessing the input data to obtain its effective bit width; configuring the number of bit widths enabled by the approximate adder based on the effective bit width of the input data and the expected calculation accuracy; adaptively selecting approximate calculation units of a specific type based on real-time analysis using an approximate calculation unit library; constructing a multi-level interconnected adder tree structure to complete the approximate adder operation; restoring the bit width of the data; and outputting the final calculation result. Using this system, the input bit width can be adaptively adjusted and the circuit configured to implement the approximate calculation process.

[0082] This design can flexibly call existing approximation calculation modules during the adder tree construction process to complete the circuit configuration. Its initialization process will call the approximation calculation unit library and the Boolean gate logic unit library respectively; during its iteration process, different types of approximation calculation units will be selected for different levels based on the user's input precision requirements; it will utilize the convergence characteristics between different calculation units to meet different precision and performance requirements. After multiple iterations, the approximation adder tree model will be transferred to the approximation calculation unit module to complete the final calculation requirements. The approximation adder library and basic logic gate units in this module can be customized by the user to meet the specific performance requirements under different technology libraries and design requirements.

[0083] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A variable bit-width adder tree generation system based on multiple types of approximation computation units, characterized in that: It includes a signal input module, an adder tree construction module, and a calculation and result output module. The input terminal A of the signal input module receives two sets of n1-bit wide addends, and defines the bit width of the input terminal of the iterative adder as n1 bits; Its input terminal B receives the number of bits n2 required by the user for precision; and initializes the precision comparison module; the value of n2 is between 1 and n1; The input of the adder tree construction module receives two sets of n1-bit wide adders that are received and transmitted by the signal input module; its initialization process will call the approximate calculation unit library and the Boolean gate logic unit library respectively. During its iteration process, different types of approximate calculation units will be selected for different levels based on the user's input accuracy requirements; the convergence characteristics between different calculation units will be utilized to meet the calculation objectives with different accuracy and performance requirements; after multiple iterations, the approximate adder tree model will be transferred to the approximate calculation unit module to complete the final calculation requirements. The calculation and result output module performs approximate addition operations on the approximate adder tree module generated in the previous stage to complete the final approximate calculation task. At the same time, this module transmits the accuracy requirement data in the input signal to the accuracy control module to reasonably control the accuracy in the approximate calculation process. Finally, the output link completes the data output.

2. The variable bit-width adder tree generation system based on multiple types of approximation calculation units according to claim 1, characterized in that: The signal input module includes: The first-bit counting circuit submodule determines the number of bits of the first 1 in the received signal, and then determines that the input data bit width is n bits. The continuous / single-bit 0 counter circuit submodule receives the input signal at its input terminal, determines the number of 0s, and buffers them. The continuous / single-bit 1 counter circuit submodule receives the input signal at its input terminal, determines the number of 1s, and buffers them.

3. The variable bit-width adder tree generation system based on multiple types of approximation calculation units according to claim 2, characterized in that: The signal input module processes data through the following steps: Step 101: Define the bit width signal based on the input data, and initialize the system's bit width unit based on the bit width length n1 of the input data; Step 102: Input the precision data n2 as the control signal for subsequent calculations to complete the precision control signal initialization; Step 103: Accuracy compliance check. The required accuracy length n2 is checked to see if it meets the data bit width requirement. If it does, it will be passed to the next level. If it does not meet the requirement, it will be required to re-enter. Step 104: Determine whether the bit widths of the two sets of addition data are the same. If they are the same, proceed directly to the next level. If they are different, the shorter data will be reorganized according to the number of additions with the longer bit width to increase its effective number of bits and make the calculation vector uniform. Step 105: The final integration module will integrate the three sets of data that have been processed and output them to the next level system.

4. The variable bit-width adder tree generation system based on multiple types of approximation calculation units according to claim 1, characterized in that: The adder tree construction module includes: The probability-compensated adder unit takes a basic adder model with a variable probability distribution as its input data unit. After multiple iterations under specific parameters, it provides an approximate probability-compensated adder that is very close to the error accuracy. The truth table regression adder unit generates the truth table regression adder based on the truth table error in the previous iteration cycle as the output signal of the next iteration cycle. After iteration with specific correction parameters, the truth table regression adder can give an adder sequence that is very close to the error accuracy. A user-defined approximation calculation unit library that integrates multiple types of basic approximation calculation units to realize basic logic units for approximation calculation under different process parameter requirements; A user-defined basic Boolean logic gate unit library that integrates multiple types of basic Boolean logic operation units to achieve approximate calculation of basic Boolean logic calculation functions under different process parameter requirements.

5. The variable bit-width adder tree generation system based on multiple types of approximation calculation units according to claim 4, characterized in that: The adder tree construction module processes data through the following steps: Step 201: The adder tree construction module receives the input data and accuracy requirement data passed from the previous level to this level, and first preloads the approximate calculation units that may be called. Step 202: Use the preloaded approximation calculation module to perform a preliminary construction of the target adder tree; Step 203: Judge the approximate adder tree constructed in the above manner. If it meets the required accuracy, the construction result is directly sent to the calculation module. Step 204: If an approximate adder that meets the requirements cannot be constructed under the condition of rapid construction, then activate the remaining approximate calculation module and re-participate in the whole process iteration; Step 205: The approximate adder tree module constructed in steps 203 and 204 will be finally integrated at this level and then transferred to the next level of calculation and precision control unit.

6. The variable bit-width adder tree generation system based on multi-type approximation calculation units according to claim 1, characterized in that: The calculation and result output module includes: The approximate calculation unit module uses the adder library generated in the previous approximate adder spanning tree module to perform approximate addition calculations. The precision control module reshapes the bit width of the calculated data according to the required precision, retaining the required n1 precision bit width. The approximate calculation result output module is interconnected with other subsequent circuits to complete the data transmission function. It has basic logic transmission and level isolation functions.

7. The variable bit-width adder tree generation system based on multi-type approximation calculation units according to claim 6, characterized in that: The calculation and result output module processes data including: Step 301: Receive the initial computation data passed to this level after the first two groups of modules have completed their iterations, activate the parallel computing interface, and prepare for computation; Step 302: Perform parallel computing. During this process, the precision control array of the preceding stage is called to control the precision of the calculation results in real time, ensuring that the calculation process matches the expected settings. Step 303: Activate the output port, activate the port connected to the downstream circuit or peripheral device and isolate the output; Step 304: The synchronous timing control module detects the timing of the output signal to ensure that the data output of the current cycle has been completed before writing the data of the next cycle, so as to avoid logical conflicts; Step 305: Final output module. The data from the final calculation will be output to the final peripheral unit via this module.

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