Drive circuit and semiconductor memory

Abstract

The present disclosure provides a driving circuit and a semiconductor memory, a control end of a first control unit receives a first driving signal, a first end is connected to a first power supply end, a second end is connected to a first end of a first impedance network, a control end of the first impedance network receives a first original correction signal, and a second end is connected to an input / output end. The first control unit controls whether a transistor in the first impedance network is turned on to the first power supply end, the first impedance network controls the state of the transistor in the first impedance network based on the first original correction signal to correct the resistance value of the first impedance network, and the first control unit controls the transistor in the first impedance network to be turned on to the first power supply end under the control of the first driving signal, and when the transistor in the first impedance network is controlled by the first control unit to be turned off under the control of the first original correction signal, the transistor in the first impedance network is in a cut-off state from the input / output end, thereby being able to reduce the capacitance on the input / output end and improve the data transmission quality.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a driving circuit and semiconductor memory. BACKGROUND

[0002] The input / output signal quality of input / output terminals (DQ) is related to the capacitance (pincap) on the input / output terminals. In the process of high-speed data transmission between DRAM and CPU, the capacitance on the input / output terminals can be reduced to improve the data transmission quality.

[0003] At present, the capacitance on the input / output terminals can be reduced by reducing the size of the transistor (MOS), but reducing the size of the transistor will result in a larger output impedance (Ron), which will affect the data transmission quality. Therefore, how to reduce the capacitance on the input / output terminals within the original output impedance range is a technical problem to be solved. SUMMARY

[0004] The present disclosure provides a driving circuit and semiconductor memory, which reduces the capacitance on the input / output terminals within the original output impedance range and improves the data transmission quality.

[0005] In a first aspect, the embodiments of the present disclosure provide a driving circuit, comprising:

[0006] a first control unit, a control end of which receives a first driving signal, a first end of which is connected to a first power supply end, and a second end of which is connected to a first end of a first impedance network, for controlling whether a transistor in the first impedance network is connected to the first power supply end;

[0007] the first impedance network, a control end of which receives a first original correction signal, and a second end of which is connected to an input / output terminal, for controlling the state of the transistor in the first impedance network based on the first original correction signal to correct the resistance value of the first impedance network.

[0008] Optionally, the driving circuit further comprises:

[0009] a second control unit, a control end of which receives a second driving signal, a first end of which is connected to a second end of a second impedance network, and a second end of which is connected to a second power supply end, for controlling whether a transistor in the second impedance network is connected to the second power supply end;

[0010] the second impedance network, a control end of which receives a second original correction signal, and a first end of which is connected to the input / output terminal, for controlling the state of the transistor in the second impedance network based on the second original correction signal to correct the resistance value of the second impedance network.

[0011] Optionally, the first power supply terminal provides a power supply voltage, and the second power supply terminal provides a ground voltage; or the first power supply terminal provides the ground voltage, and the second power supply terminal provides the power supply voltage.

[0012] Optionally, the first control unit comprises a first pull-up transistor, a second pull-up transistor and a third pull-up transistor.

[0013] The first end of the first pull-up transistor, the first end of the second pull-up transistor and the first end of the third pull-up transistor are connected to each other as the first end of the first control unit.

[0014] The control end of the first pull-up transistor, the control end of the second pull-up transistor and the control end of the third pull-up transistor are the control end of the first control unit.

[0015] Optionally, the first impedance network comprises a fourth pull-up transistor, a fifth pull-up transistor and a sixth pull-up transistor.

[0016] The first end of the fourth pull-up transistor is connected to the second end of the first pull-up transistor, the first end of the fifth pull-up transistor is connected to the second end of the second pull-up transistor, and the first end of the sixth pull-up transistor is connected to the second end of the third pull-up transistor.

[0017] The second end of the fourth pull-up transistor, the second end of the fifth pull-up transistor and the second end of the sixth pull-up transistor are connected to each other as the second end of the first impedance network.

[0018] The control end of the fourth pull-up transistor, the control end of the fifth pull-up transistor and the control end of the sixth pull-up transistor are the control end of the first impedance network.

[0019] Optionally, the sizes of the first pull-up transistor, the second pull-up transistor and the third pull-up transistor form a geometric progression, and the sizes of the fourth pull-up transistor, the fifth pull-up transistor and the sixth pull-up transistor form a geometric progression.

[0020] Optionally, the second control unit comprises a first pull-down transistor, a second pull-down transistor and a third pull-down transistor.

[0021] The first end of the first pull-down transistor, the first end of the second pull-down transistor and the first end of the third pull-down transistor are the first end of the second control unit.

[0022] The second end of the first pull-down transistor, the second end of the second pull-down transistor and the second end of the third pull-down transistor are connected to each other as the second end of the second control unit.

[0023] The control end of the first pull-down transistor, the control end of the second pull-down transistor and the control end of the third pull-down transistor are the control end of the second control unit.

[0024] Optionally, the second impedance network comprises a fourth pull-down transistor, a fifth pull-down transistor and a sixth pull-down transistor.

[0025] The first end of the fourth pull-down transistor, the first end of the fifth pull-down transistor and the first end of the sixth pull-down transistor are connected with each other as the first end of the second impedance network.

[0026] The second end of the fourth pull-down transistor is connected with the first end of the first pull-down transistor, the second end of the fifth pull-down transistor is connected with the first end of the second pull-down transistor, and the second end of the sixth pull-down transistor is connected with the first end of the third pull-down transistor.

[0027] The control end of the fourth pull-down transistor, the control end of the fifth pull-down transistor and the control end of the sixth pull-down transistor are the control end of the second impedance network.

[0028] Optionally, the first pull-down transistor, the second pull-down transistor and the third pull-down transistor form a geometric progression, and the fourth pull-down transistor, the fifth pull-down transistor and the sixth pull-down transistor form a geometric progression.

[0029] Optionally, the driving circuit further comprises:

[0030] A first driving module, whose control end receives the first driving signal, whose first end is connected with the first power supply end, and whose second end is connected with the input and output end, is used for driving the input and output end.

[0031] A third impedance network, whose control end receives a first target correction signal, whose first end is connected with the first power supply end, and whose second end is connected with the input and output end, is used for correcting the resistance value of the third impedance network under the control of the first target correction signal, and the first target correction signal is generated according to a third original correction signal and the first driving signal.

[0032] The first driving module, the third impedance network, the first control unit and the first impedance network jointly adjust the output impedance of the driving circuit.

[0033] Optionally, the first driving module comprises:

[0034] A seventh pull-up transistor has a control terminal as a control terminal of the first drive module, receives the first drive signal, has a first terminal as a first terminal of the first drive module, and has a second terminal as a second terminal of the first drive module.

[0035] Optionally, the third impedance network comprises an eighth pull-up transistor, a ninth pull-up transistor, and a tenth pull-up transistor.

[0036] The control terminal of the eighth pull-up transistor, the control terminal of the ninth pull-up transistor, and the control terminal of the tenth pull-up transistor are connected to each other and serve as a control terminal of the third impedance network, and receive the first target correction signal.

[0037] The first terminal of the eighth pull-up transistor, the first terminal of the ninth pull-up transistor, and the first terminal of the tenth pull-up transistor are connected to each other and serve as a first terminal of the third impedance network.

[0038] The second terminal of the eighth pull-up transistor, the second terminal of the ninth pull-up transistor, and the second terminal of the tenth pull-up transistor are connected to each other and serve as a second terminal of the third impedance network.

[0039] Optionally, the drive circuit further comprises:

[0040] A second drive module has a control terminal that receives the second drive signal, has a first terminal connected to the input / output terminal, and has a second terminal connected to the second power supply terminal, and is configured to drive the input / output terminal.

[0041] A fourth impedance network has a control terminal that receives a second target correction signal, has a first terminal connected to the input / output terminal, and has a second terminal connected to the second power supply terminal, and is configured to correct a resistance value of the fourth impedance network under the control of the second target correction signal, wherein the second target correction signal is generated based on a fourth original correction signal and the second drive signal.

[0042] The second drive module, the fourth impedance network, the second control unit, and the second impedance network jointly adjust an output impedance of the drive circuit.

[0043] Optionally, the second drive module comprises:

[0044] A seventh pull-down transistor has a control terminal as a control terminal of the second drive module, receives the second drive signal, has a first terminal as a first terminal of the second drive module, and has a second terminal as a second terminal of the second drive module.

[0045] Optionally, the fourth impedance network comprises an eighth pull-down transistor, a ninth pull-down transistor, and a tenth pull-down transistor.

[0046] The control end of the eighth pull-down transistor, the control end of the ninth pull-down transistor and the control end of the tenth pull-down transistor are control ends of the fourth impedance network, and are used for receiving the second target correction signal.

[0047] The first end of the eighth pull-down transistor, the first end of the ninth pull-down transistor and the first end of the tenth pull-down transistor are connected with each other, and are first ends of the fourth impedance network.

[0048] The second end of the eighth pull-down transistor, the second end of the ninth pull-down transistor and the second end of the tenth pull-down transistor are connected with each other, and are second ends of the fourth impedance network.

[0049] In a second aspect, an embodiment of the present disclosure provides a semiconductor memory, comprising the driving circuit.

[0050] The driving circuit comprises a first control unit and a first impedance network. The control end of the first control unit receives a first driving signal. The first end of the first control unit is connected to a first power supply end. The second end of the first control unit is connected to the first end of the first impedance network. The control end of the first impedance network receives a first original correction signal. The second end of the first impedance network is connected to an input and output end. The first control unit controls whether the transistor in the first impedance network is connected to the first power supply end. The first impedance network controls the state of the transistor in the first impedance network based on the first original correction signal to correct the resistance value of the first impedance network. Therefore, under the control of the first driving signal, the first control unit controls the transistor in the first impedance network to be connected to the first power supply end. Under the control of the first original correction signal, when the first impedance network controls the transistor in the first impedance network to be closed, the transistor in the first impedance network is in a cut-off state from the input and output end, so that the capacitance on the input and output end can be reduced, and the data transmission quality can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the present disclosure or the prior art, the following will briefly introduce the drawings needed in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0052] Figure 1 It is a circuit structure diagram of a driving circuit;

[0053] Figure 2 It is a circuit structure diagram of a driving circuit;

[0054] Figure 3 It is a circuit structure diagram of a driving circuit provided by an embodiment of the present disclosure;

[0055] Figure 4 A circuit structure diagram of a driving circuit is provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, the technical solutions in the present disclosure will be described clearly and completely below with reference to the drawings in the present disclosure. Obviously, the described embodiments are only some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0057] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the description of the present disclosure in conjunction with the accompanying drawings. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following the general principles thereof and including other known ins and customary technical means not expressly disclosed. The description and embodiments are only considered as illustrative, and the true scope and spirit of the present disclosure are indicated by the claims above.

[0058] Figure 1 A circuit structure diagram of a driving circuit is provided for an embodiment of the present disclosure. Figure 1 As shown in the figure, the driving circuit includes a pull up driver strength (PUDS) 10 and a pull down driver strength (PDDS) 20, the pull up driver strength 10 includes a pull up control unit 1011, a pull up impedance network 1012, a first driving module 103 and a third impedance network 104, and the pull down driver strength 20 includes a pull down control unit 2011, a pull down impedance network 2012, a second driving module 203 and a fourth impedance network 204.

[0059] As shown in the figure, the driving circuit includes a pull up driver strength (PUDS) 10 and a pull down driver strength (PDDS) 20, the pull up driver strength 10 includes a pull up control unit 1011, a pull up impedance network 1012, a first driving module 103 and a third impedance network 104, and the pull down driver strength 20 includes a pull down control unit 2011, a pull down impedance network 2012, a second driving module 203 and a fourth impedance network 204. Figure 2The control end of the pull-up control unit 1011 receives the first drive signal Pumain, the first end of the pull-up control unit 1011 is connected to the second end of the pull-up impedance network 1012, and the second end of the pull-up control unit 1011 is connected to the input / output end DQ. The control end of the pull-up impedance network 1012 receives the first original correction signal Zqpu0-Zqpu2, the first end of the pull-up impedance network 1012 is connected to the first power supply end VDD. The control end of the first drive module 103 receives the first drive signal Pumain, the first end of the first drive module 103 is connected to the first power supply end VDD, and the second end of the first drive module 103 is connected to the input / output end DQ. The control end of the third impedance network 104 receives the first target correction signal Zqpu3-Zqpu5, the first end of the third impedance network 104 is connected to the first power supply end VDD, and the second end of the third impedance network 104 is connected to the input / output end DQ.

[0060] When the pull-up control unit 1011 is turned on under the control of the first drive signal Pumain, the transistor in the pull-up impedance network 1012 is turned on to control the input / output end. At this time, the first drive module 103 is turned on under the control of the first drive signal Pumain, and drives the input / output end. At this time, if the pull-up impedance network 1012 is turned on under the control of the first original correction signal Zqpu0-Zqpu2, and the third impedance network 104 is turned on under the action of the first target correction signal, the pull-up control unit 1011, the pull-up impedance network 1012, the first drive module 103 and the third impedance network 104 jointly adjust the output impedance of the pull-up module 10, for example, pull up the output impedance of the pull-up module 10; if the pull-up impedance network 1012 is turned off under the control of the first original correction signal Zqpu0-Zqpu2, the potential at the connection between the pull-up control unit 1011 and the pull-up impedance network 1012 is floating, that is, the transistor in the pull-up impedance network 1012 is in a floating state (drain / source floating). It should be noted that the first target correction signal Zqpu3-Zqpu5 is generated according to the third original correction signal and the first drive signal Pumain, and the third original correction signal is used to adjust the output impedance of the pull-up module 10.

[0061] The control end of the pull-down control unit 2011 receives the second driving signal Pdmain, the first end of the pull-down control unit 2011 is connected to the input / output end DQ, and the second end of the pull-down control unit 2011 is connected to the first end of the pull-down impedance network 2012. The control end of the pull-down impedance network 2012 receives the second original correction signal Zqpd0-Zqpd2, and the second end of the pull-down impedance network 2012 is connected to the second power supply end VSS. The control end of the second driving module 203 receives the second driving signal Pdmain, the first end of the second driving module 203 is connected to the input / output end DQ, and the second end of the second driving signal Pdmain is connected to the second power supply end VSS. The control end of the fourth impedance network 204 receives the second target correction signal Zqpd3-Zqpd5, the first end of the fourth impedance network 204 is connected to the input / output end DQ, and the second end of the fourth impedance network 204 is connected to the second power supply end VSS.

[0062] When the pull-down control unit 2011 is turned on under the control of the second driving signal Pdmain, the transistor in the pull-down impedance network 2012 is turned on to control the input / output end. At this time, the second driving module 203 is turned on under the control of the second driving signal Pdmain, and drives the input / output end. At this time, if the pull-down impedance network 2012 is turned on under the control of the second original correction signal Zqpd0-Zqpd2, the fourth impedance network 204 is turned on under the action of the second target correction signal Zqpd3-Zqpd5, and the pull-down control unit 2011, the pull-down impedance network 2012, the second driving module 203 and the fourth impedance network 204 jointly adjust the output impedance of the pull-down module 20, for example, the output impedance of the pull-down module 20 is pulled down; if the pull-down impedance network 2012 is turned off under the control of the second original correction signal Zqpd0-Zqpd2, the potential at the connection between the pull-down control unit 2011 and the pull-down impedance network 2012 is floating, that is, the transistor in the pull-down impedance network 2012 is in a floating state (drain / source floating). It should be noted that the second target correction signal Zqpd3-Zqpd5 is generated according to the fourth original correction signal and the second driving signal Pdmain, and the fourth original correction signal is used to adjust the output impedance of the pull-down module 20.

[0063] It should be noted that, from the input-output end, the capacitance on the input-output end when the transistor in the pull-up impedance network is in the floating state > the capacitance on the input-output end when the transistor in the pull-up impedance network is in the saturation region > the capacitance on the input-output end when the transistor in the pull-up impedance network is in the ohmic region > the capacitance on the input-output end when the transistor in the pull-up impedance network is in the cut-off region. From the input-output end, the capacitance on the input-output end when the transistor in the pull-down impedance network is in the floating state > the capacitance on the input-output end when the transistor in the pull-down impedance network is in the saturation region > the capacitance on the input-output end when the transistor in the pull-down impedance network is in the ohmic region > the capacitance on the input-output end when the transistor in the pull-down impedance network is in the cut-off region.

[0064] Figure 3 and Figure 4 A circuit diagram of a driving circuit provided by an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the driving circuit provided by the present disclosure includes a first control unit 101 and a first impedance network 102. The first control unit 101 is provided with a control end, a first end and a second end, and the first impedance network 102 is provided with a control end, a first end and a second end. The control end of the first control unit 101 receives a first driving signal Pumain, the first end of the first control unit 101 is connected to a first power end VDD, and the second end of the first control unit 101 is connected to the first end of the first impedance network 102. The control end of the first impedance network 102 receives a first original correction signal Zqpd0-Zqpd2, and the second end of the first impedance network 102 is connected to an input-output end DQ. Figure 3 Figure 4

[0065] ​​The first control unit 101 controls whether the transistor in the first impedance network 102 is connected to the first power supply end VDD. The first impedance network 102 controls the state of the transistor in the first impedance network 102 based on the first original correction signal Zqpd0-Zqpd2 to correct the resistance value of the first impedance network 102. When the first drive signal Pumain is the first level signal, the first control unit 101 controls the transistor in the first impedance network 102 to be connected to the first power supply end VDD under the control of the first drive signal Pumain. At this time, the transistor in the first impedance network 102 can be in a conducting state or a cut-off state from the perspective of the input and output end DQ. When the first impedance network 102 controls the transistor in the first impedance network 102 to be cut off based on the first original correction signal Zqpd0-Zqpd2, the transistor in the first impedance network 102 is in a cut-off state, thereby being able to reduce the capacitance on the input and output end DQ. When the first impedance network 102 controls the transistor in the first impedance network 102 to be in a conducting state based on the first original correction signal Zqpd0-Zqpd2, the transistor in the first impedance network 102 collectively corrects the resistance value of the first impedance network 102, thereby correcting the output impedance of the drive circuit, so as to be able to reduce the capacitance on the input and output end DQ within the range of the original output impedance, thereby improving the data transmission quality.

[0066] For example, when the first original correction signal Zqpd0-Zqpd2 is the second level signal, the first impedance network 102 controls the transistor in the first impedance network 102 to be cut off under the control of the second level signal. When the first original correction signal Zqpd0-Zqpd2 is the first level signal, the first impedance network 102 controls the transistor in the first impedance network 102 to be in a conducting state under the control of the first level signal. The level of the first level signal is greater than the level of the second level signal. For example, the first level signal is 1, and the second level signal is 0.

[0067] In some embodiments, the first control unit 101 includes a first pull-up transistor, a second pull-up transistor, and a third pull-up transistor. The first end of the first pull-up transistor, the first end of the second pull-up transistor, and the first end of the third pull-up transistor are connected to each other as the first end of the first control unit 101, and are connected to the first power supply end VDD. The control end of the first pull-up transistor, the control end of the second pull-up transistor, and the control end of the third pull-up transistor are connected to each other as the control end of the first control unit 101, and receive the first drive signal Pumain. The second end of the first pull-up transistor, the second end of the second pull-up transistor, and the second end of the third pull-up transistor are connected to each other as the second end of the first control unit 101, and are connected to the input and output end DQ. Figure 4As shown, the control terminal of the first pull-up transistor, the control terminal of the second pull-up transistor and the control terminal of the third pull-up transistor all receive the first driving signal Pumain. The first pull-up transistor, the second pull-up transistor and the third pull-up transistor control whether the first impedance network 102 connects the first power supply end VDD under the control of the first driving signal Pumain. The first terminal of each transistor can be a drain, and the second terminal can be a source. Of course, the first terminal of each transistor can also be a source, and the second terminal can be a drain.

[0068] The first impedance network 102 includes a fourth pull-up transistor, a fifth pull-up transistor and a sixth pull-up transistor. The first terminal of the fourth pull-up transistor is connected to the second terminal of the first pull-up transistor, the first terminal of the fifth pull-up transistor is connected to the second terminal of the second pull-up transistor, and the first terminal of the sixth pull-up transistor is connected to the second terminal of the third pull-up transistor. The second terminal of the fourth pull-up transistor, the second terminal of the fifth pull-up transistor and the second terminal of the sixth pull-up transistor are connected to each other as the second terminal of the first impedance network 102, and are connected to the input and output end DQ. The control terminal of the fourth pull-up transistor, the control terminal of the fifth pull-up transistor and the control terminal of the sixth pull-up transistor are connected as the control terminal of the first impedance network 102, and receive the first original correction signal Zqpu0-Zqpu2, for example, the control terminal of the fourth pull-up transistor receives the first original correction signal Zqpu0, the control terminal of the fifth pull-up transistor receives the first original correction signal Zqpu1, and the control terminal of the sixth pull-up transistor receives the first original correction signal Zqpu2.

[0069] Then, the first pull-up transistor controls whether the fourth pull-up transistor connects the first power supply end VDD under the control of the first driving signal Pumain, the second pull-up transistor controls whether the fifth pull-up transistor connects the first power supply end VDD under the control of the first driving signal Pumain, and the third pull-up transistor controls whether the sixth pull-up transistor connects the first power supply end VDD under the control of the first driving signal Pumain.

[0070] The fourth pull-up transistor is turned on by the first power supply terminal VDD, and the fourth pull-up transistor is turned on or turned off under the control of the first original correction signal Zqpu0. The fifth pull-up transistor is turned on by the first power supply terminal VDD, and the fifth pull-up transistor is turned on or turned off under the control of the first original correction signal Zqpu1. The sixth pull-up transistor is turned on by the first power supply terminal VDD, and the sixth pull-up transistor is turned on or turned off under the control of the first original correction signal Zqpu2. Therefore, from the perspective of the input and output terminal, the fourth pull-up transistor, the fifth pull-up transistor and the sixth pull-up transistor are in the on state or the off state. When the fourth pull-up transistor, the fifth pull-up transistor and / or the sixth pull-up transistor are in the off state, the capacitance on the input and output terminal DQ can be reduced. When the fourth pull-up transistor, the fifth pull-up transistor and / or the sixth pull-up transistor are in the on state, the resistance value of the first impedance network 102 can be adjusted.

[0071] In some embodiments, the sizes of the first pull-up transistor, the second pull-up transistor and the third pull-up transistor are in a geometric progression, for example, the size of the first pull-up transistor is W / 2*L, the size of the second pull-up transistor is W / L, and the size of the third pull-up transistor is 2*W / L, W is the width of the transistor channel, L is the length of the transistor channel, and W / L is the size of the transistor channel, that is, the width-length ratio. The sizes of the fourth pull-up transistor, the fifth pull-up transistor and the sixth pull-up transistor are in a geometric progression, so as to select the corresponding transistor to adjust the resistance value of the first impedance network 102, for example, the size of the fourth pull-up transistor is the same as that of the first pull-up transistor, the size of the fifth pull-up transistor is the same as that of the second pull-up transistor, and the size of the sixth pull-up transistor is the same as that of the third pull-up transistor.

[0072] In some embodiments, the driving circuit can further comprise a first driving module 103 and a third impedance network 104, the first driving module 103 being provided with a control terminal, a first terminal and a second terminal, and the third impedance network 104 being provided with a control terminal, a first terminal and a second terminal. The control terminal of the first driving module 103 receives a first driving signal Pumain, the first terminal of the first driving module 103 is connected to the first power terminal VDD, and the second terminal of the first driving module 103 is connected to the input / output terminal DQ. The control terminal of the third impedance network 104 receives a first target correction signal Zqpu3-Zqpu5, the first terminal of the third impedance network 104 is connected to the first power terminal VDD, and the second terminal of the third impedance network 104 is connected to the input / output terminal DQ. When the first driving module 103 is turned on under the control of the first driving signal Pumain, the first driving module 103 drives the input / output terminal DQ, and when the third impedance network 104 is turned on under the control of the first target correction signal Zqpu3-Zqpu5, the third impedance network 104 can correct the resistance value of the third impedance network 104 together with the first driving module 103, the first target correction signal Zqpu3-Zqpu5 is generated according to the third original correction signal and the first driving signal Pumain, the third original correction signal is a signal acting on the third impedance network 104 before the resistance value of the third impedance network 104 is corrected, and the first driving signal Pumain is a data output signal converted from parallel to serial inside the DRAM and generated through multiple stages of pre-driver. For example, when the first driving signal Pumain is a first level signal, the first target correction signal Zqpu3-Zqpu5 can be generated, so that the output impedance of the driving circuit can be corrected by the third impedance network 104 and the first driving module 103.

[0073] Therefore, the output impedance of the driving circuit can be adjusted by the first driving module 103, the third impedance network 104, the first control unit 101 and the first impedance network 102 together. For example, when the first driving signal Pumain is a first level signal, the first control unit 101 is turned on, and the first driving module 103 is turned on, at this time, if the first impedance network 102 is turned on under the control of the first original correction signal Zqpu0-Zqpu2, and the third impedance network 104 is turned on under the control of the first target correction signal Zqpu3-Zqpu5, the output impedance of the driving circuit can be adjusted by the first control unit 101, the first impedance network 102, the first driving module 103 and the third impedance network 104.

[0074] The first driving module 103 can include a seventh pull-up transistor, a control terminal of the seventh pull-up transistor serving as a control terminal of the first driving module 103, receiving a first driving signal Pumain, a first terminal of the seventh pull-up transistor serving as a first terminal of the first driving module 103, connected to a first power supply terminal VDD, a second terminal of the seventh pull-up transistor serving as a second terminal of the first driving module 103, connected to the input / output terminal DQ, the seventh pull-up transistor being configured to drive the input / output terminal DQ. The size of the seventh pull-up transistor can be 8*W / L.

[0075] The third impedance network 104 includes an eighth pull-up transistor, a ninth pull-up transistor, and a tenth pull-up transistor. Control terminals of the eighth pull-up transistor, the ninth pull-up transistor, and the tenth pull-up transistor serve as a control terminal of the third impedance network 104, receiving a first target correction signal Zqpu3-Zqpu5. First terminals of the eighth pull-up transistor, the ninth pull-up transistor, and the tenth pull-up transistor are connected to each other, serving as a first terminal of the third impedance network 104, connected to the first power supply terminal VDD. Second terminals of the eighth pull-up transistor, the ninth pull-up transistor, and the tenth pull-up transistor are connected to each other, serving as a second terminal of the third impedance network 104, connected to the input / output terminal DQ. The eighth transistor, the ninth transistor, and / or the tenth transistor are configured to adjust the resistance value of the third impedance network 104, and further adjust the output impedance of the driving circuit.

[0076] The sizes of the eighth pull-up transistor, the ninth pull-up transistor, and the tenth pull-up transistor form a geometric progression, so that the corresponding transistors can be selected to adjust the resistance value of the third impedance network 104. For example, the size of the eighth pull-up transistor is 2*W / L, the size of the ninth pull-up transistor is 4*W / L, and the size of the tenth pull-up transistor is 8*W / L.

[0077] In some embodiments, the driving circuit further includes a second control unit 201 and a second impedance network 202, the second control unit 201 being provided with a control terminal, a first terminal, and a second terminal, and the second impedance network 202 being provided with a control terminal, a first terminal, and a second terminal. The control terminal of the second control unit 201 receives a second driving signal Pdmain, the first terminal of the second control unit 201 is connected to the second terminal of the second impedance network 202, and the second terminal of the second control unit 201 is connected to a second power supply terminal VSS. The control terminal of the second impedance network 202 receives a second original correction signal Zqpd0-Zqpd2, and the first terminal of the second impedance network 202 is connected to the input / output terminal DQ.

[0078] The second control unit 201 is configured to control whether the transistor in the second impedance network 202 is connected to the second power supply terminal VSS. The second impedance network 202 controls the state of the transistor in the second impedance network 202 based on the second original correction signal Zqpd0-Zqpd2 to correct the resistance value of the second impedance network 202. When the second drive signal Pdmain is the second level signal, the second control unit 201 controls the transistor in the second impedance network 202 to be connected to the second power supply terminal VSS under the control of the second drive signal Pdmain. At this time, the transistor in the second impedance network 202 can be in a conducting state or a non-conducting state from the perspective of the input / output terminal DQ. When the second impedance network 202 controls the transistor in the second impedance network 202 to be disconnected based on the second original correction signal Zqpd0-Zqpd2, the transistor in the second impedance network 202 is in a non-conducting state, which can further reduce the capacitance on the input / output terminal DQ. When the first impedance network 102 controls the transistor in the second impedance network 202 to be in a conducting state based on the second original correction signal Zqpd0-Zqpd2, the transistor in the second impedance network 202 collectively corrects the resistance value of the second impedance network 202, thereby correcting the output impedance of the drive circuit.

[0079] For example, when the second original correction signal Zqpd0-Zqpd2 is the first level signal, the second impedance network 202 controls the transistor in the second impedance network 202 to be disconnected under the control of the first level signal. When the second original correction signal Zqpd0-Zqpd2 is the second level signal, the second impedance network 202 controls the transistor in the second impedance network 202 to be in a conducting state under the control of the second level signal.

[0080] In some embodiments, when the first power supply terminal VDD provides a power supply voltage and the second power supply terminal VSS provides a ground voltage, the first control unit 101 and the first impedance network 102 are configured to pull up the output impedance of the drive circuit, and the second control unit 201 and the second impedance network 202 are configured to pull down the output impedance of the drive circuit. When the first power supply terminal VDD provides a ground voltage and the second power supply terminal VSS provides a power supply voltage, the first control unit 101 and the first impedance network 102 are configured to pull down the output impedance of the drive circuit, and the second control unit 201 and the second impedance network 202 are configured to pull up the output impedance of the drive circuit.

[0081] In some embodiments, the second control unit 201 includes a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor. The first end of the first pull-down transistor, the first end of the second pull-down transistor, and the first end of the third pull-down transistor are connected to the second end of the second impedance network 202 as the first end of the second control unit 201. The second end of the first pull-down transistor, the second end of the second pull-down transistor, and the second end of the third pull-down transistor are connected to each other as the second end of the second control unit 201, and are connected to the second power supply end VSS. The control end of the first pull-down transistor, the control end of the second pull-down transistor, and the control end of the third pull-down transistor receive the second drive signal Pdmain as the control end of the second control unit 201, and each of the control ends receives the second drive signal Pdmain. The first pull-down transistor, the second pull-down transistor, and the third pull-down transistor control whether the second impedance network 202 is connected to the second power supply end VSS under the control of the second drive signal Pdmain.

[0082] The second impedance network 202 includes a fourth pull-down transistor, a fifth pull-down transistor, and a sixth pull-down transistor. The first end of the fourth pull-down transistor, the first end of the fifth pull-down transistor, and the first end of the sixth pull-down transistor are connected to each other as the first end of the second impedance network 202, and are connected to the input / output end DQ. The second end of the fourth pull-down transistor is connected to the first end of the first pull-down transistor, the second end of the fifth pull-down transistor is connected to the first end of the second pull-down transistor, and the second end of the sixth pull-down transistor is connected to the first end of the third pull-down transistor. The control end of the fourth pull-down transistor, the control end of the fifth pull-down transistor, and the control end of the sixth pull-down transistor receive the second original correction signal Zqpd0-Zqpd2 as the control end of the second impedance network 202, for example, the control end of the fourth pull-down transistor receives the second original correction signal Zqpd0, the control end of the fifth pull-down transistor receives the second original correction signal Zqpd1, and the control end of the sixth pull-down transistor receives the second original correction signal Zqpd2.

[0083] Therefore, the first pull-down transistor controls whether the fourth pull-down transistor is connected to the second power supply end VSS under the control of the second drive signal Pdmain, the second pull-down transistor controls whether the fifth pull-down transistor is connected to the second power supply end VSS under the control of the second drive signal Pdmain, and the third pull-down transistor controls whether the sixth pull-down transistor is connected to the second power supply end VSS under the control of the second drive signal Pdmain.

[0084] The fourth pull-down transistor is turned on when the second power supply end VSS is turned on, and the fourth pull-down transistor is turned on or turned off under the control of the second original correction signal Zqpd0, the fifth pull-down transistor is turned on or turned off under the control of the second original correction signal Zqpd1, and the sixth pull-down transistor is turned on or turned off under the control of the second original correction signal Zqpd2. Therefore, from the perspective of the input and output end, the fourth pull-down transistor, the fifth pull-down transistor and the sixth pull-down transistor are in the on state or the off state. When the fourth pull-down transistor, the fifth pull-down transistor and / or the sixth pull-down transistor are in the off state, the capacitance on the input and output end DQ can be reduced, and when the fourth pull-down transistor, the fifth pull-down transistor and / or the sixth pull-down transistor are in the on state, the resistance value of the second impedance network 202 can be adjusted.

[0085] In some embodiments, the sizes of the first pull-down transistor, the second pull-down transistor and the third pull-down transistor are in a geometric progression, for example, the size of the first pull-down transistor is W / 2*L, the size of the second pull-down transistor is W / L, and the size of the third pull-down transistor is 2*W / L, W is the width of the transistor channel, L is the length of the transistor channel, and W / L is the size of the transistor channel, that is, the width-length ratio. The sizes of the fourth pull-down transistor, the fifth pull-down transistor and the sixth pull-down transistor are in a geometric progression, so as to select the corresponding transistor to adjust the resistance of the first impedance network 102, for example, the size of the fourth pull-down transistor is the same as that of the first pull-down transistor, the size of the fifth pull-down transistor is the same as that of the second pull-down transistor, and the size of the sixth pull-down transistor is the same as that of the third pull-down transistor.

[0086] In some embodiments, the driving circuit can further comprise a second driving module 203 and a fourth impedance network 204, the second driving module 203 being provided with a control terminal, a first terminal and a second terminal, and the fourth impedance network 204 being provided with a control terminal, a first terminal and a second terminal. The control terminal of the second driving module 203 receives a second driving signal Pdmain, the first terminal of the second driving module 203 is connected to the input / output terminal DQ, and the second terminal of the second driving module 203 is connected to the second power supply terminal VSS. The control terminal of the fourth impedance network 204 receives a second target correction signal Zqpd3-Zqpd5, the first terminal of the fourth impedance network 204 is connected to the input / output terminal DQ, and the second terminal of the fourth impedance network 204 is connected to the second power supply terminal VSS. When the second driving module 203 is turned on under the control of the second driving signal Pdmain, the second driving module 203 drives the input / output terminal DQ, and when the fourth impedance network 204 is turned on under the control of the second target correction signal Zqpd3-Zqpd5, the fourth impedance network 204 can correct the resistance value of the fourth impedance network 204 together with the second driving module 203, the second target correction signal Zqpd3-Zqpd5 is generated according to the fourth original correction signal and the second driving signal Pdmain, the second driving signal Pdmain is a data output signal converted from parallel to serial inside the DRAM and generated through multiple stages of pre-driver, and the fourth original correction signal is a signal acting on the fourth impedance network 204 before the resistance value of the fourth impedance network 204 is corrected. For example, when the second driving signal Pdmain is a second level signal, the second target correction signal Zqpd3-Zqpd5 can be generated, so that the output impedance of the driving circuit can be corrected by the fourth impedance network 204 and the second driving module 203.

[0087] Thus, the output impedance of the driving circuit can be adjusted by the second driving module 203, the fourth impedance network 204, the second control unit 201 and the second impedance network 202 together. For example, when the second driving signal Pdmain is a second level signal, the second control unit 201 is turned on, and the second driving module 203 is turned on, at this time, if the second impedance network 202 is turned on under the control of the second original correction signal Zqpd0-Zqpd2, and the fourth impedance 204 is turned on under the control of the second target correction signal Zqpd3-Zqpd5, the output impedance of the driving circuit can be adjusted by the second control unit 201, the second impedance network 202, the second driving module 203 and the fourth impedance network 204.

[0088] The second driving module 203 can include a seventh pull-down transistor, a control end of the seventh pull-down transistor serving as a control end of the second driving module 203, receiving a second driving signal Pdmain, a first end of the seventh pull-down transistor serving as a first end of the second driving module 203, connected to the input and output end DQ, a second end of the seventh pull-down transistor serving as a second end of the second driving module 203, connected to the second power supply end VSS, the seventh pull-down transistor being configured to drive the input and output end DQ. The size of the seventh pull-down transistor can be 8*W / L.

[0089] The fourth impedance network 204 includes an eighth pull-down transistor, a ninth pull-down transistor, and a tenth pull-down transistor. A control end of the eighth pull-down transistor, a control end of the ninth pull-down transistor, and a control end of the tenth pull-down transistor serve as a control end of the fourth impedance network 204, receiving a second target correction signal Zqpd3-Zqpd5. A first end of the eighth pull-down transistor, a first end of the ninth pull-down transistor, and a first end of the tenth pull-down transistor are connected to each other, serving as a first end of the fourth impedance network 204, connected to the input and output end DQ. A second end of the eighth pull-down transistor, a second end of the ninth pull-down transistor, and a second end of the tenth pull-down transistor are connected to each other, serving as a second end of the fourth impedance network 204, connected to the second power supply end VSS. The eighth transistor, the ninth transistor, and / or the tenth transistor are configured to adjust the resistance value of the fourth impedance network 204, and further adjust the output impedance of the driving circuit.

[0090] The sizes of the eighth pull-down transistor, the ninth pull-down transistor, and the tenth pull-down transistor form a geometric progression, so that the corresponding transistors can be selected to adjust the resistance value of the fourth impedance network 204. For example, the size of the eighth pull-down transistor is 2*W / L, the size of the ninth pull-down transistor is 4*W / L, and the size of the tenth pull-down transistor is 8*W / L.

[0091] Reference Figure 4 As shown, the driving circuit can further include a pull-down resistor R, a first end of the pull-down resistor R being connected to the input and output end DQ, a second end of the pull-down resistor R being connected to the first end of the second impedance network 202, the pull-down resistor R being configured to increase the output impedance of the driving circuit, and further adjust the output impedance of the driving circuit.

[0092] In the technical solution, the first control unit controls the transistor in the first impedance network to turn on the first power supply end under the control of the first drive signal; when the transistor in the first impedance network is controlled to turn on by the first original correction signal, the transistor in the first impedance network can adjust the resistance value of the first impedance network; when the transistor in the first impedance network is controlled to turn off by the first original correction signal, the transistor in the first impedance network is in an off state from the input and output end, so that the capacitance on the input and output end in the original output impedance range can be reduced, and the data transmission quality can be improved.

[0093] An embodiment of the present disclosure further provides a semiconductor memory comprising the driving circuit.

[0094] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features. The modification or replacement does not make the essence of the corresponding technical solution deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A drive circuit characterized by comprising: The drive circuit comprises: a first control unit, a control end of which receives a first drive signal, a first end of which is connected to a first power supply end, and a second end of which is connected to a first end of a first impedance network, for controlling whether a transistor in the first impedance network is connected to the first power supply end; the first power supply end provides a power supply voltage; the first impedance network, a control end of which receives a first original correction signal, and a second end of which is connected to an input / output end, for controlling a state of a transistor in the first impedance network based on the first original correction signal to correct a resistance value of the first impedance network.

2. The drive circuit according to claim 1, characterized by The drive circuit further comprises: a second control unit, a control end of which receives a second drive signal, a first end of which is connected to a second end of a second impedance network, and a second end of which is connected to a second power supply end, for controlling whether a transistor in the second impedance network is connected to the second power supply end; the second power supply end provides a ground voltage; a second impedance network, a control end of which receives a second original correction signal, and a first end of which is connected to the input / output end, for controlling a state of a transistor in the second impedance network based on the second original correction signal to correct a resistance value of the second impedance network.

3. The drive circuit according to claim 1, characterized by The first control unit comprises: a first pull-up transistor, a second pull-up transistor, and a third pull-up transistor; first ends of the first pull-up transistor, the second pull-up transistor, and the third pull-up transistor are connected to each other as a first end of the first control unit; control ends of the first pull-up transistor, the second pull-up transistor, and the third pull-up transistor are connected to each other as a control end of the first control unit.

4. The drive circuit according to claim 3, characterized in that, The first impedance network comprises: a fourth pull-up transistor, a fifth pull-up transistor, and a sixth pull-up transistor; a second end of the fourth pull-up transistor is connected to a second end of the first pull-up transistor, a second end of the fifth pull-up transistor is connected to a second end of the second pull-up transistor, and a second end of the sixth pull-up transistor is connected to a second end of the third pull-up transistor; second ends of the fourth pull-up transistor, the fifth pull-up transistor, and the sixth pull-up transistor are connected to each other as a second end of the first impedance network; control ends of the fourth pull-up transistor, the fifth pull-up transistor, and the sixth pull-up transistor are connected to each other as a control end of the first impedance network.

5. The drive circuit according to claim 4, characterized in that, sizes of the first pull-up transistor, the second pull-up transistor, and the third pull-up transistor form a geometric progression, and sizes of the fourth pull-up transistor, the fifth pull-up transistor, and the sixth pull-up transistor form a geometric progression.

6. The drive circuit according to claim 2, characterized by The second control unit comprises: a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor; first ends of the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor are connected to each other as a first end of the second control unit; second ends of the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor are connected to each other as a second end of the second control unit; The control end of the first pull-down transistor, the control end of the second pull-down transistor and the control end of the third pull-down transistor are control ends of the second control unit.

7. The drive circuit according to claim 6, characterized in that, The second impedance network comprises a fourth pull-down transistor, a fifth pull-down transistor and a sixth pull-down transistor. The first end of the fourth pull-down transistor, the first end of the fifth pull-down transistor and the first end of the sixth pull-down transistor are connected to each other and serve as a first end of the second impedance network. The second end of the fourth pull-down transistor is connected to the first end of the first pull-down transistor, the second end of the fifth pull-down transistor is connected to the first end of the second pull-down transistor, and the second end of the sixth pull-down transistor is connected to the first end of the third pull-down transistor. The control end of the fourth pull-down transistor, the control end of the fifth pull-down transistor and the control end of the sixth pull-down transistor serve as control ends of the second impedance network.

8. The drive circuit according to claim 7, characterized in that, The first pull-down transistor, the second pull-down transistor and the third pull-down transistor form a geometric progression, and the fourth pull-down transistor, the fifth pull-down transistor and the sixth pull-down transistor form a geometric progression.

9. The drive circuit of claim 1, wherein, The driving circuit further comprises: The first driving module, whose control end receives the first driving signal, whose first end is connected to the first power supply end and whose second end is connected to the input / output end, is used to drive the input / output end; The third impedance network, whose control end receives a first target correction signal, whose first end is connected to the first power supply end and whose second end is connected to the input / output end, is used to correct the resistance value of the third impedance network under the control of the first target correction signal, and the first target correction signal is generated according to a third original correction signal and the first driving signal, and the first target correction signal is generated according to the third original correction signal when the first driving signal is a first level signal. The first driving module, the third impedance network, the first control unit and the first impedance network jointly adjust the output impedance of the driving circuit.

10. The drive circuit according to claim 9, characterized in that, The first driving module comprises: The seventh pull-up transistor, whose control end serves as the control end of the first driving module and is used to receive the first driving signal, whose first end serves as the first end of the first driving module and whose second end serves as the second end of the first driving module.

11. The drive circuit according to claim 9, characterized by The third impedance network comprises an eighth pull-up transistor, a ninth pull-up transistor and a tenth pull-up transistor. The control end of the eighth pull-up transistor, the control end of the ninth pull-up transistor and the control end of the tenth pull-up transistor serve as the control end of the third impedance network and are used to receive the first target correction signal. The first end of the eighth pull-up transistor, the first end of the ninth pull-up transistor and the first end of the tenth pull-up transistor are connected to each other and serve as the first end of the third impedance network. The second end of the eighth pull-up transistor, the second end of the ninth pull-up transistor and the second end of the tenth pull-up transistor are connected to each other and serve as the second end of the third impedance network.

12. The drive circuit of claim 2, wherein, The driving circuit further comprises: a second driving module, a control terminal of which receives the second driving signal, a first terminal of which is connected to the input / output terminal, and a second terminal of which is connected to the second power terminal, for driving the input / output terminal; a fourth impedance network, a control terminal of which receives a second target correction signal, a first terminal of which is connected to the input / output terminal, and a second terminal of which is connected to the second power terminal, for correcting the resistance value of the fourth impedance network under the control of the second target correction signal, the second target correction signal being generated according to a fourth original correction signal and the second driving signal; when the second driving signal is a second level signal, the second target correction signal is generated according to the fourth original correction signal; the second driving module, the fourth impedance network, the second control unit and the second impedance network jointly adjust the output impedance of the driving circuit.

13. The drive circuit of claim 12, wherein, the second driving module comprises: a seventh pull-down transistor, a control terminal of which serves as the control terminal of the second driving module, for receiving the second driving signal, a first terminal of which serves as the first terminal of the second driving module, and a second terminal of which serves as the second terminal of the second driving module.

14. The drive circuit of claim 12, wherein, the fourth impedance network comprises an eighth pull-down transistor, a ninth pull-down transistor and a tenth pull-down transistor; control terminals of the eighth, ninth and tenth pull-down transistors serve as the control terminal of the fourth impedance network, for receiving the second target correction signal; first terminals of the eighth, ninth and tenth pull-down transistors are connected to each other, serving as the first terminal of the fourth impedance network; second terminals of the eighth, ninth and tenth pull-down transistors are connected to each other, serving as the second terminal of the fourth impedance network.

15. A semiconductor memory, characterized by comprising: the driving circuit of any one of claims 1-14.

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