TR Component Protection Logic Circuit, Control Logic and Transceiver Control System

Abstract

The present invention provides a protection logic circuit, a control logic, and a transceiver control system for a TR component, including: a counter, a comparator, a first AND gate, and a locking output module; one input terminal of the first AND gate is connected to a TR transceiver control signal input by a user, and the other input terminal is connected to the output terminal of the comparator; the output signal of the first AND gate is respectively input to the input terminal of the locking output module, one input terminal of the comparator, the forward counting control terminal of the counter, and the reverse counting control terminal of the counter; the output terminal of the counter is connected to the other input terminal of the comparator; the locking output module is connected to the TR component; when the output signal of the first AND gate is at a high level, the counter counts up by S1; when the output signal of the first AND gate is at a low level, the counter counts down by S2; the comparator is used to compare whether the output value of the counter reaches the maximum continuous emission time Smax allowed by the TR component.

Description

Technical Field

[0001] The present invention relates to the technical field of transceiver control and protection of TR components, and more specifically, to a protection logic circuit, a control logic, and a transceiver control system for TR components. Background Art

[0002] TR components are the core components of active phased arrays. They are usually expensive and easily damaged. To avoid the situation of power components burning out in the TR component during operation, there are usually some analog protection circuits or monitoring circuits inside the TR component to protect the power-on sequence, temperature, etc. inside the component. If an abnormality occurs, the TR component will stop working. However, for the purpose of flexible use, the transceiver state control of the TR component is completely the responsibility of the user. If the user is negligent or makes a logical error during debugging or use, it is very easy to cause the TR component to burn out due to overload.

[0003] The situations where the TR component is burned out caused by the input of transceiver signals can be divided into two types. One is that the TR component is in the transmit state for a long time; the second is that the duty cycle of the transceiver signal is too high to meet the heat dissipation requirements of the TR component; both situations will cause the TR component to burn out. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems in the prior art that the transceiver state control of the TR component is completely the responsibility of the user, lacking protection for the transceiver control of the TR component, and when the TR component is in the transmit state for a long time or the duty cycle of the transceiver signal is too high, it is easy to cause the TR component to burn out.

[0005] To this end, the first aspect of the present invention provides a protection logic circuit for TR components.

[0006] The second aspect of the present invention provides a control logic for the protection logic circuit of the TR component.

[0007] The third aspect of the present invention provides a transceiver control system for TR components.

[0008] The present invention provides a protection logic circuit for TR components, including: a counter, a comparator, a first AND gate, and a locked output module;

[0009] One input terminal of the first AND gate is connected to the TR transceiver control signal input by the user, and the other input terminal is connected to the output terminal of the comparator; the output signal of the first AND gate is respectively input to the input terminal of the locked output module, one input terminal of the comparator, the forward counting control terminal of the counter, and the reverse counting control terminal of the counter;

[0010] The output terminal of the counter is connected to the other input terminal of the comparator;

[0011] The locking output module is connected to the TR component and is used to pull down the transceiver control signal input to the TR component when there is a reason that can easily cause the TR component to be overloaded and burned out.

[0012] When the output signal of the first AND gate is at a high level, the counter counts up by S1; when the output signal of the first AND gate is at a low level, the counter counts down by S2.

[0013] The comparator is used to compare whether the output value of the counter reaches the maximum continuous emission time Smax allowed by the TR component.

[0014] A protection logic circuit for a TR component according to the above technical solution of the present invention may further have the following additional technical features:

[0015] In the above technical solution, the value S1 when the counter counts up and the value S2 when the counter counts down should satisfy:

[0016]

[0017] where X is the maximum allowable duty cycle for the TR component not to be damaged.

[0018] In the above technical solution, when the comparator compares the output value of the counter with the maximum continuous emission time Smax allowed by the TR component, when the output value of the counter is greater than or equal to Smax, the comparator outputs a low level; when the output value of the counter is less than Smax, the comparator outputs a high level.

[0019] In the above technical solution, the output signal of the first AND gate is input to the reverse counting control terminal of the counter after passing through a NOT gate.

[0020] In the above technical solution, the TR transceiver control signal input by the user is generated by a logic control circuit, and the Clk input terminal of the counter is connected to the clock signal input to the logic control circuit.

[0021] In the above technical solution, it further includes a transceiver control signal input module, the input terminal of the transceiver control signal input module is connected to the output terminal of the logic control circuit, and the output terminal is connected to one input terminal of the first AND gate.

[0022] In any of the above technical solutions, it further includes a second AND gate, the output terminal of the first AND gate is connected to one input terminal of the second AND gate, and the other input terminal of the second AND gate is connected to an external clock valid flag signal; the output terminal of the second AND gate is respectively connected to the input terminal of the locking output module, one input terminal of the comparator, the forward counting control terminal of the counter, and the reverse counting control terminal of the counter.

[0023] The present invention also provides a control logic for a TR component protection logic circuit, which is applied to a TR component protection logic circuit as described in any one of the above technical solutions, and includes the following processes:

[0024] A1. Start the TR component protection logic circuit and reset the counter to zero;

[0025] A2. Monitor the TR transceiver control level output by the TR component protection logic circuit;

[0026] A3. Determine whether the TR transceiver control level output by the TR component protection logic circuit in A2 is high or low. When the output signal is high, the counter count is increased by S1; when the output signal is low, the counter count is decreased by S2;

[0027] A4. Continue to monitor the TR transceiver control level output by the TR component protection logic circuit;

[0028] A5. Determine whether the TR transceiver control level output by the TR component protection logic circuit in A4 is high or low. When the output signal is high, proceed to A6; when the output signal is low, proceed to A7;

[0029] A6. Determine whether the output value of the counter is greater than the maximum continuous emission time Smax allowed by the TR component. If so, set the level of the TR transceiver control signal input to the TR component to low and return to A2; if not, maintain the level of the TR transceiver control signal input to the TR component and return to A2;

[0030] A7. Determine whether the output value of the counter is greater than 0. If so, set the level of the TR transceiver control signal input to the TR component to low and return to A2; if not, maintain the level of the TR transceiver control signal input to the TR component and return to A2.

[0031] The present invention also provides a TR component transceiver control system, including: a logic control circuit, a TR component, and a TR component protection logic circuit as described in any one of the above technical solutions;

[0032] The logic control circuit is used to generate a TR transceiver control signal and is connected to the TR component protection logic circuit;

[0033] The TR component protection logic circuit is used to automatically turn off the transmission when the TR component transceiver control transmission time is too long; automatically perform transceiver control correction when the TR component transceiver control does not meet the duty cycle requirement; prevent the TR component from burning out; and is connected to the input end of the TR component.

[0034] In the above technical solution, the logic control circuit accesses an external clock signal and an external clock valid flag signal.

[0035] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are as follows:

[0036] The present invention can realize the correction of the transceiver control logic of the TR component, thereby realizing real-time protection of the TR component in the TR control logic. In different working environments, it can prevent the TR component from being burned while not affecting the correct output of the TR. Specifically:

[0037] 1. By adding a logic protection circuit, when the transceiver control transmission time of the TR component is too long, the transmission is automatically turned off to prevent the TR component from being burned;

[0038] 2. By adding a logic protection circuit, when the transceiver control of the TR component does not meet the duty cycle requirement, the transceiver control is automatically corrected to prevent the TR component from being burned due to an excessive duty cycle;

[0039] 3. When the transceiver control meets the requirements, the logic circuit does not affect the original transceiver control.

[0040] The structure of the present invention is simple and very easy to implement whether using discrete components or logically implementing in an FPGA. It does not occupy resources. After adding this protection circuit between the user transceiver control and the TR transceiver control, there is no impact on the safe user transceiver control input. If the transceiver control continues to be too high, the circuit will forcibly pull down the transceiver control input of the TR component until the heat of the TR component dissipates and then automatically resumes to the user control. When the duty cycle of the transceiver control input is too high, the duty cycle will be automatically changed to a range acceptable to the TR component, thereby protecting the TR component from damage. Adding this logic in actual research and development and production can avoid the situation where the TR component is damaged due to transceiver control.

[0041] The additional aspects and advantages of the present invention will become apparent in the following description part or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, wherein:

[0043] Figure 1 is the circuit schematic diagram of a TR component protection logic circuit according to an embodiment of the present invention;

[0044] Figure 2 is the traditional TR component logic control circuit;

[0045] Figure 3 is the flowchart of the control logic of a TR component protection logic circuit according to an embodiment of the present invention;

[0046] Figure 4It is the output waveform diagram of a TR component protection logic circuit in the first specific embodiment of the present invention under normal input conditions;

[0047] Figure 5 It is the output waveform diagram of a TR component protection logic circuit in the first specific embodiment of the present invention under abnormal input clock conditions;

[0048] Figure 6 It is the output waveform diagram of a TR component protection logic circuit in the first specific embodiment of the present invention under abnormal duty cycle input conditions;

[0049] Figure 7 It is the output waveform diagram of a TR component protection logic circuit in the first specific embodiment of the present invention under long - term high - level input conditions. Detailed implementation manners

[0050] In order to more clearly understand the above - mentioned objects, features and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

[0051] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0052] Next, refer to Figures 1 to 7 to describe a TR component protection logic circuit, a control logic and a transceiver control system provided according to some embodiments of the present invention.

[0053] Some embodiments of the present application provide a TR component protection logic circuit.

[0054] As Figures 1 to 3 shown, the first embodiment of the present invention proposes a TR component protection logic circuit, including: a counter, a comparator, a first AND gate &1 and a lock - out output module TR_lockout;

[0055] One input terminal of the first AND gate &1 is connected to the TR transceiver control signal input by the user, and the other input terminal is connected to the output terminal of the comparator; the output signal of the first AND gate &1 is respectively input to the input terminal of the lock - out output module TR_lockout, one input terminal of the comparator, the forward counting control terminal UP en of the counter and the reverse counting control terminal DOWNen of the counter;

[0056] The output terminal of the counter is connected to the other input terminal of the comparator;

[0057] The locking output module TR_lockout is connected to the TR component and is used to pull down the transceiver control signal input to the TR component when there are reasons that are likely to cause the TR component to be overloaded and burned out.

[0058] When the output signal of the first AND gate &1 is at a high level, the counter increments by S1; when the output signal of the first AND gate &1 is at a low level, the counter decrements by S2.

[0059] The comparator is used to compare whether the output value of the counter reaches the maximum continuous emission time Smax allowed by the TR component.

[0060] In this embodiment, when both input terminals of the first AND gate &1 are at a high level, the output of the first AND gate &1 is at a high level, indicating that the transceiver control signal meets the requirements of the TR component. The requirements include the longest working time, duty cycle, etc. The locking output module TR_lockout transmits the transceiver control signal to the TR component; when either of the two input terminals of the first AND gate &1 is at a low level, the output of the first AND gate &1 is at a low level, indicating that the transceiver control signal does not meet the requirements of the TR component. The locking output module TR_lockout forcibly pulls down the transceiver control signal, thus ensuring that the TR component will not burn out.

[0061] The second embodiment of the present invention proposes a protection logic circuit for a TR component, and on the basis of the first embodiment, as Figures 1 to 3 shown, the value S1 when the counter increments and the value S2 when the counter decrements should satisfy:

[0062]

[0063] where X is the maximum allowable duty cycle for the TR component not to be damaged.

[0064] In this embodiment, the duty cycle of the TR control signal can be adjusted by the ratio of the increase and decrease of the counter, that is, the ratio of S2 and S1.

[0065] The third embodiment of the present invention proposes a protection logic circuit for a TR component, and on the basis of any of the above embodiments, as Figures 1 to 3 shown, when the comparator compares the output value of the counter with the maximum continuous emission time Smax allowed by the TR component, when the output value of the counter is greater than or equal to Smax, the comparator outputs a low level; when the output value of the counter is less than Smax, the comparator outputs a high level.

[0066] The fourth embodiment of the present invention proposes a protection logic circuit for a TR component, and on the basis of any of the above embodiments, as Figures 1 to 3As shown, the output signal of the first AND gate is input to the reverse counting control terminal of the counter after passing through a NOT gate. The NOT gate is set at the reverse counting control terminal of the counter, indicating that the low level is the effective input state.

[0067] The fifth embodiment of the present invention proposes a protection logic circuit for a TR component, and on the basis of any of the above embodiments, as Figures 1 to 3 shown, the TR transceiver control signal input by the user is generated by a logic control circuit. The Clk input terminal of the counter is connected to the clock signal input to the logic control circuit to ensure the accuracy of timing and clock synchronization. The Clk input terminal of the counter can also be connected to other clock sources.

[0068] The sixth embodiment of the present invention proposes a protection logic circuit for a TR component, and on the basis of any of the above embodiments, as Figures 1 to 3 shown, it further includes a transceiver control signal input module TR in. The input terminal of the transceiver control signal input module TR in is connected to the output terminal of the logic control circuit, and the output terminal is connected to one input terminal of the first AND gate.

[0069] The seventh embodiment of the present invention proposes a protection logic circuit for a TR component, and on the basis of any of the above embodiments, as Figures 1 to 3 shown, it further includes a second AND gate &2. The output terminal of the first AND gate &1 is connected to one input terminal of the second AND gate &2. The other input terminal of the second AND gate &2 is connected to an external clock valid flag signal Clk lock to prevent logic failure caused by clock failure. The output terminal of the second AND gate &2 is respectively connected to the input terminal of the lock output module TR_lockout, one input terminal of the comparator, the forward counting control terminal UP en of the counter, and the reverse counting control terminal DOWN en of the counter.

[0070] In this embodiment, the output signal of the first AND gate &1 is input to the input terminal of the lock output module TR_lockout, one input terminal of the comparator, the forward counting control terminal UP en of the counter, and the reverse counting control terminal DOWN en of the counter after performing AND logic with the external clock valid flag signal Clk lock. This is used to prevent logic failure caused by clock failure.

[0071] The eighth embodiment of the present invention proposes a control logic for a protection logic circuit of a TR component, as Figure 3 shown, which is applied to a protection logic circuit of a TR component as described in any one of the above embodiments, and includes the following processes:

[0072] A1. Start the protection logic circuit of the TR component, and the counter is reset to zero;

[0073] A2. Monitor the TR transceiver control level output by the TR component protection logic circuit;

[0074] A3. Determine whether the TR transceiver control level output by the TR component protection logic circuit in A2 is high or low. When the output signal is high, the counter counts up by S1; when the output signal is low, the counter counts down by S2;

[0075] A4. Continue to monitor the TR transceiver control level output by the TR component protection logic circuit;

[0076] A5. Determine whether the TR transceiver control level output by the TR component protection logic circuit in A4 is high or low. When the output signal is high, perform A6; when the output signal is low, perform A7;

[0077] A6. Determine whether the output value of the counter is greater than the maximum continuous transmission time Smax allowed by the TR component; if so, set the level of the TR transceiver control signal input to the TR component to low and return to A2; if not, keep the level of the TR transceiver control signal input to the TR component and return to A2;

[0078] A7. Determine whether the output value of the counter is greater than 0; if so, set the level of the TR transceiver control signal input to the TR component to low and return to A2; if not, keep the level of the TR transceiver control signal input to the TR component and return to A2.

[0079] In this embodiment, when the system is just powered on, since the external clock valid flag Clk_lock has not been set to high level, the TR transceiver control signal is pulled low by the protection logic circuit. When the system enters the working state, the protection logic circuit will detect the level state of the TR transceiver control signal. When it is high level, the counter increases; when it is low level, the counter decreases. The duty cycle of the TR control signal can be adjusted by the increase and decrease ratio. When the counter reaches the maximum occurrence duration Smax allowed by the TR component, the TR transceiver control signal is pulled low by the protection logic circuit, thus ensuring that the TR component will not burn out.

[0080] The ninth embodiment of the present invention proposes a TR component transceiver control system, and on the basis of any of the above embodiments, as Figures 1 to 3 shown, it includes: a logic control circuit, a TR component, and a TR component protection logic circuit as described in any one of the above embodiments;

[0081] The logic control circuit is used to generate a TR transceiver control signal and is connected to the TR component protection logic circuit; the logic control circuit accesses an external clock signal and an external clock valid flag signal.

[0082] The TR component protection logic circuit is used to automatically turn off the transmission when the TR component transceiver control transmission time is too long; when the TR component transceiver control does not meet the duty cycle requirement, automatically perform transceiver control correction; and is connected to the input end of the TR component; to prevent the TR component from burning out.

[0083] In the first specific embodiment of the present invention, a TR protection logic circuit with a clock of 100 MHz, a continuous transmission time less than 120 us, and a duty cycle less than 33% is designed, and the logic is implemented in VHDL language. The effect on the transceiver control is as Figures 4 to 7 shown, Figures 4 to 7 The waveform display in [] is based on the same coordinate system.

[0084] As Figure 4 shown, when the TR transceiver control signal is input under normal duty cycle conditions, the output of TR_lockout is consistent with the TR transceiver control signal, and the logic circuit does not affect the original transceiver control.

[0085] As Figure 5 shown, when the clock is unlocked, the monitoring logic fails, and at this time the output of TR_lockout is low level to protect the TR component. In this way, during the power-on period of the circuit, the TR component can also be protected from burning out.

[0086] As Figure 6 shown, when the duty cycle of the TR transceiver control signal input is too high, the output of TR_lockout is a signal with the maximum allowable duty cycle. That is, to ensure there is an output and also protect the TR component from burning out.

[0087] As Figure 7 shown, when the TR transceiver control signal input is pulled high for a long time, after the counter reaches the maximum occurrence duration Smax allowed by the TR component, that is, the highest holding time of 120 us, the output of TR_lockout becomes low level. Automatically protect the TR component.

[0088] In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0089] Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A protection logic circuit for a TR component, characterized in that, Comprising: a counter, a comparator, a first AND gate, and a locking output module; One input terminal of the first AND gate is connected to the TR transceiver control signal input by the user, and the other input terminal is connected to the output terminal of the comparator; the output signal of the first AND gate is respectively input to the input terminal of the locking output module, one input terminal of the comparator, the forward counting control terminal of the counter, and the reverse counting control terminal of the counter; The output terminal of the counter is connected to the other input terminal of the comparator; The locking output module is connected to the TR component. When any one of the two input terminals of the first AND gate is at a low level, the output of the first AND gate is at a low level, and the locking output module pulls down the level of the transceiver control signal input to the TR component; When the output signal of the first AND gate is at a high level, the counter counts up by S1; when the output signal of the first AND gate is at a low level, the counter counts down by S2; The comparator is used to compare whether the output value of the counter reaches the maximum continuous transmission time Smax allowed by the TR component.

2. The protection logic circuit of a TR component according to claim 1, wherein The value S1 when the counter counts up and the value S2 when the counter counts down should satisfy: where X is the maximum allowable duty cycle for the TR component not to be damaged.

3. The protection logic circuit of a TR component according to claim 2, wherein When the comparator compares the output value of the counter with the maximum continuous transmission time Smax allowed by the TR component, when the output value of the counter is greater than or equal to Smax, the comparator outputs a low level; when the output value of the counter is less than Smax, the comparator outputs a high level.

4. The protection logic circuit for a TR component according to claim 1, wherein The output signal of the first AND gate is input to the reverse counting control terminal of the counter after passing through a NOT gate.

5. The protection logic circuit of a TR component according to claim 1, characterized in that, The TR transceiver control signal input by the user is generated by a logic control circuit, and the Clk input terminal of the counter is connected to the clock signal input to the logic control circuit.

6. The protection logic circuit of a TR component according to claim 5, characterized in that, It further includes a transceiver control signal input module, the input terminal of the transceiver control signal input module is connected to the output terminal of the logic control circuit, and the output terminal is connected to one input terminal of the first AND gate.

7. A protection logic circuit for a TR component according to any one of claims 1 to 6, characterized in that, It further includes a second AND gate, the output terminal of the first AND gate is connected to one input terminal of the second AND gate, and the other input terminal of the second AND gate is connected to an external clock valid flag signal; the output terminal of the second AND gate is respectively connected to the input terminal of the locking output module, one input terminal of the comparator, the forward counting control terminal of the counter, and the reverse counting control terminal of the counter.

8. The control logic of a protection logic circuit for a TR component, characterized in that, Applied to a TR component protection logic circuit as described in any one of claims 1 to 7, it includes the following processes: A1. Start the TR component protection logic circuit, and the counter is reset to zero; A2. Monitor the TR transceiver control level output by the TR component protection logic circuit; A3. Judge whether the TR transceiver control level output by the TR component protection logic circuit in A2 is high or low. When the output signal is high, the counter counts up by S1; when the output signal is low, the counter counts down by S2; A4. Continue to monitor the TR transceiver control level output by the TR component protection logic circuit; A5. Judge whether the TR transceiver control level output by the TR component protection logic circuit in A4 is high or low. When the output signal is high, perform A6; when the output signal is low, perform A7; A6. Determine whether the output value of the counter is greater than the maximum continuous transmission time Smax allowed by the TR component; if so, set the level of the TR transceiver control signal input to the TR component to low, and return to A2; if not, maintain the level of the TR transceiver control signal input to the TR component, and return to A2; A7. Determine whether the output value of the counter is greater than 0; if so, set the level of the TR transceiver control signal input to the TR component to low, and return to A2; if not, maintain the level of the TR transceiver control signal input to the TR component, and return to A2.

9. A TR component transceiver control system, characterized in that, It includes: a logic control circuit, a TR component, and a TR component protection logic circuit as described in any one of claims 1 to 7; the logic control circuit is used to generate a TR transceiver control signal and is connected to the TR component protection logic circuit; the TR component protection logic circuit is used to automatically turn off the transmission when the transmission time of the TR component transceiver control is too long; when the TR component transceiver control does not meet the duty cycle requirement, automatically perform transceiver control correction; prevent the TR component from burning out; the TR component protection logic circuit is connected to the input end of the TR component.

10. A transceiver control system for a TR component according to claim 9, characterized in that, The logic control circuit is connected to an external clock signal and an external clock valid flag signal.

Images