Non-continuous variable-length Flash caching methods, electronic devices and storage media

Abstract

This invention discloses a non-contiguous variable-length Flash caching method, electronic device, and storage medium. The method includes: obtaining a read request for the physical address content of the Flash memory; traversing a cache segment linked list to obtain the content to be written; when a cache commit is required, traversing the cache segment linked list and dynamically allocating a segment of RAM as a cache page; and writing data according to the cache segment linked list and the cache page. This invention uses a linked list structure to cache only "useful" data, enabling Flash cache read / write operations with less RAM. Especially when the content to be updated is distributed across different Flash pages, the cache savings are even greater without reducing performance. The available RAM for other parts of the system can remain unchanged or increase, thus maintaining more system runtime and enhancing system compatibility.

Description

Technical Field

[0001] This invention relates to the field of Flash cache read / write technology for embedded systems, and specifically to a non-continuous variable-length Flash cache method, electronic device, and storage medium. Background Technology

[0002] An embedded system is a dedicated computer system used to control, monitor, or assist in the operation of machines and equipment. Typically, an embedded system is an embedded processor control board with its control program stored in ROM. In fact, all devices with digital interfaces, such as watches, microwave ovens, VCRs, and automobiles, use embedded systems. Some embedded systems also include an operating system, but most embedded systems implement the entire control logic through a single program. The operating data of an embedded system is usually stored on-chip or in external FLASH memory.

[0003] After a power outage, all information that can exist on an embedded system is stored in the Flash memory of its internal or external chips. However, reading and writing data to Flash takes time, especially writing data, which is relatively long. Therefore, a caching method is usually used: data is first stored in RAM, read and written in RAM, and then written to Flash all at once when the time is right. This reduces the number of Flash writes, thereby improving performance.

[0004] Prepare a fixed-length cache area in advance, usually in units of pages, such as 2 pages or 4 pages. When a piece of Flash data needs to be updated, first find the physical page address where the Flash data is located, then copy the entire page content sequentially into the cache page, and then copy the updated data into the cache page. After that, read and write the data in the cache as needed. Finally, when the cache is committed, write the entire cache page to Flash to complete the Flash update.

[0005] As mentioned above, existing caching techniques cache the entire contents of a physical page containing a segment of Flash data, regardless of whether it actually needs updating. For example, if each byte of a Flash page (256 bytes) is 0x55, and we need to update the two bytes starting from byte 128 to 0xaa (only these two bytes are truly "useful"), we would need to copy the entire page (all the "useless" 0x55 bytes) to the cache, then modify the two bytes starting from byte 128 in the cache to 0xaa, and finally write the entire cached page back to Flash. This approach only requires one page when the data to be updated is distributed across the same page; however, if the data to be updated at once is distributed across different Flash pages, more cache pages are needed, resulting in more cached useless data. Therefore, existing caching techniques are not problematic when used in processors with ample RAM. However, when the processor has limited RAM, if the Flash read / write performance is to remain constant, the number of cache pages must remain constant. This results in less available RAM allocated to other parts of the system. If more available RAM is required to maintain other parts of the system, the RAM allocated to cache pages will decrease. Consequently, there will not be enough cache pages for a one-time update, and Flash updates will need to be performed multiple times, leading to a decrease in Flash read / write performance. Summary of the Invention

[0006] In view of the technical defects mentioned in the background art, the purpose of this invention is to provide a non-continuous variable-length Flash cache method, electronic device and storage medium.

[0007] To achieve the above objectives, in a first aspect, embodiments of this application provide a non-continuous variable-length Flash cache method, comprising:

[0008] Obtain a read request for the physical address of the Flash memory;

[0009] According to the read request, the cache segment linked list is traversed to obtain the content to be written; the cache segment linked list includes multiple cache segment nodes, and the data structure of each cache segment node includes physical address, cache length, cache content and the address of the next cache segment node.

[0010] When it is necessary to submit the cache, the cache segment linked list is traversed, and a segment of RAM space is dynamically allocated according to the data structure of each cache segment node as a Flash cache page for writing Flash content;

[0011] The content to be written is written to the Flash based on the cache segment linked list and the Flash cache page.

[0012] As one specific implementation of this application, the read request includes the Flash physical address; according to the read request, the cache segment linked list is traversed to obtain the content to be written, specifically as follows:

[0013] Traverse the linked list of the cache segments;

[0014] If a cache segment node in the cache segment linked list covers the Flash physical address, then the content is read from that cache segment node as the content to be written.

[0015] If no cache segment node in the cache segment linked list covers the Flash physical address, then the content is read from the Flash physical address as the content to be written.

[0016] As a specific implementation of this application, the process of obtaining the Flash cache page is as follows:

[0017] When a cache needs to be committed, the cache segment linked list is traversed to find the cache segment node where all physical addresses are on the same page;

[0018] Record the page addresses of all physical addresses, and find the maximum value based on the cache length of each cache segment node;

[0019] Based on this maximum value, a segment of RAM space is dynamically allocated as a Flash cache page for writing Flash content.

[0020] As a specific implementation of this application, the writing of the content to be written to the Flash is achieved based on the cache segment linked list and the Flash cache page, specifically as follows:

[0021] Copy the content starting from the recorded page address into the Flash cache page;

[0022] Copy the contents of all identified cache segment nodes sequentially to the Flash cache page;

[0023] Delete all cache segment nodes found in the cache segment list;

[0024] Update the Flash cache page to Flash and dynamically release the Flash cache page.

[0025] As a preferred implementation of this application, before obtaining the read request for the Flash physical address content, the method further includes:

[0026] When it is necessary to cache a piece of Flash content, each cache segment node of the cache segment linked list is traversed according to the physical address of the Flash content and the cache length;

[0027] If the cache request coincides with the current cache segment node, then the current cache segment node is modified according to the cache request;

[0028] If the cache request does not overlap with the current cache segment node, then a segment of RAM space is dynamically allocated as a new cache segment node based on the size of the current cache segment node;

[0029] The physical address, cache length, and content are filled into the new cache segment node, and the new cache segment node is added to the end of the cache segment linked list.

[0030] As a specific implementation method, the criterion for determining whether a cache request overlaps with the current cache segment node is:

[0031] If the physical address of the Flash segment is between the physical address stored in the cache segment node and the physical address stored in the cache segment node plus the cache length; or

[0032] The physical address of the Flash segment plus the length of the Flash segment content lies between the physical address stored in the cache segment node and the physical address stored in the cache segment node plus the cache length.

[0033] Secondly, embodiments of this application provide an electronic device, including:

[0034] The first unit is used to obtain a read request for the physical address content of the Flash memory;

[0035] The second unit is used to traverse the cache segment linked list according to the read request to obtain the content to be written; the cache segment linked list includes multiple cache segment nodes, and the data structure of each cache segment node includes physical address, cache length, cache content and the address of the next cache segment node.

[0036] The third unit is used to traverse the cache segment linked list when it is necessary to submit the cache, and dynamically allocate a segment of RAM space as a Flash cache page for writing Flash content according to the data structure of each cache segment node.

[0037] The fourth unit is used to write the content to be written into the Flash based on the cache segment linked list and the Flash cache page.

[0038] Furthermore, as a preferred implementation of this application, the electronic device further includes a fifth unit for:

[0039] When it is necessary to cache a piece of Flash content, each cache segment node of the cache segment linked list is traversed according to the physical address of the Flash content and the cache length;

[0040] If the cache request coincides with the current cache segment node, then the current cache segment node is modified according to the cache request;

[0041] If the cache request does not overlap with the current cache segment node, then a segment of RAM space is dynamically allocated as a new cache segment node based on the size of the current cache segment node;

[0042] The physical address, cache length, and content are filled into the new cache segment node, and the new cache segment node is added to the end of the cache segment linked list.

[0043] Thirdly, embodiments of this application also provide another electronic device, including a processor, an input device, an output device, and a memory, wherein the processor, input device, output device, and memory are interconnected, wherein the memory is used to store a computer program, the computer program includes program instructions, and the processor is configured to invoke the program instructions to execute the steps of the method described in the first aspect above.

[0044] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, the computer program including program instructions. When executed by a processor, the program instructions implement the steps of the method described in the first aspect above.

[0045] Compared to existing technologies, this invention uses a linked list structure to cache only "useful" data, enabling Flash cache read / write operations with less RAM. This is especially beneficial when the content to be updated is distributed across different Flash pages, resulting in even greater cache savings without performance degradation. The available RAM for other parts of the system can remain constant or even increase, thus maintaining more system runtime and enhancing system compatibility. Attached Figure Description

[0046] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below.

[0047] Figure 1 This is a flowchart of a non-continuous variable-length Flash cache method provided in an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the cache segment linked list;

[0049] Figure 3 This is the execution flowchart of the cache allocation function;

[0050] Figure 4 This is a flowchart of the merged nodes;

[0051] Figure 5 This is a flowchart of the process of adding a new node;

[0052] Figure 6 This is the execution flowchart of the cache read function;

[0053] Figure 7 This is the execution flowchart of the cache submission function;

[0054] Figure 8 This is a structural diagram of an electronic device provided in an embodiment of the present invention;

[0055] Figure 9 This is another structural diagram of the electronic device provided in the embodiments of the present invention. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0058] The inventive concept of this invention is as follows: As described in the background section, in processors with limited RAM, maintaining consistent Flash read / write performance reduces the available RAM in other parts of the system, potentially leading to system malfunctions or limited usage environments. Therefore, this embodiment employs a linked list structure to cache only "useful" data, thus reducing cache usage. Combined with a dynamic allocation and release mechanism, this ensures normal system operation. It should be noted that, compared to the background technology, in this embodiment, the cache length is not fixed, and the cached content is not contiguous within RAM.

[0059] Example 1:

[0060] Please refer to Figure 1 This invention provides a non-continuous variable-length Flash cache method, including:

[0061] S1 defines the data structure of the cache segment node and generates a cache segment linked list based on the cache segment node.

[0062] Specifically, the data structure of each cache segment node includes: physical address, cache length, cache content, and the address of the next cache segment node. Multiple cache segment nodes can form a structure like this: Figure 2 The cache segment linked list shown.

[0063] S2, update the cache segment linked list.

[0064] Specifically, when it is necessary to cache a piece of Flash content, each cache segment node of the cache segment linked list is traversed according to the physical address of the Flash content and the cache length;

[0065] If the cache request coincides with the current cache segment node, then the current cache segment node is modified according to the cache request;

[0066] If the cache request does not overlap with the current cache segment node, then a segment of RAM space is dynamically allocated as a new cache segment node based on the size of the current cache segment node;

[0067] The physical address, cache length, and content are filled into the new cache segment node, and the new cache segment node is added to the end of the cache segment linked list.

[0068] The criteria for determining whether a cache request overlaps with the current cache segment node are as follows:

[0069] If the physical address of the Flash segment is between the physical address stored in the cache segment node and the physical address stored in the cache segment node plus the cache length; or

[0070] The physical address of the Flash segment plus the length of the Flash segment content lies between the physical address stored in the cache segment node and the physical address stored in the cache segment node plus the cache length.

[0071] S3, obtain the read request for the physical address content of Flash.

[0072] S4. Based on the read request, traverse the cache segment linked list to obtain the content to be written.

[0073] Specifically, when it is necessary to read a certain Flash physical address, the cache segment linked list is traversed;

[0074] If a cache segment node in the cache segment linked list covers the Flash physical address, then the content is read from that cache segment node as the content to be written.

[0075] If no cache segment node in the cache segment linked list covers the Flash physical address, then the content is read from the Flash physical address as the content to be written.

[0076] S5. When it is necessary to submit the cache, traverse the cache segment linked list and dynamically allocate a RAM space as a Flash cache page for writing Flash content according to the data structure of each cache segment node.

[0077] Specifically, when a cache needs to be submitted, the cache segment linked list is traversed to find the cache segment node where all physical addresses are on the same page;

[0078] Record the page addresses of all physical addresses, and find the maximum value based on the cache length of each cache segment node;

[0079] Based on this maximum value, a segment of RAM space is dynamically allocated as a Flash cache page for writing Flash content.

[0080] S6, The content to be written is written to the Flash according to the cache segment linked list and the Flash cache page.

[0081] Specifically, S6 includes:

[0082] (1) Copy the contents starting from the page address recorded in step S5 to the cache page requested in step S5;

[0083] (2) Copy the contents of all cache segment nodes found in step S5 to the cache page requested in step S5 in sequence;

[0084] (3) In the cache segment linked list, delete the cache segment node found in step S5 and release its space.

[0085] (4) Update the cached page to Flash;

[0086] (5) Dynamically release the cache pages allocated in step S5.

[0087] Furthermore, in this embodiment, after releasing the requested cache page, the process will continue to jump to step S5, repeat steps S5 and S6, repeatedly traverse the cache segment linked list, and search for cache segment nodes whose physical addresses belong to different pages, until both left and right cache segment nodes are committed and the cache segment linked list is cleared.

[0088] Example 2:

[0089] This invention also provides another method for non-contiguous variable-length Flash caching, comprising the following steps:

[0090] I. Define a structure

[0091] The implementation code is as follows:

[0092]

[0093] Here, the variable addr is the physical address of the Flash memory, length is the cache length, value is a pointer to the cache content address, and next is the address of the next cache segment node.

[0094] Next, define a global variable t_cache_node*cache_start; to store the starting node of the cache segment linked list.

[0095] II. Define the cache allocation function

[0096] like Figure 3 As shown, the execution flow of the cache allocation function is as follows:

[0097] (1) At the beginning of the function, the pointers of the current and previous nodes are initialized to the starting node of the linked list;

[0098] (2) The initial value of the cache hit variable is set to false;

[0099] (3) Determine if the current node pointer is null. If not, end the traversal; if yes, proceed to step (4).

[0100] (4) Check if the flash update address and length coincide with the current node. If yes, set the cache hit variable to true, merge the nodes, and end the traversal. If no, execute step (5).

[0101] (5) The pointer of the previous node is assigned the value of the pointer of the current node;

[0102] (6) The current node pointer is assigned the value of the next node that the current node points to;

[0103] (7) Traversal ends;

[0104] (8) Determine whether the cache hit variable is true or false. If it is true, the function ends; otherwise, add a new node and the function ends.

[0105] Among them, such as Figure 4 As shown, the process for merging the nodes is as follows:

[0106] (1) At the beginning of the function, compare the relationship between the flash address length and the current node address length to determine the starting address and length of the data to be merged;

[0107] (2) Allocate temporary RAM as new cache space based on the new data size;

[0108] (3) Copy the flash address and the current node cache content address to the new cache space;

[0109] (4) Release the RAM space of the current node's cached content;

[0110] (5) Modify the Flash physical address, cache length and cache content address pointer of the point-to-pay node, and the function ends.

[0111] Among them, such as Figure 5 As shown, the process for adding a new node is as follows:

[0112] (1) At the beginning of the function, temporary RAM is allocated as cache space and linked list nodes according to the data size;

[0113] (2) Copy data from the flash address to the cache space;

[0114] (3) Fill in the node's Flash physical address, cache length, and cache content address pointer;

[0115] (4) Attach the node to the end of the cache segment linked list and the function ends.

[0116] III. Define the cache read function

[0117] like Figure 6 As shown, the execution flow of the cache read function is as follows:

[0118] (1) At the beginning of the function, the current node pointer is initially assigned the value of the starting node of the linked list;

[0119] (2) The initial value of the cache hit variable is set to false;

[0120] (3) Check if the current node pointer is null. If yes, proceed to step (4). If no, end the traversal.

[0121] (4) Check if the flash address and length coincide with the current node. If yes, set the cache hit variable to true, copy the data from the cache to the buffer, and end the traversal. If no, execute step (5).

[0122] (5) The current node pointer is assigned the value of the next node that the current node points to;

[0123] (6) Traversal ends;

[0124] (7) Determine whether the cache hit is found based on the cache hit variable. If yes, the function ends; otherwise, execute step (8).

[0125] (8) Copy data from flash to buffer, the function ends.

[0126] III. Define the cache commit function

[0127] like Figure 7 As shown, the execution flow of the cache commit function is as follows:

[0128] (1) At the beginning of the function, check if the starting node of the linked list is empty. If it is, the function ends; otherwise, proceed to step (2).

[0129] (2) The current node pointer is initialized to the starting node of the linked list;

[0130] (3) The Flash page address variable is assigned the page address of the current node's Flash address;

[0131] (4) Check if the current node pointer is null. If yes, end the traversal. If no, proceed to step (5).

[0132] (5) Is the page address of the current node Flash address equal to the Flash page address variable? If yes, proceed to step (6); if no, assign the current pointer node to the next node of the current node pointer.

[0133] (6) Check if the current node cache length is greater than the maximum cache length of the record. If yes, proceed to step (7). If no, assign the current pointer node to the next node of the current node pointer.

[0134] (7) Assign the maximum cache length variable of the record to the cache length of the current node, and assign the current pointer node to the next node of the current node pointer;

[0135] (8) Traversal ends;

[0136] (9) Calculate the cache page size based on the maximum cache length;

[0137] (10) Allocate temporary page cache RAM;

[0138] (11) The Flash page address variable is assigned the page address of the current node's Flash address;

[0139] (12) Is the current node pointer null? If yes, the traversal ends; otherwise, proceed to step (13).

[0140] (13) Is the page address of the current node's Flash address equal to the Flash page address variable? If yes, proceed to step (14); otherwise, proceed to step (16).

[0141] (14) Copy the cached content to the temporary cache RAM;

[0142] (15) Delete the current node;

[0143] (16) Assign the current node pointer to the next node of the current pointer and return to step (11);

[0144] (17) Traversal ends;

[0145] (18) Update the cached page to Flash;

[0146] (19) Release temporary page cache RAM.

[0147] As can be seen from the above description, the embodiments of the present invention use a linked list structure to cache only "useful" data, enabling Flash cache read and write operations with less RAM. Especially when the content to be updated is distributed across different Flash pages, the cache savings are even greater, and performance is not reduced. The available RAM for other parts of the system can remain unchanged or even increase, thus maintaining more system runtime and enhancing system compatibility.

[0148] Based on the same inventive concept, embodiments of the present invention provide an electronic device. For example... Figure 8 As shown, the above-mentioned electronic device may include:

[0149] The first unit is used to obtain a read request for the physical address content of the Flash memory;

[0150] The second unit is used to traverse the cache segment linked list according to the read request to obtain the content to be written; the cache segment linked list includes multiple cache segment nodes, and the data structure of each cache segment node includes physical address, cache length, cache content and the address of the next cache segment node.

[0151] The third unit is used to traverse the cache segment linked list when it is necessary to submit the cache, and dynamically allocate a segment of RAM space as a Flash cache page for writing Flash content according to the data structure of each cache segment node.

[0152] The fourth unit is used to write the content to be written into the Flash based on the cache segment linked list and the Flash cache page.

[0153] The read request shown includes the Flash physical address; the second unit is specifically used for:

[0154] Traverse the linked list of the cache segments;

[0155] If a cache segment node in the cache segment linked list covers the Flash physical address, then the content is read from that cache segment node as the content to be written.

[0156] If no cache segment node in the cache segment linked list covers the Flash physical address, then the content is read from the Flash physical address as the content to be written.

[0157] Furthermore, the third unit is specifically used for:

[0158] When a cache needs to be committed, the cache segment linked list is traversed to find the cache segment node where all physical addresses are on the same page;

[0159] Record the page addresses of all physical addresses, and find the maximum value based on the cache length of each cache segment node;

[0160] Based on this maximum value, a segment of RAM space is dynamically allocated as a Flash cache page for writing Flash content.

[0161] Furthermore, Unit 4 is specifically used for:

[0162] Copy the content starting from the recorded page address into the Flash cache page;

[0163] Copy the contents of all identified cache segment nodes sequentially to the Flash cache page;

[0164] Delete all cache segment nodes found in the cache segment list;

[0165] Update the Flash cache page to Flash and dynamically release the Flash cache page.

[0166] Preferably, the electronic device further includes a fifth unit for:

[0167] When it is necessary to cache a piece of Flash content, each cache segment node of the cache segment linked list is traversed according to the physical address of the Flash content and the cache length;

[0168] If the cache request coincides with the current cache segment node, then the current cache segment node is modified according to the cache request;

[0169] If the cache request does not overlap with the current cache segment node, then a segment of RAM space is dynamically allocated as a new cache segment node based on the size of the current cache segment node;

[0170] The physical address, cache length, and content are filled into the new cache segment node, and the new cache segment node is added to the end of the cache segment linked list.

[0171] Alternatively, please refer to Figure 9 The electronic device of this invention may include one or more processors 101, one or more input devices 102, one or more output devices 103, and a memory 104. The processors 101, input devices 102, output devices 103, and memory 104 are interconnected via a bus 105. The memory 104 stores a computer program, which includes program instructions. The processor 101 is configured to invoke the program instructions to execute, for example... Figure 1 The steps are shown.

[0172] It should be understood that, in this embodiment of the invention, the processor 101 may be a central processing unit (CPU), but it may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0173] Input device 102 may include a keyboard, etc., and output device 103 may include a display (LCD, etc.), a speaker, etc.

[0174] The memory 104 may include read-only memory and random access memory, and provides instructions and data to the processor 101. A portion of the memory 104 may also include non-volatile random access memory. For example, the memory 104 may also store device type information.

[0175] In specific implementations, the processor 101, input device 102, and output device 103 described in the embodiments of the present invention can execute the implementation methods described in the embodiments of the non-continuous variable-length Flash cache method provided in the embodiments of the present invention, which will not be repeated here.

[0176] It should be noted that for a more detailed description of the workflow of the electronic device, please refer to the aforementioned method embodiment section, which will not be repeated here.

[0177] In addition, corresponding to the aforementioned method embodiments and electronic devices, this embodiment of the invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, implement the above-described non-continuous variable-length Flash cache method.

[0178] The computer-readable storage medium can be an internal storage unit of the electronic device described in any of the foregoing embodiments, such as a system hard drive or memory. The computer-readable storage medium can also be an external storage device of the system, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the computer-readable storage medium can include both internal storage units and external storage devices. The computer-readable storage medium is used to store the computer program and other programs and data required by the system. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0179] The aforementioned storage media include: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks or optical disks, and other media that can store program code.

[0180] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A non-contiguous variable-length Flash cache method, characterized in that, include: Obtain a read request for the physical address of the Flash memory; Based on the read request, traverse the cache segment linked list to obtain the content to be written; The cache segment linked list includes multiple cache segment nodes. The data structure of each cache segment node includes physical address, cache length, cache content and the address of the next cache segment node. When a cache needs to be committed, the cache segment linked list is traversed to find the cache segment node where all physical addresses are on the same page; Record the page addresses of all physical addresses, and find the maximum value based on the cache length of each cache segment node; Based on this maximum value, a segment of RAM space is dynamically allocated as a Flash cache page for writing Flash content; The writing of the content to be written to Flash is implemented based on the cache segment linked list and Flash cache pages, specifically as follows: Copy the content starting from the recorded page address into the Flash cache page; Copy the contents of all identified cache segment nodes sequentially to the Flash cache page; Delete all cache segment nodes found in the cache segment list; Update the Flash cache page to Flash and dynamically release the Flash cache page.

2. The Flash caching method as described in claim 1, characterized in that, The read request includes the Flash physical address; based on the read request, the cache segment linked list is traversed to obtain the content to be written, specifically: Traverse the linked list of the cache segments; If a cache segment node in the cache segment linked list covers the Flash physical address, then the content is read from that cache segment node as the content to be written. If no cache segment node in the cache segment linked list covers the Flash physical address, then the content is read from the Flash physical address as the content to be written.

3. The Flash caching method as described in claim 1 or 2, characterized in that, Before obtaining the read request for the Flash physical address content, the method further includes: When it is necessary to cache a piece of Flash content, each cache segment node of the cache segment linked list is traversed according to the physical address of the Flash content and the cache length; If a cache request overlaps with the current cache segment node, then the current cache segment node is modified according to the cache request; If the cache request does not overlap with the current cache segment node, then a segment of RAM space is dynamically allocated as a new cache segment node based on the size of the current cache segment node; The physical address, cache length, and content are filled into the new cache segment node, and the new cache segment node is added to the end of the cache segment linked list.

4. The Flash caching method as described in claim 3, characterized in that, The criterion for determining whether a cache request overlaps with the current cache segment node is: If the physical address of the Flash segment is between the physical address stored in the cache segment node and the physical address stored in the cache segment node plus the cache length; or The physical address of the Flash segment plus the length of the Flash segment content lies between the physical address stored in the cache segment node and the physical address stored in the cache segment node plus the cache length.

5. An electronic device, characterized in that, include: The first unit is used to obtain a read request for the physical address content of the Flash memory; The second unit is used to traverse the cache segment linked list according to the read request to obtain the content to be written; the cache segment linked list includes multiple cache segment nodes, and the data structure of each cache segment node includes physical address, cache length, cache content and the address of the next cache segment node. The third unit is used to traverse the cache segment linked list when a cache submission is required, find the cache segment node where all physical addresses are on the same page, record the page address of all physical addresses, find the maximum value based on the cache length of each cache segment node, and dynamically allocate a segment of RAM space based on the maximum value as a Flash cache page for writing Flash content. The fourth unit is used to write the content to be written into the Flash based on the cache segment linked list and the Flash cache page, specifically as follows: Copy the content starting from the recorded page address into the Flash cache page; Copy the contents of all identified cache segment nodes sequentially to the Flash cache page; Delete all cache segment nodes found in the cache segment list; Update the Flash cache page to Flash and dynamically release the Flash cache page.

6. The electronic device as claimed in claim 5, characterized in that, The electronic device further includes a fifth unit for: When it is necessary to cache a piece of Flash content, each cache segment node of the cache segment linked list is traversed according to the physical address of the Flash content and the cache length; If a cache request overlaps with the current cache segment node, then the current cache segment node is modified according to the cache request; If the cache request does not overlap with the current cache segment node, then a segment of RAM space is dynamically allocated as a new cache segment node based on the size of the current cache segment node; The physical address, cache length, and content are filled into the new cache segment node, and the new cache segment node is added to the end of the cache segment linked list.

7. An electronic device, characterized in that, The electronic device includes a processor, an input device, an output device, and a memory, which are interconnected. The memory is used to store a computer program, which includes program instructions. The processor is configured to invoke the program instructions to execute the method as described in any one of claims 1-4.

8. A computer-readable storage medium storing a computer program, the computer program comprising program instructions, characterized in that, When the program instructions are executed by the processor, they implement the method as described in any one of claims 1-4.

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