Non-volatile memory and data reading method thereof, computer system

Abstract

The present disclosure provides a non-volatile memory and a data read method thereof, and a computer system. The data read method for the non-volatile memory includes configuring the non-volatile memory into a continuous read mode based on only a first command sub-sequence in a first operation signal, wherein the continuous read mode is used to allow the non-volatile memory to continuously perform a plurality of data read cycles. The method further includes performing one or more data read cycles until a second command sub-sequence is received after the non-volatile memory is configured into the continuous read mode, wherein the second command sub-sequence is different from the first command sub-sequence. The data read method provided by the present disclosure improves the efficiency of the read operation of the NOR flash memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory, and more specifically, to a data retrieval technology for a non-volatile memory. Background Technology

[0002] Semiconductor memory devices can generally be classified into volatile memory and non-volatile (NV) memory. Volatile memory (such as DRAM, SRAM, etc.) loses stored data when power is absent. Conversely, non-volatile memory (such as EEPROM, EAROM, PROM, EPROM, NAND flash memory, NOR flash memory, etc.) retains stored data even when power is absent. With the development of portable electronic products (such as personal computers, smartphones, digital cameras, multimedia playback devices, etc.), the demand for non-volatile memory is increasing, and the performance requirements for it are also becoming more stringent.

[0003] In non-volatile memory, there are three basic operations: read, program, and erase. Flash memory (such as NAND flash or NOR flash) is widely used as a non-volatile memory. Traditional NOR flash memory provides a sequential read mode to improve the efficiency of read operations.

[0004] The following is Figure 1 For example, this illustrates the existing data reading methods.

[0005] Figure 1 This illustrates the signal inputs and outputs of each pin of the NOR flash memory during the execution of existing data read methods. For example... Figure 1 As shown, the CS# (chip select) pin is the chip select pin. When a low voltage is input to the CS# pin, the current NOR flash memory is selected, and inputs to other pins of the NOR flash memory (e.g., SCLK pin, IO pins, etc.) are valid. In other words, a low voltage received at the CS# pin activates the NOR flash memory. Conversely, a high voltage input to the CS# pin deselects the current NOR flash memory, and inputs to other pins of the NOR flash memory are completely invalid. In other words, a high voltage received at the CS# pin disables the NOR flash memory, and signals received at other pins of the NOR flash memory are invalid. See also... Figure 1The SCLK (Serial Clock) pin is the serial clock pin, which can be used to receive clock signals. The IO (Input Output) pin is the input / output pin (also called the transmission pin), which can be used for at least one of the following: receiving signals (e.g., read signals, write signals, programming signals, erase signals, etc., where read signals may include, for example, combinations of the following). Figure 1 The command subsequence, address subsequence, pattern subsequence, redundancy subsequence, etc., and the output signal (for example, in conjunction with the following) Figure 1 (The data stored in the NOR flash memory's storage cells). Figure 1 The diagram shows four I / O pins: I / O0, I / O1, I / O2, and I / O3.

[0006] like Figure 1 As shown, during the NOR flash memory's data read operation, when a low voltage is received at the CS# pin, the current NOR flash memory is selected (i.e., activated), and the clock signal received at the SCLK pin is valid at this time. Figure 1 As shown, the first data read cycle of the NOR flash memory can begin when a command subsequence (e.g., EBH) is received at the IO0 pin during the eight SCLK signal periods (i.e., SCLK signal 0-7). Figure 1 As shown, during the first data read cycle of the NOR flash memory, the NOR flash memory receives the address subsequence A23-0 at pins IO0, IO1, IO2, and IO3 during the SCLK signal period 8-13, and receives a redundant subsequence at pins IO0, IO1, IO2, and IO3 during the subsequent SCLK signal period 14-19. (The text repeats itself here, so the translation ends here.) Figure 1As shown, the redundant subsequence may include the mode subsequence M7-0. After the redundant subsequence ends, during the SCLK signal period 20-21, the data D1 stored in the NOR flash memory cell indicated by the address subsequence A23-0 can be output from the IO0, IO1, IO2, and IO3 pins. This completes the first data read cycle of the NOR flash memory. Specifically, in the mode subsequence M7-0 received at the IO0, IO1, IO2, and IO3 pins during the SCLK signal period 14-15, M5-4 is configured as (1, 0). The mode subsequence M7-0 with M5-4 configured as (1, 0) can be used to initiate the continuous read mode of the NOR flash memory. When the NOR flash memory is in continuous read mode, during the second data read cycle, as long as the NOR flash memory receives the address subsequence A23-0, the data stored in the NOR flash memory cell indicated by the address subsequence A23-0 can be output, without requiring the receipt of a command subsequence (e.g., EBH). During the second data read cycle, if a mode subsequence M7-0, where M5-4 is configured as (1, 0), is received after address subsequence A23-0, the NOR flash memory can be maintained in continuous read mode. However, if a mode subsequence M7-0, where M5-4 is not configured as (1, 0), is received after address subsequence A23-0, the NOR flash memory can be exited from continuous read mode to perform other operations, such as programming or erasing. In some other cases, when the NOR flash memory is in continuous read mode, if a signal indicating exiting continuous read mode (e.g., a soft reset signal) is received at an IO pin, the NOR flash memory can be exited from continuous read mode to perform other operations, such as programming or erasing.

[0007] When re-entering NOR flash memory's continuous read mode after exiting it, the system requires receiving the command subsequence (e.g., EBH), address subsequence A23-0, and mode subsequence M7-0 where M5-4 is configured as (1, 0), as described above. Therefore, whether maintaining the NOR flash memory in continuous read mode or re-entering it after exiting, time is required to receive the mode subsequence M7-0 where M5-4 is configured as (1, 0). This reduces the efficiency of NOR flash memory read operations.

[0008] Therefore, it is desirable to propose a technical solution to improve the read operation efficiency of NOR flash memory. Summary of the Invention

[0009] The technical solution proposed in this invention aims to solve the problem of low read efficiency of NOR flash memory as described above.

[0010] In one aspect of the invention, a data reading method for a non-volatile memory is provided, comprising: configuring the non-volatile memory into a continuous read mode based solely on a first command subsequence in a first operation signal, wherein the continuous read mode is configured to allow the non-volatile memory to continuously execute multiple data read cycles; and after the non-volatile memory is configured into the continuous read mode, executing one or more data read cycles until a second command subsequence is received, wherein the second command subsequence is different from the first command subsequence.

[0011] In at least one embodiment of one aspect of the present invention, the data reading method further includes: receiving a first operation signal, the first operation signal including at least a first command subsequence; in response to receiving the first command subsequence, determining whether the first command subsequence indicates entering the continuous read mode; and in response to determining that the first command subsequence indicates entering the continuous read mode, configuring the non-volatile memory into the continuous read mode.

[0012] In at least one embodiment of one aspect of the present invention, the data reading method further includes: receiving a second operation signal, the second operation signal including at least a second command subsequence; in response to receiving the second command subsequence, determining whether the second command subsequence indicates exiting the continuous read mode; in response to determining that the received second command subsequence indicates exiting the continuous read mode, determining whether the second command subsequence was received during the continuous read mode; and in response to determining that the second command subsequence was received during the continuous read mode, causing the non-volatile memory to exit the continuous read mode.

[0013] In at least one embodiment of one aspect of the present invention, the non-volatile memory includes one or more memory cells, each memory cell having a corresponding memory address, and receiving the first operation signal includes: during each data read cycle, receiving a first address subsequence, the first address subsequence indicating a corresponding first memory address; and the data read method further includes: during each data read cycle, outputting data in a first memory cell of the non-volatile memory, wherein the first memory cell has the first memory address; and during at least one data read cycle, outputting data in a second memory cell of the non-volatile memory, wherein the second memory cell is a memory cell immediately following the first memory cell.

[0014] In at least one embodiment of one aspect of the present invention, the non-volatile memory includes a chip select pin, a serial clock pin, and one or more transmission pins, each transmission pin being used for at least one of the following: receiving a first command subsequence, receiving a second command subsequence, receiving an address subsequence, and outputting data stored in the non-volatile memory. The data reading method further includes: receiving a low voltage via the chip select pin to activate the non-volatile memory; and receiving a clock signal via the serial clock pin.

[0015] In at least one embodiment of one aspect of the present invention, the data reading method further includes: receiving a high voltage via the chip select pin during each data reading cycle to terminate the data reading cycle.

[0016] In at least one embodiment of one aspect of the invention, the non-volatile memory is NOR flash memory.

[0017] In another aspect of the invention, a data reading method for a non-volatile memory is provided, the non-volatile memory including one or more memory cells, each memory cell having a corresponding memory address, the data reading method comprising: inputting a first operation signal to the non-volatile memory such that the non-volatile memory is configured into a continuous read mode based solely on a first command subsequence in the first operation signal, wherein the continuous read mode allows the non-volatile memory to continuously perform multiple data read cycles; during a data read cycle: inputting an address subsequence to the non-volatile memory, the address subsequence indicating a corresponding memory address; and receiving data from a memory cell having the memory address indicated by the input address subsequence from the non-volatile memory; and inputting a second operation signal including a second command subsequence to the non-volatile memory such that the non-volatile memory exits the continuous read mode, wherein the second command subsequence is different from the first command subsequence.

[0018] In another aspect of the invention, a non-volatile memory is provided that stores computer instructions, which, when executed by a processing unit, perform the data reading method described in any of the preceding paragraphs on the non-volatile memory.

[0019] In another aspect of the present invention, a computer system is provided, comprising: a computer storage medium storing computer instructions; a non-volatile memory; and a processing unit that, when executing the computer instructions, performs a data reading method described in any of the preceding paragraphs on the non-volatile memory.

[0020] The technical solution proposed in this invention can improve the read operation efficiency of NOR flash memory and simplify the read operation of NOR flash memory. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0022] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the invention will now be described by way of example and with reference to the accompanying drawings, wherein:

[0023] Figure 1 The signal inputs and outputs of each pin of the NOR flash memory are illustrated during the execution of the existing data read method.

[0024] Figure 2 The signal inputs and outputs of each pin of the NOR flash memory are illustrated during the execution of the data reading method according to an embodiment of the present invention.

[0025] Figure 3 A data reading method according to an embodiment of the present invention is shown.

[0026] Figure 4 A block diagram of a non-volatile memory according to an embodiment of the present invention is shown.

[0027] Figure 5 A block diagram of a computer system according to an embodiment of the present invention is shown.

[0028] Figure label:

[0029] 400 Non-volatile Memory

[0030] 401 Storage Area

[0031] 403 Processing Department

[0032] 500 computer systems

[0033] 501 Non-volatile Memory

[0034] 502 Computer storage media

[0035] 503 Processing Department Detailed Implementation

[0036] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0037] Various aspects of the invention are described in this disclosure with reference to the accompanying drawings, which illustrate numerous illustrative embodiments. The embodiments of this disclosure are not necessarily intended to encompass all aspects of the invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0038] Those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or in conjunction with other alternatives and / or additional methods, operations, or components. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the embodiments of the invention. Similarly, for illustrative purposes, specific numbers, operations, and configurations are set forth to provide a comprehensive understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Furthermore, it should be understood that the embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0039] See Figure 2 and Figure 3 , Figure 2 The signal inputs and outputs of each pin of the NOR flash memory are illustrated during the execution of the data read method 300 according to an embodiment of the present invention. Figure 3 A data reading method 300 according to an embodiment of the present invention is shown. In conjunction with the above... Figure 1 Similar to the described pins, the CS# (chip select) pin is the chip select pin. When a low voltage is input to the CS# pin, the current NOR flash memory is selected, and inputs to other pins of the NOR flash memory (e.g., SCLK pin, IO pins) are valid. In other words, a low voltage at the CS# pin activates the NOR flash memory. Conversely, a high voltage is input to the CS# pin deselects the current NOR flash memory, and inputs to other pins of the NOR flash memory are completely invalid. In other words, a high voltage at the CS# pin disables the NOR flash memory, and signals received at other pins of the NOR flash memory are invalid. See also Figure 2 The SCLK (Serial Clock) pin is the serial clock pin, which can be used to receive clock signals. The IO (Input Output) pin is the input / output pin (also called the transmission pin), which can be used to receive at least one of the following: a first operation signal (e.g., a read signal for executing continuous read mode, which may include the following combinations). Figure 2 and Figure 3The first command subsequence, the first address subsequence, the second address subsequence, etc., are received, a second operation signal (e.g., an exit signal, which may include the second command subsequence to indicate exiting continuous read mode), and an output signal (e.g., as combined below). Figure 2 and Figure 3 (The data stored in the NOR flash memory's storage cells). Figure 2 In the illustrated embodiment, four I / O pins are shown: IO0, IO1, IO2, and IO3. In other embodiments, the NOR flash memory may have other numbers of I / O pins, such as one, two, or eight. Those skilled in the art will understand that the number of I / O pins used when receiving and / or outputting signals via I / O pins can affect the SCLK signal time occupied by the received and / or output signals. For example, when receiving or outputting an 8-bit signal, using one I / O pin requires eight SCLK signal times, using two I / O pins requires four SCLK signal times, using four I / O pins requires two SCLK signal times, and using eight I / O pins requires one SCLK signal time.

[0040] The following combination Figure 2 and Figure 3 This describes how NOR flash memory performs data reading method 300 in some embodiments of the present invention.

[0041] exist Figure 3 At step 301, a low voltage is received via the CS# pin. In some embodiments, when the NOR flash memory processing unit (e.g., as combined below) Figure 4 The processing unit 403 or below is combined with Figure 5 When the processing unit 503 receives a low voltage via the CS# pin of the NOR flash memory, it can activate the NOR flash memory. At this time, the clock signal received via the SCLK pin of the NOR flash memory is valid. Method 300 can then proceed to step 302.

[0042] At step 302, a first command subsequence is received via an IO pin. In some embodiments, the processing unit can receive 8 SCLK signals (e.g., such as...). Figure 2 During the first SCLK signal period (0-7) shown, the first command subsequence CMD1 is received via the IO0 pin. Method 300 can proceed to step 303.

[0043] At step 303, it is determined whether the first command subsequence indicates entry into continuous read mode. In some embodiments, such as Figure 2As shown, the first command subsequence CMD1 can be a predetermined subsequence including 8 bits of data. In other embodiments, the first command subsequence CMD1 can be set to a predetermined subsequence of other bit lengths as needed or required. When the processing unit determines that the first command subsequence CMD1 indicates entry into continuous read mode, method 300 proceeds to step 304; otherwise, the method proceeds to step 317.

[0044] At step 304, the NOR flash memory is configured for continuous read mode. In some embodiments, the processing unit may configure the NOR flash memory for continuous read mode when it determines that the first command subsequence CMD1 indicates entry into continuous read mode. In continuous read mode, the NOR flash memory can continuously perform multiple data read cycles. In some embodiments, when the processing unit configures the NOR flash memory for continuous read mode, it may set the mode state value to 1. Method 300 may proceed to step 305 to begin the first data read cycle of the NOR flash memory.

[0045] At step 305, the first address sub-sequence is received via an IO pin. In some embodiments, the processing unit may, as shown in... Figure 2 The SCLK signal shown receives the first address subsequence A23-0 via pins IO0, IO1, IO2, and IO3 during period 8-13. The first address subsequence A23-0 can indicate the storage address (e.g., address 100) of a first predetermined memory cell in the NOR flash memory. Method 300 can proceed to step 306.

[0046] At step 306, data is output via an I / O pin. In some embodiments, the processing unit may, as shown in... Figure 2 During the SCLK signal period 14-15, the data D1 stored in the first predetermined memory cell indicated by the first address sequence A23-0 is output via the IO0, IO1, IO2 and IO3 pins for use by other devices (e.g., processing units 403 or 503 described below). Method 300 may proceed to step 307.

[0047] At step 307, a high voltage is received via the CS# pin. In some embodiments, when the processing unit is in such a state... Figure 2 When a high voltage is received via the CS# pin after the SCLK signal period 14-15 as shown, the first data read cycle of the NOR flash memory can be ended.

[0048] In other embodiments, when the processing unit receives a low voltage via the CS# pin and a clock signal via the SCLK pin after the SCLK signal period 14-15, it can perform the operation during the subsequent SCLK signal period (e.g., SCLK signal period 16-17). Figure 2(Not shown) Data stored in one or more first additional memory units (e.g., addresses 101, 102, ...) immediately following the first predetermined memory unit (e.g., address 100) is output via pins IO0, IO1, IO2, and IO3. The number of the one or more first additional memory units depends on the duration of the SCKL signal received via the CS# pin. For example, when the low voltage received via the CS# pin lasts for two SCKL signal periods, data stored in one first additional memory unit (e.g., address 101) immediately following the first predetermined memory unit (e.g., address 100), i.e., one byte of data, can be output via pins IO0, IO1, IO2, and IO3. When a low voltage received via the CS# pin lasts for four consecutive SCKL signal periods, pins IO0, IO1, IO2, and IO3 can output data (2 bytes) stored in two first supplementary memory units (e.g., addresses 101 and 102) immediately following the first predetermined memory unit (e.g., address 100). When the processing unit subsequently receives a high voltage via the CS# pin, it can stop outputting data via pins IO0, IO1, IO2, and IO3, thereby ending the first data read cycle of the NOR flash memory.

[0049] Method 300 can proceed to step 308.

[0050] At step 308, a low voltage is received via the CS# pin. In some embodiments, such as Figure 2 As shown, when the processing unit receives a low voltage again via the CS# pin, the current NOR flash memory can be reactivated, at which point the clock signal received via the SCLK pin is valid. Method 300 can proceed to step 309 to begin the second data read cycle of the NOR flash memory.

[0051] At step 309, the second address sub-sequence is received via the IO pin. In some embodiments, the processing unit may, as shown in... Figure 2 During the second SCLK signal period 0-5, the second address subsequence A23-0 is received via pins IO0, IO1, IO2, and IO3. The second address subsequence A23-0 indicates the storage address of a second predetermined memory cell in the NOR flash memory. Method 300 can proceed to step 310.

[0052] At step 310, data is output via an I / O pin. In some embodiments, the processing unit can, as shown in... Figure 2During the second SCLK signal period 6-7, the data D2 stored in the second predetermined memory cell indicated by the second address sequence A23-0 is output via the IO0, IO1, IO2 and IO3 pins for use by other devices (e.g., processing units 403 or 503 described below). Method 300 may proceed to step 311.

[0053] At step 311, a high voltage is received via the CS# pin. In some embodiments, such as Figure 2 As shown, when the processing unit receives a high voltage via the CS# pin after the second SCLK signal period 6-7, the second data read cycle of the NOR flash memory can be terminated.

[0054] In other embodiments, when the processing unit receives a low voltage via the CS# pin and a clock signal via the SCLK pin after the second SCLK signal period 6-7, it can perform the operation during subsequent SCLK signal periods (e.g., SCLK signal period 8-9). Figure 2 The data stored in one or more second additional memory cells (e.g., addresses 201, 202, ...) immediately following the second predetermined memory cell (e.g., address 200) is output via pins IO0, IO1, IO2, and IO3. Similar to the description above for the first additional memory cell, the number of these one or more second additional memory cells depends on the SCKL signal sustained by a low voltage received via the CS# pin. When the processing unit subsequently receives a high voltage via the CS# pin, it can stop outputting data via pins IO0, IO1, IO2, and IO3, thereby ending the second data read cycle of the NOR flash memory.

[0055] When the NOR flash memory is in sequential read mode, the third, fourth, ..., Nth data read cycles can be performed similarly to the second data read cycle. For example, steps 308-311 can be repeated to perform the third, fourth, ..., Nth data read cycles. In other embodiments, the NOR flash memory in sequential read mode may perform only one data read cycle.

[0056] Method 300 can proceed to step 312.

[0057] At step 312, a low voltage is received via the CS# pin. In some embodiments, such as Figure 2 As shown, when the processing unit receives a low voltage via the CS# pin, it can activate the current NOR flash memory, at which point the clock signal received via the SCLK pin is valid. Method 300 can then proceed to step 313.

[0058] At step 313, a second command subsequence is received via an IO pin. In some embodiments, the processing unit can receive the second command subsequence via eight SCLK signals (e.g., as shown in the image). Figure 2 The second command subsequence CMD2 is received via the IO0 pin during the third SCLK signal period (0-7). Method 300 can proceed to step 314.

[0059] At step 314, it is determined whether the second command subsequence indicates exiting continuous read mode. The second command subsequence CMD2 indicating exiting continuous read mode may be different from the first command subsequence CMD1 indicating entering continuous read mode. Those skilled in the art can predetermine the first command subsequence CMD1 and the second command subsequence CMD2 specifically for continuous read mode of NOR flash memory as needed.

[0060] When the processing unit determines that the second command subsequence CMD2 indicates exiting continuous read mode, method 300 may proceed to step 315; otherwise, the method proceeds to step 318.

[0061] At step 315, it is determined whether the second command subsequence was received during continuous read mode. In some embodiments, the processing unit may determine whether the mode state value when the second command subsequence CMD2 was received was 1. When it is determined that the mode state value when the second command subsequence CMD2 was received was 1, the processing unit may determine that the second command subsequence CMD2 was received during continuous read mode.

[0062] When the processing unit determines that the second command subsequence was received during continuous read mode, method 300 may proceed to step 316; otherwise, the method proceeds to step 319.

[0063] At step 316, the NOR flash memory is exited from continuous read mode. In some embodiments, the NOR flash memory can be exited from continuous read mode when the processing unit determines that the second command subsequence CMD2 indicates an exit from continuous read mode and determines that the second command subsequence CMD2 was received during continuous read mode. In some embodiments, when the NOR flash memory exits continuous read mode, the processing unit can set the mode state value to 0.

[0064] At step 317, the operation indicated by the first command subsequence is executed. In some embodiments, when the processing unit determines at step 303 that the first command subsequence does not indicate a continuous read mode, other operations indicated by the first command subsequence may be executed. For example, if it is determined that the first command subsequence indicates entering a read mode, the NOR flash memory may be configured to read mode. As another example, if it is determined that the first command subsequence indicates entering an erase mode, the NOR flash memory may be configured to erase mode.

[0065] At step 318, a first predetermined operation is performed. In some embodiments, when the processing unit determines at step 314 that the second command subsequence does not indicate exiting the continuous read mode, the first predetermined operation may be performed, for example, an error reporting operation may be performed to indicate that the current operation is erroneous.

[0066] At step 319, a second predetermined operation is performed. In some embodiments, when the processing unit determines at step 315 that the second command subsequence was not received during continuous read mode, a second predetermined operation may be performed, for example, an error reporting operation to indicate that the current operation is erroneous.

[0067] The above steps are exemplary and not intended to be limiting. Those skilled in the art may add one or more steps, delete one or more of the above steps, combine or replace one or more of the above steps, or adjust the order of one or more of the above steps as needed.

[0068] The above description, for illustrative purposes only, describes receiving or outputting signals via specific I / O pins, such as receiving a first command subsequence CMD1 and a second command subsequence CMD2 via pin IO0, and outputting data via pins IO0-IO3. In other embodiments, those skilled in the art can configure the I / O pins for input or output signals as needed. For example, any one or more of pins IO0-IO3 can be used to perform at least one of the following: receiving a first command subsequence, receiving a second command subsequence, receiving an address subsequence, and outputting data stored in NOR memory.

[0069] According to the data reading method of the present invention, NOR flash memory can be configured into a continuous read mode that allows multiple data read cycles to be executed consecutively, based solely on a first command subsequence CMD1. In each data read cycle of the continuous read mode, as long as an address subsequence including a memory address indicating a predetermined memory cell is received via an I / O pin, at least the data within that predetermined memory cell can be output via the I / O pin. In this way, the present invention can improve the read operation efficiency of NOR flash memory and also simplify the read operation of NOR flash memory.

[0070] The above description uses NOR flash memory as an example to illustrate a data reading method for non-volatile memory, as well as the signal inputs and outputs of each pin of the NOR flash memory during the execution of this data reading method. However, it should be understood that this application can be applied to other non-volatile memories.

[0071] As can be seen, the above-described data reading method for non-volatile memory is described from the following first perspective: receiving signals (e.g., low voltage and / or high voltage) via the CS# pin, receiving clock signals via the SCLK pin, receiving signals (e.g., a first command subsequence, a second command subsequence, a first address subsequence, and / or a second address subsequence) via the IO pin, and / or outputting signals (e.g., data within the memory cell) via the IO pin. Those skilled in the art should understand that the present invention should also cover the data reading method for non-volatile memory described from the following second perspective, corresponding to the first perspective: inputting signals (e.g., low voltage and / or high voltage) to the CS# pin of the non-volatile memory, inputting clock signals to the SCLK pin of the non-volatile memory, inputting signals (e.g., a first command subsequence, a second command subsequence, a first address subsequence, and / or a second address subsequence) to the IO pin of the non-volatile memory, and / or receiving signals (e.g., data within the memory cell) from the IO pin of the non-volatile memory. For example, a data read method for a non-volatile memory may include: inputting a first operation signal to the non-volatile memory such that the non-volatile memory is configured to a continuous read mode, allowing the non-volatile memory to continuously execute multiple data read cycles, based solely on a first command subsequence in the first operation signal. The data read method may further include: during a data read cycle, inputting an address subsequence to the non-volatile memory and receiving data from a memory cell, wherein the memory cell has a memory address indicated by the input address subsequence. Furthermore, the data read method may further include: inputting a second operation signal to the non-volatile memory comprising a second command subsequence different from the first command subsequence, such that the non-volatile memory exits the continuous read mode.

[0072] The following is for reference Figure 4 The non-volatile memory of an embodiment of the present invention will be described. Figure 4 A block diagram of a non-volatile memory 400 according to an embodiment of the present invention is shown.

[0073] In some embodiments, the non-volatile memory 400 may be a non-volatile memory such as NAND flash memory or NOR flash memory. Figure 4 As shown, the non-volatile memory 400 may include a storage region 401 and a processing unit 403. The storage region 401 may be used to store computer instructions. The processing unit 403 may automatically execute the computer instructions stored in the storage region 401 or, upon receiving a signal from an external computing device (e.g., a computer or a communication terminal), to perform one or more steps of the data reading method 300 described above on the non-volatile memory 400. In some embodiments, the processing unit 403 may be, for example, a semiconductor chip within the non-volatile memory 400.

[0074] The following is for reference Figure 5 The computer system according to an embodiment of the present invention will be described. Figure 5 A block diagram of a computer system 500 according to an embodiment of the present invention is shown.

[0075] like Figure 5 As shown, the computer system 500 may include a non-volatile memory 501, a computer storage medium 502, and a processing unit 503. The non-volatile memory 501 may be NAND flash memory, NOR flash memory, etc. The computer storage medium 502 can be used to store computer instructions. The processing unit 503 can automatically control the non-volatile memory 501, or control the non-volatile memory 501 upon receiving signals from the outside (e.g., via wireless transmission) or from the inside (e.g., from other circuits or components within the computer system 500). For example, the processing unit 503 can execute computer instructions stored in the computer storage medium 502 to implement one or more steps of the data reading method 300 described above for the non-volatile memory 501. As an example, the processing unit 503 may include an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), various logic circuits, and various signal processing circuits, etc.

[0076] Although the invention has been described with reference to preferred embodiments thereof, it is not intended to be limited thereto, but rather to be limited only by the scope set forth in the appended claims.

Claims

1. A data reading method for a non-volatile memory, the non-volatile memory comprising one or more memory cells, each memory cell having a corresponding memory address, the data reading method comprising: Based solely on the first command subsequence in the first operation signal, the non-volatile memory is configured into a continuous read mode, wherein the continuous read mode is used to allow the non-volatile memory to continuously execute multiple data read cycles; and After the non-volatile memory is configured into the sequential read mode, multiple data read cycles are executed until a second command subsequence is received, wherein the second command subsequence is different from the first command subsequence. During each data reading cycle: Only address subsequences are received, the address subsequences indicating their corresponding storage addresses; and Output the data in the storage cell of the non-volatile memory, wherein the storage cell has a storage address indicated by the received address subsequence.

2. The data reading method as described in claim 1, characterized in that, Also includes: Receive the first operation signal, wherein the first operation signal includes at least a first command subsequence; In response to receiving the first command subsequence, determine whether the first command subsequence indicates entering the continuous read mode; and In response to determining that the first command subsequence indicates entry into the continuous read mode, the non-volatile memory is configured into the continuous read mode.

3. The data reading method as described in claim 2, characterized in that, Also includes: Receive a second operation signal, the second operation signal including at least the second command subsequence; In response to receiving the second command subsequence, determine whether the second command subsequence indicates exiting the continuous read mode; In response to determining that the received second command subsequence indicates exiting the continuous read mode, it is determined whether the second command subsequence was received during the continuous read mode; as well as In response to determining that the second command subsequence was received during continuous read mode, the non-volatile memory is caused to exit the continuous read mode.

4. The data reading method as described in claim 2, characterized in that, Receiving the first operation signal includes: during each data read cycle, receiving the address subsequence, the address subsequence indicating its corresponding storage address; and The data reading method further includes: During each data read cycle, data in a first storage cell of the non-volatile memory is output, wherein the first storage cell has the storage address; and During at least one data read cycle, data in a second storage cell of the non-volatile memory is output, wherein the second storage cell is a storage cell immediately following the first storage cell.

5. The data reading method as described in any one of claims 1-4, characterized in that, The non-volatile memory includes a chip select pin, a serial clock pin, and one or more transmission pins. Each transmission pin is used for at least one of the following: receiving the first command subsequence, receiving the second command subsequence, receiving an address subsequence, and outputting data stored in the non-volatile memory. The data reading method further includes: A low voltage is received via the chip select pin to activate the non-volatile memory; The clock signal is received via the serial clock pin.

6. The data reading method as described in claim 5, characterized in that, Also includes: During each data read cycle, a high voltage is received via the chip select pin to end the data read cycle.

7. The data reading method as described in any one of claims 1-4, characterized in that, The non-volatile memory is NOR flash memory.

8. A data reading method for a non-volatile memory, the non-volatile memory comprising one or more memory cells, each memory cell having a corresponding memory address, the data reading method comprising: A first operation signal is input to the non-volatile memory so that the non-volatile memory is configured into a continuous read mode based solely on a first command subsequence in the first operation signal, wherein the continuous read mode is used to allow the non-volatile memory to continuously execute multiple data read cycles; During each data read cycle: Input only an address subsequence to the non-volatile memory, the address subsequence indicating its corresponding memory address; and Data is received from a storage cell in the non-volatile memory, the storage cell having a storage address indicated by an input address subsequence; and A second operation signal, including a second command subsequence, is input to the non-volatile memory so that the non-volatile memory exits the continuous read mode, wherein the second command subsequence is different from the first command subsequence.

9. A non-volatile memory, characterized in that, The non-volatile memory stores computer instructions, which, when executed by a processing unit, perform a data reading method as described in any one of claims 1 to 8 on the non-volatile memory.

10. A computer system, characterized in that, include: Computer storage media that stores computer instructions; Non-volatile memory; as well as The processing unit, when executing the computer instructions, performs the data reading method as described in any one of claims 1 to 8 on the non-volatile memory.

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