Formation of junction barrier diodes and schottky diodes and mps devices

Abstract

Embodiments of the present disclosure relate to formation of junction barrier diodes and Schottky diodes and MPS devices. A merged PiN-Schottky (MPS) device includes a solid having a first conductivity, an implanted region extending into the solid facing a front side of the solid having a second conductivity opposite the first conductivity, and a semiconductor layer extending over the front side formed of a transition metal dichalcogenide (TMD) material. A first region of the semiconductor layer has the second conductivity and extends in electrical contact with the implanted region, and a second region of the semiconductor layer has the first conductivity and extends adjacent the first region in electrical contact with a corresponding surface portion of the front side having the first conductivity.

Description

Technical Field

[0001] This disclosure relates to methods for manufacturing MPS (Merged PiN Schottky) devices and MPS devices. Specifically, SiC-based devices will be discussed. Background Technology

[0002] As is well known, it has a wide bandgap (especially a bandgap energy value Eg greater than 1.1 eV) and low on-state resistance (R). ON Semiconductor materials with high thermal conductivity, high operating frequency, and high charge carrier saturation velocity are well-suited for manufacturing electronic components such as diodes or transistors (especially for power supply applications). Silicon carbide (SiC) is a material possessing these properties and designed for manufacturing electronic components. Specifically, different polytypes of silicon carbide (e.g., 3C-SiC, 4H-SiC, 6H-SiC) are preferred over silicon in terms of the properties listed above.

[0003] Compared to similar devices provided on silicon substrates, electronics provided on silicon carbide substrates offer numerous advantages, such as low output resistance in conduction, low leakage current, high operating temperature, and high operating frequency. Specifically, SiC Schottky diodes exhibit superior switching performance, making SiC electronics particularly suitable for high-frequency applications. Current applications place demands on the electrical properties and long-term reliability of these devices. Summary of the Invention

[0004] This disclosure provides electronic devices and methods for manufacturing electronic devices. Attached Figure Description

[0005] To better understand this disclosure, preferred embodiments thereof will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0006] Figure 1 The MPS device according to a known embodiment is shown in cross-sectional view.

[0007] Figure 2A and Figure 2B The prior art is shown in cross-sectional view. Figure 1 Intermediate manufacturing steps of MPS devices; and

[0008] Figures 3A-3C The cross-sectional view shows the situation according to the prior art. Figure 2A and Figure 2B The steps after which are used in Figure 1 The steps for forming ohmic contacts in MPS devices;

[0009] Figure 4The diagram illustrates the prior art in plan view form. Figures 3A-3B Undesirable areas formed during the manufacturing process;

[0010] Figure 5 An MPS device according to an embodiment of the present disclosure is shown in cross-sectional view.

[0011] Figures 6A-6D The cross-sectional view illustrates the following according to the present disclosure. Figure 5 The manufacturing steps of MPS devices; and

[0012] Figures 7A-7D The diagram illustrates the steps involved in forming a MoS2 semiconductor layer, which can be used for... Figure 6D In the context of the manufacturing steps. Detailed Implementation

[0013] This disclosure will be described with reference to SiC-based merged PiN Schottky MPS devices; however, as will be apparent from the following description, this disclosure is generally applicable to MPS devices based on different types of semiconductors (e.g., GaN).

[0014] Figure 1 The MPS device 1 is shown in the form of a transverse cross-sectional view in a Cartesian (triaxial) reference frame with X, Y, and Z axes.

[0015] MPS device 1 includes: a substrate 3 formed of N-type SiC having a first doping concentration, having a surface 3a opposite to surface 3b, and a thickness of approximately 350 μm; a drift layer 2 formed of N-type SiC (grown epitaxially), having a second doping concentration lower than the first doping concentration, extending on surface 3a of substrate 3, and having a thickness in the range of 5-10 μm; an ohmic contact region 6 (e.g., formed of nickel silicide) extending on surface 3b of substrate 3; a cathode metallization 16 extending on ohmic contact region 6; an anode metallization 8 extending on top surface 2a of drift layer 2; a plurality of junction barrier (JB) elements 9 in drift layer 2 facing top surface 2a of drift layer 2, and each including a corresponding P-type implantation region 9' and an ohmic contact 9" of metallic material; and an edge termination region or guard ring 10 (optional), for example, completely surrounding the P-type implantation region of junction barrier (JB) element 9.

[0016] A Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization portion 8. In some embodiments, the Schottky (semiconductor-metal) junction is formed from a portion of the drift layer 2 that is in direct electrical contact with a corresponding portion of the anode metallization portion 8.

[0017] The region in MPS device 1 that includes JB element 9 and Schottky diode 12 (i.e., the region contained within guard ring 10) is the active region 4 of MPS device 1.

[0018] refer to Figure 2A and Figure 2B , Figure 1 The manufacturing steps of MPS device 1 are provided ( Figure 2A The process involves the masked implantation of a dopant (e.g., boron or aluminum) having a second conductivity type (P). The implanted material is in... Figure 2A Arrow 18 is used to illustrate this. A mask 11, such as a hard mask formed of silicon oxide or TEOS, is used for implantation. This forms the implantation region 9' and the edge termination region 10. Then, in... Figure 2B In the process, mask 11 is removed and a thermal annealing step is performed to activate it. Figure 2A The dopant material is injected during the process. Thermal annealing is performed, for example, at temperatures above 1600°C (e.g., in the range of 1700–1900°C and in some cases even higher).

[0019] refer to Figures 3A-3C The next step is to perform further steps to form the ohmic contact 9". (See reference...) Figure 3A A deposition mask 13, formed of silicon oxide or TEOS, is used to cover the surface area of ​​the drift layer 2 except for the injection region 9' (and the edge termination region 10, if present). In other words, the mask 13 has a through opening 13a at the injection region 9' (and optionally at least a portion of the edge termination region 10). Next, in Figure 3B On mask 13 and through opening 13a ( Figure 3B Nickel deposition is performed inside the metal layer 14). The nickel thus deposited reaches and contacts the injection region 9' and the edge termination region 10 through the through opening 13a.

[0020] refer to Figure 3C The subsequent high-temperature thermal annealing (rapid heat treatment, lasting from 1 minute to 120 minutes in the range of 900°C to 1050°C) allows the ohmic contact 9” of nickel silicide to be formed through a chemical reaction between the deposited nickel and the silicon of the drift layer 2 at the through opening 13a. In fact, the deposited nickel reacts at the location in contact with the surface material of the drift layer 2 to form Ni2Si (i.e., the ohmic contact). Subsequently, a step of removing the metal extending over the mask 13 is performed and the mask 13 is removed.

[0021] The inventor has confirmed that, as Figure 4 As an example, although limited, a reaction still occurs between the nickel in the metal layer 14 and the mask 13 in which they are in direct contact. Figure 4 yes Figure 3BA top view of a portion of the device in the XY plane, where the area is defined by dashed lines, and... Figure 3B It is identified by reference numeral 15 in the attached figure. Figure 4 Involving Figure 3B and Figure 3C The intermediate manufacturing step involves the mask 13 remaining, but the nickel layer 14 being removed. (As...) Figure 4 As shown, irregular regions or islands 17 extend on mask 13, and these irregular regions or islands 17 are due to an undesirable reaction between nickel and silicon in mask 13. The inventors also noted that similar serrated or toothed regions extend beneath mask 13, i.e., on surface 2a of drift layer 2. Figure 4 In the figure, these sawtooth or serrated regions are identified by reference numeral 16 and are formed of a conductive material, including nickel. If the extension of these sawtooth or serrated regions 16 in the XY plane (e.g., along the X-axis) is greater than the corresponding extension of the injection region 9', a short circuit will exist that could lead to device failure. Specifically, if the unwanted conductive region extends into the region dedicated to the Schottky contact, an ohmic or quasi-ohmic contact (a Schottky contact with a low barrier) (which, from an electrical point of view, is a resistance) will be formed on the N-type region; therefore, a continuous current will flow in both forward and reverse bias, thus losing the characteristics of a diode.

[0022] Figure 5 A fused PiN Schottky (MPS) device 50 according to one aspect of this disclosure is shown as a transverse cross-sectional view in a Cartesian (triaxial) reference frame with axes X, Y, and Z.

[0023] The MPS device 50 includes a substrate 53 of a wide bandgap semiconductor material. In some embodiments, the substrate 53 comprises N-type SiC, such as 4H-SiC, having a first N+ doping concentration, having a surface 53a opposite to surface 53b, and a thickness in the range of 50 μm to 350 μm, and in some embodiments, in the range of 160 μm to 200 μm, and in some other embodiments, equal to 180 μm. In some embodiments, the substrate 53 may be formed of GaN.

[0024] An epitaxially grown drift layer 52, formed of N-type SiC (or GaN), has a second N-doping concentration lower than the first doping concentration, extends on the surface 53a of the substrate 53, and has a thickness in the range of 5-15 μm. For example, a region or layer of ohmic contacts 56 formed of nickel silicide extends on the surface 53b of the substrate 53. For example, a bottom metallization 57 of Ti / NiV / Ag or Ti / NiV / Au extends on the region of the ohmic contacts 56.

[0025] One or more P-type doped regions 59, hereinafter referred to as "junction barrier elements" or "JB elements," extend within the drift layer 52 facing or adjacent to the top surface 52a of the drift layer 52. The accompanying drawings illustrate two JB regions 59 by way of non-limiting example. As mentioned, each JB element 59 is a P-type implantation region, and in some embodiments, a P+ type implantation region. Each JB element has, for example, a dopant density greater than 1.10. 18 atoms / cm 3 The doping concentration.

[0026] In some embodiments, the edge termination region or guard ring 60 (optionally) is an injection region of the P-type (P+) that externally defines or surrounds the active region of the device.

[0027] According to one aspect of this disclosure, a semiconductor layer 61 formed of, for example, MoS2 (molybdenum sulfide, also known as molybdenite or molybdenum disulfide) extends on the top surface 52a of the drift layer 52. The semiconductor layer 61 is in electrical contact with the JB element 59 (e.g., in direct contact with the P+ implantation region 59) and with portions of the top surface 52a of the N-type drift layer 52 that are horizontal to the JB element 59.

[0028] Typically, layer 61 is formed of a material belonging to the transition metal dichalcogenides group. In some embodiments, the dichalcogenides are referred to as "transition metal dichalcogenides" or "TMDs" and possess semiconductor properties. TMDs are materials having the chemical formula MX2, where M is a transition metal from group 4 to 10 (e.g., Mo, W, Nb, Ta, etc.) and X is a chalcogenide (e.g., S, Se, Te). In addition to the aforementioned MoS2, the non-limiting list includes MoSe2, MoTe2, WS2, WSe2, WTe2, and NbS2. These materials have a typical layered structure, i.e., they are formed by stacking different crystalline layers bonded together by weak van der Waals bonds. According to the chemical formula MX2, each crystalline layer is formed by the bonding of transition metal atoms with chalcogenide atoms, exhibiting strong covalent bonds. The symmetry of the monolayer is hexagonal or rhombohedral, with atoms arranged in octahedral or trigonal prism coordination. A unique characteristic of semiconductor TMD thin films (such as MoS2) is that their bandgap width and work function depend on the thickness of the stack (i.e., the number of layers). For example, a film made from a single MoS2 layer (0.65 nm thick) has a “direct” bandgap of 1.8–1.9 eV, while a film made from two or more MoS2 layers has an “indirect” bandgap of 1.2 eV.

[0029] Furthermore, according to one aspect of this disclosure, the material of the semiconductor layer 61 is selected based on the materials of the substrate 53 and the epitaxial layer 52. In some embodiments, the material of the semiconductor layer 61 is chosen such that it has good lattice matching with the material of the epitaxial layer 52 forming thereon. For example, the inventors have demonstrated that using MoS2 on a substrate or epitaxial layer formed of SiC or GaN satisfies this requirement.

[0030] The top metallization portion 63 extends on the semiconductor layer 61 and is in electrical contact with the semiconductor layer 61, for example, in direct electrical contact with the semiconductor layer 61.

[0031] A passivation layer 69 extends over the top metallization 63 and at least partially protects the latter. The passivation layer 69 has at least one opening that exposes the top metallization 63 through the passivation layer 69, so that it can be electrically contacted from the outside, for example by wire bonding or other techniques, to bias the device during use.

[0032] According to one aspect of this disclosure, in order to form an ohmic contact at each JB element 59, and, for example, to form a Schottky contact laterally with the JB element 59 at a surface region of the N-type drift layer 52, the semiconductor layer 61 is selectively doped to selectively change its conductivity. In this respect, the semiconductor layer 61 has a region 61' of P-type conductivity at or near the corresponding JB element 59, and a region 61' of N-type conductivity at the surface portion of the drift layer 52, which forms the corresponding Schottky diode 62.

[0033] Along the X-axis, regions 61' and 61" alternate with each other. In addition, each region 61' is adjacent to at least one corresponding region 61" along the X-axis.

[0034] Each region 61' of the P-type extends, for example, vertically along the Z-axis, through the thickness of the semiconductor layer 61 to make electrical contact with a corresponding JB element, wherein it is (at least partially) vertically aligned. Similarly, each region 61” extends, for example, vertically along the Z-axis, through the thickness of the semiconductor layer 61 to make electrical contact with a corresponding surface region of the N-type layer 52.

[0035] Each region 61' forms a corresponding junction barrier diode 58 with the corresponding JB element in electrical contact therewith; similarly, each region 61" forms a corresponding Schottky diode 62 with the corresponding surface portion of the layer 52 in electrical contact therewith.

[0036] The region in MPS device 50 that includes JB diode 58 and Schottky diode 62, such as the region contained within guard ring 60, is the active region of MPS device 50.

[0037] The inventors have demonstrated that the work function of MoS2 materials can be altered, modified, or adjusted through appropriate functionalization of MoS2 (e.g., functionalization to modify the conductivity properties (N-type or P-type) of MoS2). Furthermore, as an alternative or addition to the foregoing, the work function of MoS2 materials can be altered, modified, or adjusted by selecting an appropriate number of stacked MoS2 layers. For example, in the context of this disclosure, "semiconductor layer 61" can be a single MoS2 layer, such as a monolayer with a two-dimensional structure, or, for example, a multilayer of MoS2 with a three-dimensional structure.

[0038] For example, the work function of a MoS2 multilayer can be adjusted, for example, between 4.4 eV and 5.6 eV by appropriate doping with oxygen (O2), which is used to generate a unique doped region with P-type conductivity.

[0039] As another example, the work function of a single MoS2 layer can be adjusted, for example, between 4.1 eV and 6 eV by appropriate doping with oxygen (O2), which is used to generate a unique doped region with P-type conductivity.

[0040] In the context of this disclosure, the term "semiconductor layer 61" includes both multilayer and single-layer.

[0041] The barrier of MoS2 layer 61 can thus be modified by selectively altering the conductivity of the MoS2 layer 61 and / or the number of its (multi-layer or single-layer) sublayers.

[0042] For example, in the case of N-type doped MoS2, a Schottky contact is formed with an N-type 4H-SiC substrate, and the barrier height is about 1.3 eV in the multilayer case and about 1 eV in the monolayer case.

[0043] For example, in the case of P-type doped MoS2, an ohmic contact is formed with the P+ implantation region in the N-type 4H-SiC substrate, with a barrier height of approximately 0.6 eV in the multilayer case and approximately 0.2 eV in the monolayer case.

[0044] refer to Figures 6A-6D To describe the manufacturing steps of MPS device 50.

[0045] refer to Figure 6A A wafer 100 is arranged thereon, the wafer 100 including a substrate 53 formed of SiC, such as 4H-SiC; however, other polytypes may be used. As mentioned above, other materials, such as GaN, may also be used.

[0046] Substrate 53 has a first type of conductivity, in some example embodiments an N-type dopant, and is provided with a front surface 53a and a rear surface 53b opposite to each other along the Z-axis. Substrate 53 has, for example, a conductivity of 1.10. 19 -1·10 20atoms / cm 3 N+ doping concentration within the range.

[0047] The front side of the wafer 100 corresponds to the front surface 53a, and the back side of the wafer 100 corresponds to the rear surface 53b.

[0048] The drift layer 52, formed of silicon carbide, is conductive N, and its N-doping concentration is lower than that of the substrate 53, for example, at 1.10. 14 -5·10 16 atoms / cm 3 Within the range, it is formed, for example, by epitaxial growth on the front surface 53a of the substrate 53. The drift layer 52 is made of SiC, such as 4H-SiC, but other SiC polytypes may also be used, or alternatively, GaN may be used.

[0049] The drift layer 52 extends in thickness between the top side 52a and the bottom side 52b, with the bottom side 52b in direct contact with the front surface 53a of the substrate 53.

[0050] Then, Figure 6B The hard mask 70 is formed on the top side 52a of the drift layer 52, for example, by depositing a photoresist or tetraethoxysilane (TEOS) or other suitable material for this purpose. The hard mask 70 has a thickness in the range of 0.5 μm to 2 μm, or in any case has a thickness that makes it suitable for masking the following references. Figure 6B The thickness of the implant described. The hard mask 70 extends into the region of the wafer 100, where the active region 54 of the MPS device 50 will be formed in a subsequent step.

[0051] In the plan, it has been referenced Figure 5 The hard mask 70 covers the area on the top side 52a of the drift layer 52 in the XY plane where a Schottky cell (diode 62) will be formed, and exposes the area on the top side 52a of the drift layer 52 where an injection region 59 will be formed.

[0052] Then, a hard mask 70 is used to perform the implantation of a dopant (e.g., boron or aluminum) having a second type of conductivity, here for example, P-type (the implant is indicated by arrow 72 in the figure). Figure 6B During the steps, a protective ring 60 is also formed (if present).

[0053] In one example embodiment, Figure 6B The implantation process involves one or more implantations of a dopant material exhibiting type II conductivity, with implantation energies ranging from 30 keV to 400 keV and doses between 1.10 keV and 1.10 keV. 12 atoms / cm 2 -1·10 15atoms / cm 2 Within a certain range, to form a doping concentration greater than 1.10 18 atoms / cm 3 The injection region 59 thus formed has a depth in the range of 0.4 μm to 1 μm as measured from the surface 52a.

[0054] Subsequently, Figure 6C Mask 70 was removed, and, Figure 6D For example, a semiconductor layer 61 formed of MoS2 is formed.

[0055] An example process for forming semiconductor layer 61 is now described, which is formed by CVD (“chemical vapor deposition”) deposition of MoS2 on epitaxial layer 52, in this example epitaxial layer 52 being SiC. Reference Figures 7A-7C The process is described, wherein a dual-zone reactor 90 is schematically illustrated, comprising a quartz tubular body and formed by two zones 90a, 90b that can be heated independently of each other.

[0056] refer to Figure 7A Sulfur (S) and molybdenum (Mo, or MoO) x For example, where x = 3) is used as a precursor for growing MoS2. The sulfur precursor (e.g., in powder form) is arranged in a crucible 92 in region 90a at a distance (about 7-15 cm) from the wafer on which MoS2 growth will be performed. The molybdenum precursor (e.g., also in powder form) is arranged in a corresponding crucible 93 in region 90b, close to the wafer 100 on which MoS2 growth will be performed (i.e., in region 90b between the wafer 100 and the sulfur crucible).

[0057] refer to Figure 7B Region 90a is heated to a temperature T1 in the range of 100-200°C, for example, a temperature in the range of 150-160°C, causing sulfur deposited on wafer 100 to evaporate. Region 90b is heated to a temperature T2 above temperature T1 (and therefore in the range of 700-800°C), causing molybdenum deposited on wafer 100 to evaporate.

[0058] This process occurs in the presence of a carrier gas, which in turn... Figures 7A-7C Arrow 91 indicates the direction in which gas is introduced into reactor 90. The gas, for example, is argon (Ar) introduced at approximately 100 sccm. The direction of the gas pushes sulfur and molybdenum vapor toward wafer 100.

[0059] At the level of chip 100, Figure 7C Sulfur and molybdenum are deposited on it, forming a MoS2 layer 61 through a chemical reaction.

[0060] The number of MoS2 sublayers (single or multiple layers) formed during the reaction of sulfur and molybdenum vapor on wafer 100 can be controlled by adjusting one or more of the following: temperature T2, duration of the growth process, and flow rate of sulfur vapor (by adjusting the flow rate of carrier gas).

[0061] Alternatively or additionally, MoS2 multilayers can be deposited, and one or more layers can then be selectively removed by etching techniques until the multilayer is reduced to a single layer / monolayer.

[0062] Other relative arrangements of crucibles 92 and 93 and wafer 100 within reactor 90 are possible. For example, Figure 7D The crucible 93 can be arranged below the wafer 100. In this case, the wafer 100 is oriented such that its top surface (on which layer 61 will be formed) faces the crucible 93.

[0063] Other techniques or methods may be used to form the semiconductor layer 61 within the context of this disclosure. Such methods (known in the literature) are of the bottom-up and top-down type and include: atomic layer deposition (ALD), pulsed laser deposition (PLD), sputtering.

[0064] The semiconductor layer 61 thus formed exhibits N-type conductivity without further doping, which remains possible even if the concentration of most conductive materials is to be further adjusted.

[0065] Return to Figure 6D A mask 80 (e.g., photoresist) with openings 80a is formed in the semiconductor layer 61 at the regions that need to be functionalized to alter its conductivity. Surface regions 61a of the semiconductor layer 61 are exposed through the openings 80a in the photoresist. These openings 80a (along the Z-axis, or in a top view in the XY plane) are at least partially aligned with the corresponding JB element 59.

[0066] A wafer 100, provided with a mask 80, is arranged in a reactor where an oxygen plasma is generated for functionalizing a semiconductor layer 61. The oxygen reacts with the material of the semiconductor layer 61 exposed through opening 80a, providing selective p-type doping. (Reference) Figure 5 The doped region 61' (P-type) is described, and in context, region 61" (N-type) is thus formed.

[0067] Functionalization of MoS2 for forming the P-type region 61' occurs, for example, via plasma processing and can be performed using a variety of chemicals, including O2, CHF3, CF4, and SF6.

[0068] The conductivity of region 61” of the semiconductor layer 61 covered by mask 80 will not be changed by the functionalization step of O2; therefore, these regions retain N-type conductivity.

[0069] Then mask 80 can be removed.

[0070] The subsequent manufacturing steps are performed in a manner not shown in the figure, forming the top metallization and passivation layer in a manner known per se, and therefore are not further described or illustrated in the figure. The formation of ohmic contacts on the back side of the wafer and the formation of the bottom metallization are also known per se, and therefore will not be described further.

[0071] The advantages provided by this disclosure will become apparent upon examination of the features provided in this specification.

[0072] In some embodiments, the “IFSM robustness” value of the SiC MPS diode is maximized, the manufacturing process is simplified, and problems related to protrusions or nickel residues described with reference to the prior art are avoided and overcome.

[0073] Finally, it is obvious that modifications and changes can be made to the descriptions and illustrations herein without departing from the scope of this disclosure as defined in the appended claims.

[0074] A method for manufacturing a merged PiN Schottky MPS device (50) can be summarized as comprising the following steps: implanting a dopant material at the front side (52a) of a solid (52, 53) having a first conductivity (N), the dopant material having a second conductivity (P) opposite to the first conductivity (N), thereby forming an implantation region (59) extending from the front side (52a) into the solid; forming a semiconductor layer (61) on the front side (52a), the material of the semiconductor layer (61) being a transition metal dichalcogenide (TMD) having the first conductivity (N); selectively functionalizing a first region (61') of the semiconductor layer (61) by means of a chemical substance to generate the second conductivity (P) in the first region, the first region being in electrical contact with the implantation region (59) and adjacent to a second region of the semiconductor layer (61) having the first conductivity (N), the second region being in electrical contact with a corresponding surface portion of the front side (52a) having the first conductivity (N).

[0075] The first region (61') may extend through the thickness of the semiconductor layer (61) and at least partially reach the front side (52a) of the solid (52, 53) at the implantation region (59).

[0076] Functionalizing the first region (61') may include forming an ohmic contact at the interface between the solid (52, 53) and the injection region (59).

[0077] Forming an ohmic contact can include forming a junction barrier JB diode.

[0078] The step of forming a semiconductor layer (61) may include forming a Schottky diode at the interface between the second region (61”) and the solid, transverse to the implantation region (59).

[0079] The solid (52, 53) material can be one of the following: SiC, 4H-SiC, GaN, AlN, diamond, Ga2O3.

[0080] The material of the semiconductor layer (61) can be one of MoS2, MoSe2, MoTe2, WS2, WSe2, or WTe2.

[0081] The method may further include the following steps: forming a first electrical terminal shared by the JB diode and the Schottky diode on a semiconductor layer (61), the first electrical terminal including a first metal layer; and forming a second electrical terminal (57) shared by the JB diode and the Schottky diode on a back side (53b) opposite to the front side (52a) of the solid, the second electrical terminal including a second metal layer.

[0082] The method may further include the following steps: arranging a substrate (53); epitaxially growing an epitaxial layer (52) on the substrate (53) to form a drift layer of the MPS device (50), wherein the substrate (53) and the epitaxial layer (52) together form the solid.

[0083] The steps of forming the semiconductor layer (61) may include performing a CVD growth process, or an ALD process, or a sputtering process, or a PLD process.

[0084] The first conductivity can be N-type, the second conductivity can be P-type, and the step of functionalizing the first region (61') can include doping the first region (61') with O2.

[0085] The merged PiN Schottky MPS device (50) can be summarized as including: a solid (52, 53) having a first conductivity (N); an implantation region (59) extending into the solid (52, 53) facing the front side (52a) of the solid (52, 53) and having a second conductivity (P) opposite to the first conductivity (N); and a semiconductor layer (61) extending on the front side (52a) and formed of a transition metal dichalcogenide (TMD) material, wherein a first region (61') of the semiconductor layer (61) has the second conductivity (P) and extends in electrical contact with the implantation region (59), and a second region (61') of the semiconductor layer (61) has the first conductivity (N) and extends adjacent to the first region (61') and in electrical contact with a corresponding surface portion of the front side (52a) having the first conductivity (N).

[0086] The first region (61') can extend through the thickness of the semiconductor layer (61) and reach at least partially the front side (52a) of the solid (52, 53) at the implantation region (59).

[0087] The first region (61') can form an ohmic contact with the injection region (59).

[0088] At the first region (61'), the semiconductor layer (61) can form a junction barrier JB diode together with the injection region (59).

[0089] In the second region (61”), the semiconductor layer (61) can be formed together with the solid (52, 53) to form a Schottky diode.

[0090] The solid (52, 53) material can be one of the following: SiC, 4H-SiC, GaN, AlN, diamond, Ga2O3.

[0091] The material of the semiconductor layer (61) can be one of MoS2, MoSe2, MoTe2, WS2, WSe2, or WTe2.

[0092] The device may also include a first electrical terminal shared by the JB diode and the Schottky diode, which may include a first metal layer on the semiconductor layer (61); and a second electrical terminal (57) shared by the JB diode and the Schottky diode, which may include a second metal layer located on the back side (53b) opposite to the front side (52a) of the solid.

[0093] The solid may include a substrate (53); and an epitaxial layer (52) on the substrate (53), wherein the epitaxial layer (52) may be a drift layer of the MPS device (50).

[0094] The first conductivity can be N-type, and the second conductivity can be P-type.

[0095] The various embodiments described above can be combined to provide further embodiments. If desired, aspects of the embodiments can be modified to employ the concepts of various embodiments to provide even more advanced embodiments.

[0096] These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents claimed for such embodiments. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for fabricating a semiconductor device, comprising: implanting a dopant species at a front side of a solid having a first type of electrical conductivity, the dopant species having a second type of electrical conductivity opposite the first type of electrical conductivity, thereby forming an implanted region extending from the front side into the solid; forming a semiconductor layer of a transition metal dichalcogenide (TMD) material at the front side, the semiconductor layer having the first type of electrical conductivity; selectively functionalizing a first region of the semiconductor layer by a dopant species, thereby generating the second type of electrical conductivity in the first region, the first region being in electrical contact with the implanted region and laterally adjacent to a second region of the semiconductor layer having the first type of electrical conductivity, the second region being in electrical contact with a respective surface portion of the front side having the first type of electrical conductivity.

2. The method of claim 1, wherein the first region extends throughout a thickness of the semiconductor layer, reaching the front side of the solid, and at least partially overlaps the implanted region.

3. The method of claim 1, wherein functionalizing the first region comprises: forming an ohmic contact at an interface between the implanted region and the first region.

4. The method of claim 3, wherein forming the ohmic contact comprises forming a junction barrier (JB) diode.

5. The method of claim 4, wherein forming the semiconductor layer comprises: forming a Schottky diode laterally to the implanted region at an interface between the second region and the solid.

6. The method of claim 1, wherein a material of the solid is one of: SiC, 4H-SiC, GaN, AlN, diamond, or Ga2O3.

7. The method of claim 1, wherein a material of the semiconductor layer is one or more of: MoS2, MoSe2, MoTe2, WS2, WSe2, or WTe2.

8. The method of claim 5, further comprising: forming a first electrical terminal common to the JB diode and the Schottky diode on the semiconductor layer; and forming a second electrical terminal common to the JB diode and the Schottky diode at a back side opposite the front side of the solid.

9. The method of claim 1, further comprising: disposing a substrate; epitaxially growing an epitaxial layer on the substrate, wherein the substrate and epitaxial layer together form the solid.

10. The method of claim 1, wherein forming the semiconductor layer comprises performing a CVD growth process, an ALD process, a sputtering process, or a PLD process. doping the first region using O2.

11. The method of claim 1, wherein the first type of electrical conductivity is N-type, the second type of electrical conductivity is P-type, and functionalizing the first region comprises:

12. A merged PiN Schottky device, comprising: a solid having a first type of electrical conductivity; an implanted region extending from a front side of the solid into the solid, the implanted region having a second type of electrical conductivity different from the first type of electrical conductivity; and a semiconductor layer on the front side of the solid, the semiconductor layer having a transition metal dichalcogenide (TMD) material, ​ ​ wherein a first region of the semiconductor layer has the second type of electrical conductivity and is in electrical contact with the implanted region, and a second region of the semiconductor layer has the first type of electrical conductivity and is adjacent to the first region and in electrical contact with a respective surface portion of the front side having the first type of electrical conductivity.

13. The device of claim 12, wherein the first region extends through a thickness of the semiconductor layer, reaching the front side of the solid, and at least partially overlaps the implanted region.

14. The device of claim 12, wherein the first region forms an ohmic contact with the implanted region.

15. The device of claim 14, wherein the first region of the semiconductor layer forms a junction barrier JB diode with the implanted region.

16. The device of claim 15, wherein the second region of the semiconductor layer forms a Schottky diode with the solid.

17. The device of claim 12, wherein a material of the solid is one of: SiC, 4H-SiC, GaN, AlN, diamond, Ga2O3.

18. The device of claim 12, wherein a material of the semiconductor layer is one or more of: MoS2, MoSe2, MoTe2, WS2, WSe2, or WTe2.

19. The device of claim 16, further comprising: a first electrical terminal on the semiconductor layer, shared by the JB diode and the Schottky diode; and a second electrical terminal on a back side opposite the front side of the solid, shared by the JB diode and the Schottky diode.

20. A semiconductor device, comprising: a substrate; an epitaxial layer formed of a wide bandgap semiconductor material on the substrate, the epitaxial layer having a first type of electrical conductivity; a first doped region in the epitaxial layer and adjacent to a surface of the epitaxial layer away from the substrate, the doped region having a second type of electrical conductivity; and a semiconductor layer on the epitaxial layer, the semiconductor layer having a transition metal dichalcogenide, TMD, material, the semiconductor layer including a second doped region extending through a thickness of the semiconductor layer and overlapping the first doped region, the second doped region having the second type of electrical conductivity. a third doped region in the epitaxial layer, the third doped region laterally surrounding the first doped region. ​ 21. The semiconductor device of claim 20, further comprising: ​

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