Semiconductor test structures

Abstract

The present application relates to a semiconductor test structure. The semiconductor test structure includes: a first test circuit, a second test circuit, a third test circuit, and a fourth test circuit that are sequentially connected end to end to form a circular closed circuit; a plurality of diodes, respectively connected between adjacent test circuits; a first test array and a second test array, the first test array and the second test array both including a plurality of test units spaced apart along a first direction; the test units each including a multi-layer spaced apart metal layer, a dielectric layer, and a conductive plug. The semiconductor test structure of the present application, by providing a first test array and a second test array and adding diodes, can simultaneously detect the reliability of the dielectric layer between the conductive plugs corresponding to two adjacent parallel metal layers and the reliability of the dielectric layer between the conductive plug located at the end of the metal layer and the metal layer adjacent in the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor test structure. Background Art

[0002] During the specialized IC manufacturing process, two layers of conductive plugs are stacked directly on top of each other rather than resting on metal traces. This structure can lead to misalignment of the two layers of conductive plugs during fabrication. Larger process variations increase the risk of breakdown between adjacent conductive plugs.

[0003] Currently, a comb-tooth structure is commonly used to detect the risk of dielectric breakdown between conductive plugs. However, in this structure, conductive plugs are only provided between the upper and lower metal layers of the comb-tooth portion, and no conductive plugs are provided below the metal layer that serves as the connection between the comb-tooth portions. Therefore, this structure is limited to detecting the reliability of the dielectric layer between the conductive plugs corresponding to two adjacent parallel metal layers (i.e., adjacent comb-tooth portions). For the conductive plug located at the end of the metal layer serving as the comb-tooth portion, since it is adjacent to a connection portion (its own connection portion or a connection portion of another comb-tooth structure), when the two layers of conductive plugs at the end of the metal layer of the comb-tooth portion are misaligned toward the end (i.e., toward the connection portion), the reliability of the dielectric layer between the conductive plug and the metal layer of the adjacent connection portion cannot be detected. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor test structure to solve the above-mentioned problem of being unable to detect the reliability of the dielectric layer between the conductive plug located at the end of the metal layer and the adjacent metal layer.

[0005] To achieve the above objectives, the present application provides a semiconductor test structure, comprising:

[0006] A first test circuit, a second test circuit, a third test circuit, and a fourth test circuit are sequentially connected end to end to form a ring closed circuit;

[0007] A plurality of diodes are respectively connected between adjacent test circuits;

[0008] A first test array and a second test array, each comprising a plurality of test cells spaced apart along a first direction; each test cell comprising a plurality of metal layers, a dielectric layer, and conductive plugs spaced apart, wherein the dielectric layer is located between adjacent metal layers; the conductive plug structure comprises a plurality of conductive plugs stacked from bottom to top, located within the dielectric layer, and electrically connecting adjacent metal layers; in the first test array, the test cells located in odd columns are connected to the second test circuit, and the test cells located in even columns are connected to the third test circuit; in the second test array, the test cells located in odd columns are connected to the fourth test circuit, and the test cells located in even columns are connected to the first test circuit; the first test array and the second test array are spaced apart along a second direction, which intersects with the first direction.

[0009] The semiconductor test structure of the present application, by setting up a first test array, a second test array, and adding diodes, can simultaneously detect the reliability issues of the dielectric layer between the conductive plugs corresponding to two adjacent parallel metal layers, as well as the reliability of the dielectric layer between the conductive plug located at the end of the metal layer (i.e., the conductive plug closest to another test unit) and the adjacent metal layer in the second direction.

[0010] In one embodiment, the plurality of diodes include a first diode, a second diode, a third diode, and a fourth diode;

[0011] The first test circuit includes a first test pad and a second test pad, the first test pad is connected to the second test pad; in the second test array, the test cells located in even-numbered columns are connected between the first test pad and the second test pad;

[0012] The second test circuit includes a third test pad and a fourth test pad, the third test pad is connected to the fourth test pad; the anode of the first diode is connected to the first test pad, and the cathode of the first diode is connected to the third test pad; in the first test array, the test cells located in odd columns are connected between the third test pad and the fourth test pad;

[0013] The third test circuit includes a fifth test pad and a sixth test pad, the fifth test pad is connected to the sixth test pad; the anode of the third diode is connected to the sixth test pad, and the cathode of the third diode is connected to the fourth test pad; in the first test array, the test cells located in even-numbered columns are connected between the fifth test pad and the sixth test pad;

[0014] The fourth test circuit includes a seventh test pad and an eighth test pad, the seventh test pad is connected to the eighth test pad; the anode of the second diode is connected to the seventh test pad, and the cathode of the second diode is connected to the fifth test pad; the anode of the fourth diode is connected to the eighth test pad, and the cathode of the fourth diode is connected to the second test pad; in the second test array, the test units located in odd columns are connected between the seventh test pad and the eighth test pad.

[0015] In one embodiment, the number of the test units in the first test array is the same as the number of the test units in the second test array, and are arranged in a one-to-one correspondence.

[0016] In one embodiment, a spacing between the test cells in the first test array and the corresponding test cells in the second test array is smaller than a spacing between adjacent test cells in the first test array and a spacing between adjacent test cells in the second test array.

[0017] In one embodiment, a spacing between the test cells in the first test array and the corresponding test cells in the second test array complies with minimum design rules.

[0018] In one embodiment, the testing unit comprises:

[0019] a first metal layer extending along the second direction;

[0020] a first conductive plug, located on an upper surface of the first metal layer;

[0021] a second conductive plug, located on an upper surface of the first conductive plug;

[0022] The second metal layer is located on the upper surface of the second conductive plug and extends along the second direction.

[0023] In one embodiment, the dielectric layer is located between the first metal layer and the second metal layer.

[0024] In one embodiment, the number of the first conductive plugs and the number of the second conductive plugs are both plural.

[0025] In one embodiment, in the same test unit, a plurality of the first conductive plugs and a plurality of the second conductive plugs are arranged at intervals along the second direction.

[0026] In one embodiment, the first metal layer and the second metal layer are arranged in correspondence with each other up and down; in the same test unit, the spacing between adjacent first conductive plugs, the spacing between adjacent second conductive plugs, and the spacing between the first conductive plug and the second conductive plug located on the outermost sides and the end faces of the first metal layer and the end faces of the second metal layer all comply with the minimum design rules. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic diagram of a top view of a semiconductor test structure;

[0029] Figure 2 For the Figure 1 Schematic diagram of the cross-sectional structure in the AA direction;

[0030] Figure 3 For the Figure 1 Schematic diagram of the cross-sectional structure in the middle BB direction;

[0031] Figure 4 A schematic top view of the semiconductor test structure provided in this application;

[0032] Figure 5 For the Figure 4 Schematic diagram of the cross-sectional structure in the AA direction.

[0033] Description of reference numerals:

[0034] 10. First comb-tooth structure; 101. Comb-tooth portion; 1011. First metal layer; 1012. First conductive plug; 1013. Second conductive plug; 1014. Second conductive layer; 102. Connecting portion; 11. Second comb-tooth structure; 111. Comb-tooth portion; 1111. First metal layer; 1112. First conductive plug; 1113. Second conductive plug; 1114. Second metal layer; 112. Connecting portion; 20. Test unit; 201. First metal layer; 202. First conductive plug; 203. Second conductive plug; 204. Second metal layer; 21. First test array; 22. Second test array. DETAILED DESCRIPTION

[0035] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion.

[0038] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0039] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] During the specialized IC manufacturing process, two layers of conductive plugs are stacked directly on top of each other rather than resting on metal traces. This structure can lead to misalignment of the two layers of conductive plugs during fabrication. Larger process variations increase the risk of breakdown between adjacent conductive plugs.

[0041] Usually adopt Figure 1 The comb-tooth structure shown is used to detect the risk of dielectric layer breakdown between conductive plugs. Figure 1 The comb tooth structure includes a first comb tooth structure 10 and a second comb tooth structure 11. The first comb tooth structure 10 includes a plurality of comb tooth portions 101 arranged in parallel and spaced apart and a connecting portion 102 connecting one end of the plurality of comb tooth portions 101 in series. The second comb tooth structure 11 includes a plurality of comb tooth portions 111 arranged in parallel and spaced apart and a connecting portion 112 connecting one end of the plurality of comb tooth portions 111 in series. Figure 2 As shown, the comb-tooth portion 101 includes a first metal layer 1011, a first conductive plug 1012, a second conductive plug 1013, and a second metal layer 1014 stacked sequentially from bottom to top; the comb-tooth portion 111 includes a first metal layer 1111, a first conductive plug 1112, a second conductive plug 1113, and a second metal layer 1114 stacked sequentially from bottom to top. Figure 3As shown, the connecting portion 102 may include only the first metal layer 1011. Of course, in other examples, the connecting portion 102 may also include only the second metal layer 1014. The specific structure of the connecting portion 112 may be the same as that of the connecting portion 102, and will not be repeated here. However, in the above-mentioned comb-tooth structure, only the comb-tooth portions 101 and 111 are provided with conductive plugs, while the connecting portions 102 and 112 are not provided with conductive plugs. Therefore, this comb-tooth structure is limited to detecting the reliability of the dielectric layer between the conductive plugs corresponding to two adjacent parallel metal layers (i.e., adjacent comb-tooth portions). As for the conductive plug located at the end of the comb-tooth portion 101 or the comb-tooth portion 111, since it is adjacent to the connecting portion 102 or the connecting portion 112, when the first conductive plug and the second conductive plug stacked up and down at the end of the comb-tooth portion 101 or the end of the comb-tooth portion 111 are misaligned toward the end (i.e., toward the connecting portion 102 or the connecting portion 112), the reliability of the dielectric layer between the conductive plug and the metal layer of the adjacent connecting portion cannot be detected. Specifically, it can be Figure 3 For example, when the second conductive plug 1113 and the first conductive plug 1112 exist in the first metal layer 1011 serving as the connecting portion 102, the reliability of the dielectric layer between the first conductive plug 1112 and the second conductive plug 1113 and the first metal layer 1011 serving as the connecting portion 102 cannot be detected through this structure.

[0042] In order to solve the above problems, Figure 4 As shown, the present application provides a semiconductor test structure, which includes: a first test circuit, a second test circuit, a third test circuit, and a fourth test circuit connected end to end in a circular closed circuit; a plurality of diodes connected between adjacent test circuits; a first test array 21 and a second test array 22, each of which includes a plurality of test units 20 arranged at intervals along a first direction; each test unit 20 includes multiple layers of metal layers, dielectric layers, and conductive plugs arranged at intervals, wherein the dielectric layers are located between adjacent metal layers. The conductive plug structure includes multiple conductive plugs stacked from bottom to top, located within the dielectric layer and electrically connecting adjacent metal layers. In the first test array 21, the test cells 20 located in odd-numbered columns are connected to the second test circuit, and the test cells 20 located in even-numbered columns are connected to the third test circuit. In the second test array 22, the test cells 20 located in odd-numbered columns are connected to the fourth test circuit, and the test cells 20 located in even-numbered columns are connected to the first test circuit. The first test array 21 and the second test array 22 are arranged in a second direction with intervals, and the second direction intersects the first direction.

[0043] The semiconductor test structure of the present application, by providing a first test array 21, a second test array 22, and adding diodes, can simultaneously detect the reliability of the dielectric layer between the conductive plugs corresponding to two adjacent parallel metal layers, as well as the reliability of the dielectric layer between the conductive plug located at the end of the metal layer (i.e., the conductive plug closest to another test unit) and the adjacent metal layer in the second direction.

[0044] In one embodiment, Figure 4 As shown, the plurality of diodes include a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4; the first test circuit includes a first test pad PAD1 and a second test pad PAD2, and the first test pad PAD1 is connected to the second test pad PAD2; in the second test array 22, the test units 20 located in the even columns are connected between the first test pad PAD1 and the second test pad PAD2; the second test circuit includes a third test pad PAD3 and a fourth test pad PAD4, and the third test pad PAD3 is connected to the fourth test pad PAD4; the anode of the first diode D1 is connected to the first test pad PAD1, and the cathode of the first diode D1 is connected to the third test pad PAD3; in the first test array 21, the test units 20 located in the odd columns are connected between the third test pad PAD3 and the fourth test pad PAD4; the third test circuit includes a fifth test pad PAD5 and a sixth test pad PAD6 , the fifth test pad PAD5 is connected to the sixth test pad PAD6; the anode of the third diode D3 is connected to the sixth test pad PAD6, and the cathode of the third diode D3 is connected to the fourth test pad PAD4; in the first test array 21, the test units 20 located in the even columns are connected between the fifth test pad PAD5 and the sixth test pad PAD6; the fourth test circuit includes the seventh test pad PAD7 and the eighth test pad PAD8, and the seventh test pad PAD7 is connected to the eighth test pad PAD8; the anode of the second diode D2 is connected to the seventh test pad PAD7, and the cathode of the second diode D2 is connected to the fifth test pad PAD5; the anode of the fourth diode D4 is connected to the eighth test pad PAD8, and the cathode of the fourth diode D4 is connected to the second test pad PAD2; in the second test array 22, the test units 20 located in the odd columns are connected between the seventh test pad PAD7 and the eighth test pad PAD8.

[0045] As an example, the first test pad PAD1 and the second test pad PAD2 can be connected through a metal wire; the first diode D1 and the first test pad PAD1 and the third test pad PAD3 can be connected through a metal wire; the third test pad PAD3 and the fourth test pad PAD4 can also be connected through a metal wire; the third diode D3 and the fourth test pad PAD4 and the sixth test pad PAD6 can be connected through a metal wire; the fifth test pad PAD5 and the sixth test pad PAD6 can be connected through a metal wire; the second diode D2 and the fifth test pad PAD5 and the seventh test pad PAD7 can all be connected through a metal wire; the seventh test pad PAD7 and the eighth test pad PAD8 can be connected through a metal wire; the fourth diode D4 and the second test pad PAD2 and the eighth test pad PAD8 can all be connected through a metal wire.

[0046] Specifically, in the present application, by introducing a diode between the test pads, the test voltage during the test process can be controlled by the diode.

[0047] As an example, the number of test cells 20 in the first test array 21 is the same as the number of test cells 20 in the second test array 22, and they are arranged in a one-to-one correspondence. Specifically, the test cells 20 in the first test array 21 and the test cells 20 in the second test array 22 can be arranged in a one-to-one correspondence along the second direction.

[0048] As an example, the spacing between the test cells 20 in the first test array 21 and the corresponding test cells 20 in the second test array 22 can be smaller than the spacing between adjacent test cells 20 in the first test array 21 and the spacing between adjacent test cells 20 in the second test array 22. Because the spacing between the test cells 20 in the first test array 21 and the corresponding test cells 20 in the second test array 22 is the smallest, the conductive plug structure in the first test array 21 closest to the second test array 22 is closest to the metal layer in the second test array 22, and the breakdown risk between the two is the greatest. The semiconductor test structure of the present application, by providing the first test array 21 and the second test array 22 and adding diodes, can simultaneously detect the reliability of the dielectric layer between the conductive plugs corresponding to two adjacent parallel metal layers, as well as the reliability of the dielectric layer between the conductive plug at the end of the metal layer (i.e., the conductive plug closest to another test cell) and the metal layer adjacent in the second direction.

[0049] Of course, in other examples, the spacing between the test cells 20 in the first test array 21 and the corresponding test cells 20 in the second test array 22 may also be greater than or equal to the spacing between adjacent test cells 20 in the first test array 21 and the spacing between adjacent test cells 20 in the second test array 22 .

[0050] As an example, the spacing between the test cells 20 in the first test array 21 and the corresponding test cells 20 in the second test array 22 needs to comply with the minimum design rules; and the minimum spacing between the test cells 20 in the first test array 21 and the corresponding test cells 20 in the second test array 22 must at least comply with the minimum design rules. Of course, the spacing between the test cells 20 in the first test array 21 and the corresponding test cells 20 in the second test array 22 can also be larger than the spacing dimension specified by the minimum design rules.

[0051] As an example, Figure 5 As shown, the test unit 20 may include: a first metal layer 201, the first metal layer 201 extends along the second direction; a first conductive plug 202, the first conductive plug 202 is located on the upper surface of the first metal layer 201; a second conductive plug 203, the second conductive plug 203 is located on the upper surface of the first conductive plug 202; and a second metal layer 204, the second metal layer 204 is located on the upper surface of the second conductive plug 203 and extends along the second direction.

[0052] As an example, the first metal layer 201 and the second metal layer 204 can both be but are not limited to copper layers, nickel layers or chromium layers, etc.; the first conductive plug 202 and the second conductive plug 203 can both include copper conductive plugs. Of course, a metal barrier layer such as a titanium nitride layer can also be provided between the copper conductive plug and the dielectric layer.

[0053] As an example, a dielectric layer (not shown) may be located between the first metal layer 201 and the second metal layer 204. Specifically, the dielectric layer may be located between the first metal layer 201 and the second metal layer 204, and between adjacent conductive plugs.

[0054] As an example, the dielectric layer may include but is not limited to an oxide layer or a nitride layer; more specifically, the dielectric layer may include but is not limited to a silicon oxide layer or a silicon nitride layer.

[0055] It should be noted that Figure 4 The top layer of the test unit 20 should be the second metal layer 204, and the second conductive plug 203 is as follows Figure 5 The second metal layer 204 is located below the second metal layer 204 and is blocked by the second metal layer 204, and cannot be seen in the top view, but for the convenience of explaining the solution of this application, Figure 4 The second conductive plug 203 located below the second metal layer 204 is also shown.

[0056] As an example, the number of the first conductive plugs 202 and the number of the second conductive plugs 203 are both multiple. Specifically, the number of the first conductive plugs 202 and the number of the second conductive plugs 203 in the same test unit 20 are both multiple; the number of the first conductive plugs 202 and the number of the second conductive plugs 203 in the same test unit 20 can be set according to actual needs. Figure 4 In the example, the number of the first conductive plugs 202 and the number of the second conductive plugs 203 in the same test unit 20 are both three. However, in other examples, the number of the first conductive plugs 202 and the number of the second conductive plugs 203 in the same test unit 20 are not the same. Figure 4 The number is limited to , it can also be two, four, five, six or even more.

[0057] As an example, in the same test unit 20 , the plurality of first conductive plugs 202 and the plurality of second conductive plugs 203 are arranged at intervals along the second direction.

[0058] As an example, the first metal layer 201 and the second metal layer 204 are arranged in a vertically corresponding manner; specifically, the first metal layer 201 and the second metal layer 204 in the same test unit 20 are arranged in a vertically corresponding manner, that is, the orthographic projection of the second metal layer 204 on the first metal layer 201 completely overlaps with the first metal layer 201. Of course, in other examples, the first metal layer 201 and the second metal layer 204 in the same test unit 20 may also be arranged in a staggered manner.

[0059] As an example, in the same test unit 20, the spacing between adjacent first conductive plugs 202 and the spacing between adjacent second conductive plugs 203 both need to comply with the minimum design rules; that is, in the same test unit 20, the spacing between adjacent first conductive plugs 202 and the spacing between adjacent second conductive plugs 203 both need to be greater than or equal to the minimum size required by the minimum design rules.

[0060] As an example, in the same test unit 20, the spacing between the first conductive plug 202 and the second conductive plug 203 located on the outermost side and the end surface of the first metal layer 201 and the end surface of the second metal layer 204 both need to comply with the minimum design rules; in the same test unit 20, the spacing between the first conductive plug 202 and the second conductive plug 203 located on the outermost side and the end surface of the first metal layer 201 and the end surface of the second metal layer 204 both need to be greater than or equal to the minimum size required by the minimum design rules.

[0061] The testing method for the semiconductor test structure of the present application is as follows: a positive voltage is applied to the first test pad PAD1, and the fifth test pad PAD5 is grounded. At this time, the first diode D1 and the second diode D2 are forward-conducting, the third diode D3 and the fourth diode D4 are reverse-blocking, the odd-numbered test cells 20 in the first test array 21 and the even-numbered test cells 20 in the second test array 22 are positively charged, and the even-numbered test cells 20 in the first test array 21 and the second test array 22 are zero-voltage. Through this testing method, dielectric breakdown can be detected regardless of whether it occurs between conductive plugs in the first direction or between conductive plugs in the second direction. This allows for simultaneous detection of dielectric layer reliability issues between conductive plugs corresponding to two adjacent parallel metal layers, as well as the reliability of the dielectric layer between a conductive plug at the end of a metal layer (i.e., the conductive plug closest to another test cell) and an adjacent metal layer in the second direction.

[0062] Once a failure is detected using the above test method, the following test method can be used to determine in which direction breakdown has occurred: a positive voltage can be applied to the sixth test pad PAD6 and the second test pad PAD2 can be grounded. At this time, the third diode D3 and the fourth diode D4 are forward-conducting, the first diode D1 and the second diode D2 are reverse-conducting, the test cells 20 in the first test array 21 are all at a positive voltage, and the test cells 20 in the second test array 22 are all at zero potential. At this time, there is no voltage difference between the test cells 20 in the first direction, and only breakdown in the second direction can be detected. If a significant leakage current is detected at this time, it indicates that leakage breakdown has occurred in the conductive plug in the second direction. If no leakage current is detected at this time, it indicates that leakage breakdown has occurred in the conductive plug in the first direction.

[0063] The semiconductor test structure of the present application, by setting a first test array 21 and a second test array 22, and adding diodes, can simultaneously detect the reliability problem of the dielectric layer between the conductive plugs corresponding to two adjacent parallel metal layers and the reliability of the dielectric layer between the conductive plug located at the end of the metal layer (that is, the conductive plug closest to another test unit) and the metal layer adjacent in the second direction. At the same time, since the semiconductor test structure of the present application adopts an array structure, the area of ​​the entire semiconductor test structure can be reduced by about half compared to the comb structure. The semiconductor test structure of the present application can not only detect the reliability problem of the dielectric layer, but also can detect the direction of the breakdown when there is a breakdown, which can improve the accuracy and efficiency of the test.

[0064] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor test structure, characterized in that: include: A first test circuit, a second test circuit, a third test circuit, and a fourth test circuit are sequentially connected end to end to form a ring closed circuit; A plurality of diodes are respectively connected between adjacent test circuits; a first test array and a second test array, each comprising a plurality of test units spaced apart along a first direction; each test unit comprising a plurality of spaced apart metal layers, a dielectric layer, and a conductive plug structure, wherein the dielectric layer is located between adjacent metal layers; and the conductive plug structure comprises a plurality of conductive plugs stacked from bottom to top, located within the dielectric layer, and electrically connecting adjacent metal layers. In the first test array, the test cells located in odd-numbered columns are connected to the second test circuit, and the test cells located in even-numbered columns are connected to the third test circuit; in the second test array, the test cells located in odd-numbered columns are connected to the fourth test circuit, and the test cells located in even-numbered columns are connected to the first test circuit; the first test array and the second test array are arranged at intervals along a second direction, and the second direction intersects the first direction; The plurality of diodes include a first diode, a second diode, a third diode and a fourth diode; The first test circuit includes a first test pad and a second test pad, the first test pad is connected to the second test pad; in the second test array, the test cells located in even-numbered columns are connected between the first test pad and the second test pad; The second test circuit includes a third test pad and a fourth test pad, the third test pad is connected to the fourth test pad; the anode of the first diode is connected to the first test pad, and the cathode of the first diode is connected to the third test pad; in the first test array, the test cells located in odd columns are connected between the third test pad and the fourth test pad; The third test circuit includes a fifth test pad and a sixth test pad, the fifth test pad is connected to the sixth test pad; the anode of the third diode is connected to the sixth test pad, and the cathode of the third diode is connected to the fourth test pad; in the first test array, the test cells located in even-numbered columns are connected between the fifth test pad and the sixth test pad; The fourth test circuit includes a seventh test pad and an eighth test pad, the seventh test pad is connected to the eighth test pad; the anode of the second diode is connected to the seventh test pad, and the cathode of the second diode is connected to the fifth test pad; the anode of the fourth diode is connected to the eighth test pad, and the cathode of the fourth diode is connected to the second test pad; in the second test array, the test cells located in odd columns are connected between the seventh test pad and the eighth test pad; The number of the test units in the first test array is the same as the number of the test units in the second test array, and are arranged in a one-to-one correspondence.

2. The semiconductor test structure according to claim 1, wherein: A spacing between the test cells in the first test array and the corresponding test cells in the second test array is smaller than a spacing between adjacent test cells in the first test array and a spacing between adjacent test cells in the second test array.

3. The semiconductor test structure according to claim 2, wherein: A spacing between the test cells in the first test array and the corresponding test cells in the second test array complies with minimum design rules.

4. The semiconductor test structure according to any one of claims 1 to 3, characterized in that: The testing unit comprises: a first metal layer extending along the second direction; a first conductive plug, located on an upper surface of the first metal layer; a second conductive plug, located on an upper surface of the first conductive plug; The second metal layer is located on the upper surface of the second conductive plug and extends along the second direction.

5. The semiconductor test structure according to claim 4, wherein: The dielectric layer is located between the first metal layer and the second metal layer.

6. The semiconductor test structure according to claim 4, wherein: The number of the first conductive plugs and the number of the second conductive plugs are both plural.

7. The semiconductor test structure according to claim 4, wherein: In the same test unit, the plurality of first conductive plugs and the plurality of second conductive plugs are arranged at intervals along the second direction.

8. The semiconductor test structure according to claim 4, wherein: The first metal layer and the second metal layer are arranged correspondingly up and down; in the same test unit, the spacing between adjacent first conductive plugs, the spacing between adjacent second conductive plugs, and the spacing between the first conductive plug and the second conductive plug located on the outermost side and the end face of the first metal layer and the end face of the second metal layer all comply with the minimum design rules.

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