An interference rejection correction circuit and a digital isolation circuit

Abstract

The application discloses an interference suppression correction circuit and a digital isolation circuit, wherein the interference suppression correction circuit is arranged at a receiving end of the digital isolation circuit, and comprises: a clamping circuit connected with an output end of an isolator; the clamping circuit comprises a pair of NMOS tubes and a pair of PMOS tubes, and has a first state that the pair of NMOS tubes is closed and the pair of PMOS tubes is opened when a transient pulse higher than a common mode level is included in an output signal of the isolator, a second state that the pair of NMOS tubes is opened and the pair of PMOS tubes is closed when a transient pulse lower than the common mode level is included in the output signal of the isolator, and a third state that the pair of NMOS tubes and the pair of PMOS tubes are both closed when the output signal of the isolator is the common mode level; a signal detection circuit connected with the clamping circuit; a signal correction circuit with an input end connected with the signal detection circuit and a demodulation circuit; and an input end of the demodulation circuit connected with the clamping circuit. The circuit in the application can effectively suppress common mode transient interference.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to an interference suppression correction circuit and a digital isolation circuit. Background Technology

[0002] Isolation refers to the electrical separation between various functional circuits in a system, preventing signal transmission through direct conductive paths. Instead, it physically separates high-voltage and low-voltage domains, minimizing mutual interference between circuits at different potentials. Currently, capacitive coupling is commonly used. A typical capacitive isolation drive circuit includes a transmitter (modulation module on the low-voltage side), a receiver (demodulation module on the high-voltage side), and an isolation capacitor. The transmitter modulates the transmitted signal into a signal that can pass through the isolation capacitor module, while the receiver demodulates the signal from the isolation capacitor module back into the transmitted signal. The isolation capacitor module connects the transmitter and receiver.

[0003] With the increasing intelligence of industrial and communication equipment, the market demand for digital isolators is growing daily, and the performance requirements are becoming increasingly stringent. One of the primary problems to be solved in designing and inventing digital isolators is common-mode transient interference. Currently, differential circuits are commonly used to improve the common-mode transient interference of digital isolators. This mainly relies on two resistors in the circuit to reduce common-mode interference, but its operating range is relatively small. When the common-mode voltage exceeds its operating range, it can still lead to communication failure.

[0004] Therefore, how to effectively suppress common-mode transient interference in digital isolation circuits has become an urgent problem to be solved. Summary of the Invention

[0005] Therefore, in order to solve the above-mentioned problems in the prior art, this application provides an interference suppression correction circuit and a digital isolation circuit.

[0006] According to a first aspect, the present invention provides an interference suppression correction circuit disposed at the receiving end of a digital isolation circuit, comprising:

[0007] A clamping circuit is connected to the output of the isolator. The clamping circuit includes a pair of NMOS transistors and a pair of PMOS transistors. The clamping circuit has a first state where the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on to reduce the transient pulse when the output signal of the isolator includes a transient pulse higher than the common-mode level; a second state where the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off to increase the transient pulse when the output signal of the isolator includes a transient pulse lower than the common-mode level; and a third state where both the pair of NMOS transistors and the pair of PMOS transistors are turned off when the output signal of the isolator is at the common-mode level.

[0008] The signal detection circuit is connected to the clamping circuit to output a first level when the clamping circuit is in the first state and the second state, and to output a second level when the clamping circuit is in the third state.

[0009] The signal correction circuit has its input connected to the signal detection circuit and the demodulation circuit to correct the demodulated signal based on the output level of the signal detection circuit; the input of the demodulation circuit is connected to the clamping circuit.

[0010] Furthermore, the signal detection circuit includes:

[0011] A first current mirror group connected to a pair of NMOS transistors is used to acquire and output the current at the pair of NMOS transistors;

[0012] A second current mirror group connected to a pair of PMOS transistors is used to collect and output the current at the pair of PMOS transistors;

[0013] A first inverter and a first buffer stage are respectively connected to the first current mirror group and the second current mirror group, and an OR gate with two input terminals respectively connected to the output terminals of the first inverter and the first buffer stage; the delay of the first buffer stage is the same as the delay of the first inverter.

[0014] Furthermore, a pair of NMOS transistors includes NMOS transistor M1 and NMOS transistor M3, and a pair of PMOS transistors includes PMOS transistor M2 and PMOS transistor M4;

[0015] The gates of both NMOS transistor M1 and PMOS transistor M2 are connected to the reference voltage. The drain of NMOS transistor M1 is connected to the high-level output terminal of the drive power supply, and its source is connected to the source of PMOS transistor M2 and connected to the non-inverting input terminal and the non-inverting output terminal. The drain of PMOS transistor M2 is grounded.

[0016] The gates of both NMOS transistor M3 and PMOS transistor M4 are connected to the reference voltage. The drain of NMOS transistor M3 is connected to the high-level output terminal of the drive power supply, and its source is connected to the source of PMOS transistor M4 and connected to the inverting input terminal and the inverting output terminal. The drain of PMOS transistor M4 is grounded.

[0017] Furthermore, the first current mirror group includes:

[0018] NMOS transistors M5, M7, M9, and M10 are used. The gate and source of NMOS transistor M5 are connected to the gate and source of NMOS transistor M1, respectively. The gate and source of NMOS transistor M7 are connected to the gate and source of NMOS transistor M3, respectively. The drain of PMOS transistor M9 is connected to the drain of both NMOS transistor M5 and NMOS transistor M7. The gate and source of PMOS transistor M10 are connected to the gate and source of PMOS transistor M9, respectively. The gate of PMOS transistor M9 is also connected to the drain of PMOS transistor M9. The sources of both PMOS transistors M9 and M10 are connected to the high-level output terminal of the drive power supply.

[0019] The second current mirror group includes:

[0020] PMOS transistors M6, M8, M11, and M12 are used. The gate and source of PMOS transistor M6 are connected to the gate and source of PMOS transistor M2, respectively. The gate and source of PMOS transistor M8 are connected to the gate and source of PMOS transistor M4, respectively. The drain of NMOS transistor M11 is connected to the drain of PMOS transistors M6 and M8, respectively. The gate and source of NMOS transistor M12 are connected to the gate and source of NMOS transistor M11, respectively. The gate of NMOS transistor M11 is connected to the drain of NMOS transistor M11. The source of NMOS transistors M11 and M12 are both grounded.

[0021] The input terminal of the first inverter is connected to the drain of the NMOS transistor M12 and then connected to the first current source.

[0022] The input terminal of the first buffer stage is connected to the drain of the PMOS transistor M10 and then connected to the second current source.

[0023] Furthermore, the interference suppression correction circuit also includes:

[0024] The detection signal processing circuit is connected between the signal detection circuit and the signal correction circuit. It is used to process the pulse signal output by the signal detection circuit and output the processed pulse signal to the signal correction circuit.

[0025] Furthermore, the detection signal processing circuit includes:

[0026] A buffer whose input is connected to the output of a signal detection circuit, and which has two outputs;

[0027] The first SR flip-flop has two input terminals connected to the two output terminals of the buffer, and a delay unit is provided between one of the output terminals of the buffer and the first SR flip-flop.

[0028] Furthermore, the signal correction circuit includes:

[0029] The second inverter has its input terminal connected to the output voltage signal of the demodulation circuit.

[0030] The second SR flip-flop has one of its two input terminals connected to the output terminal of the second inverter, and the other connected to the pulse signal output by the detection signal processing circuit;

[0031] The second and third buffer stages are respectively connected to the two outputs of the second SR flip-flop.

[0032] The third SR flip-flop has its two inputs connected to the outputs of the second and third buffer stages, respectively.

[0033] According to a second aspect, the present invention also provides a digital isolation circuit, the receiving end of which includes the interference suppression correction circuit of any embodiment of the first aspect described above.

[0034] The technical solution provided by this invention has the following advantages:

[0035] 1. The interference suppression correction circuit provided by the present invention, by setting a clamping circuit including a pair of NMOS transistors and a pair of PMOS transistors, and setting that when the output signal of the isolator includes a transient pulse higher than the common-mode level, the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on, thereby reducing the pulse amplitude of the transient pulse; when the output signal of the isolator includes a transient pulse lower than the common-mode level, the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off, thereby increasing the pulse amplitude of the transient pulse, and finally achieving effective suppression of common-mode transient interference.

[0036] Furthermore, by setting up a signal detection circuit connected to the clamping circuit, it detects whether a transient pulse has passed through the clamping circuit and converts the detection result into a pulse voltage signal, which is then transmitted to a signal correction circuit connected to the signal detection circuit and the output of the demodulation circuit. This allows the signal correction circuit to perform digital logic compensation on the problematic demodulated waveform (the demodulated waveform corresponding to the transient pulse), thereby further eliminating the impact of common-mode transient interference on the signal transmission of the digital isolation circuit.

[0037] 2. The interference suppression correction circuit provided by the present invention, by setting a detection signal processing circuit between the signal detection circuit and the signal correction circuit, processes the pulse signal output by the signal detection circuit into a signal that is more compatible with the demodulated signal output by the demodulation circuit (such as adjusting the pulse width or delaying), thereby further improving the signal correction effect of the interference suppression correction circuit. Attached Figure Description

[0038] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of an interference suppression correction circuit provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the structure of a clamping circuit and a signal detection circuit provided in an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of a detection signal processing circuit provided in an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of a signal correction circuit provided in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of a demodulation circuit provided in an embodiment of the present invention. Detailed Implementation

[0044] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] Example 1

[0047] Figure 1 This diagram illustrates the structure of an interference suppression correction circuit in one embodiment of this invention. Specifically, as shown... Figure 1 As shown, the interference suppression and correction circuit is located at the receiving end of the digital isolation circuit, that is, on the high-voltage side of the isolator (such as an isolation capacitor), and as... Figure 1As shown, the setting of this interference suppression and correction circuit does not affect the settings of other parts of the digital isolation circuit (such as the transmitting circuit, the receiving demodulation circuit, the receiving amplification circuit, etc.). Figure 1 As shown, the interference suppression and correction circuit includes: a clamping circuit, a signal detection circuit, and a signal correction circuit.

[0048] The clamping circuit is connected to the output of the isolator. This clamping circuit includes a pair of NMOS transistors and a pair of PMOS transistors. It has three states: a first state where, when the output signal of the isolator includes a transient pulse higher than the common-mode level, the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on to reduce the transient pulse; a second state where, when the output signal of the isolator includes a transient pulse lower than the common-mode level, the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off to increase the transient pulse; and a third state where, when the output signal of the isolator is at the common-mode level, both the pair of NMOS transistors and the pair of PMOS transistors are turned off.

[0049] Specifically, such as Figure 1 As shown, the signal after common-mode transient interference suppression by the clamping circuit is normally transmitted to the preamplifier and demodulation circuit for demodulation. That is, the clamping circuit has two outputs, and the other one is transmitted to the signal detection circuit.

[0050] The signal detection circuit is connected to the clamping circuit to output a first level when the clamping circuit is in the first state and the second state, and to output a second level when the clamping circuit is in the third state.

[0051] The input terminal of the signal correction circuit is connected to the signal detection circuit and the demodulation circuit to correct the signal demodulated by the demodulation circuit based on the output level of the signal detection circuit.

[0052] Since transient pulses are generally narrow, meaning the pulse duration corresponding to the first level is short, while the demodulated signal after passing through the preamplifier and demodulation circuits has a wider pulse, in order to achieve effective correction, such as Figure 1 As shown, in another embodiment of the present invention, the interference suppression correction circuit may further include a detection signal processing circuit, which is connected between the signal detection circuit and the signal correction circuit, for processing the pulse signal output by the signal detection circuit and outputting the processed pulse signal to the signal correction circuit.

[0053] Figure 2 A schematic diagram of the clamping circuit in one embodiment of this invention is shown. Figure 2As shown, the clamping circuit may include: NMOS transistor M1, PMOS transistor M2, NMOS transistor M3, and PMOS transistor M4 (where NMOS transistors M1 and M3 are the aforementioned pair of NMOS transistors, and PMOS transistors M2 and M4 are the aforementioned pair of PMOS transistors). The gates of NMOS transistors M1, M2, M3, and M4 are all connected to a reference voltage V. REF The drain of NMOS transistor M1 is connected to the high-level output terminal V of the drive power supply. DD The source of NMOS transistor M1 is connected to the source of PMOS transistor M2 and connected to the positive input V. IP Connect the positive phase output V OP The drain of PMOS transistor M2 is grounded; the drain of NMOS transistor M3 is connected to the high-level output terminal V of the drive power supply. DD The source of NMOS transistor M3 is connected to the source of PMOS transistor M4 and connected to the inverting input V. IN , Connect the inverting output V ON The drain of PMOS transistor M4 is grounded.

[0054] Specifically, set the reference voltage V REF If it is a common-mode level, then at the input signal (V IP and V IN When the normal constant common-mode level is reached, NMOS transistors M1, M2, M3, and M4 are all turned off, and the output signal (V) is... OP and V ON The input signal is the same as the input signal. When the input signal is a pulse higher than the common-mode level, NMOS transistors M1 and M3 are turned off, and PMOS transistors M2 and M4 are turned on, reducing the pulse amplitude. When the input signal is a pulse lower than the common-mode level, NMOS transistors M1 and M3 are turned on, and PMOS transistors M2 and M4 are turned off, increasing the pulse amplitude. Ultimately, effective suppression of common-mode transient interference is achieved regardless of whether a transient pulse higher or lower than the common-mode level occurs.

[0055] This embodiment also provides a circuit structure for a signal detection circuit in a specific implementation. Specifically, the signal detection circuit may include: a first current mirror group, a second current mirror group, a first inverter, a first buffer stage, and an OR gate. The first current mirror group is connected to a pair of NMOS transistors to acquire and output the current at the pair of NMOS transistors; the second current mirror group is connected to a pair of PMOS transistors to acquire and output the current at the pair of PMOS transistors; the first inverter and the first buffer stage are respectively connected to the first current mirror group and the second current mirror group; the two output terminals of the OR gate are respectively connected to the output terminals of the first inverter and the first buffer stage, and the output terminal of the OR gate is the output terminal of the signal detection circuit; and the delay of the first buffer stage is the same as the delay of the first inverter.

[0056] Figure 2 A schematic diagram of a specific structure of the above-mentioned signal detection circuit is shown.

[0057] like Figure 2 As shown, the first current mirror group includes: NMOS transistor M5, NMOS transistor M7, PMOS transistor M9, and PMOS transistor M10. The gate and source of NMOS transistor M5 are connected to the gate and source of NMOS transistor M1, respectively (the source of NMOS transistor M5 is connected to the source of NMOS transistor M1, i.e., connected to the output of the clamping circuit). Similarly, NMOS transistors M7, PMOS transistors M6, and PMOS transistor M8 are all connected to the output of the clamping circuit. Meanwhile, as... Figure 2 As shown, the output of the clamping circuit is also connected to the preamplifier U1; the output of the preamplifier U1 is connected to the demodulation circuit. The gate and source of NMOS transistor M7 are connected to the gate and source of NMOS transistor M3, respectively. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M5 and the drain of NMOS transistor M7. The gate and source of PMOS transistor M10 are connected to the gate and source of PMOS transistor M9, respectively, and the gate of PMOS transistor M9 is connected to the drain of PMOS transistor M9. The sources of PMOS transistors M9 and M10 are both connected to the high-level output terminal V of the drive power supply. DD Connected.

[0058] like Figure 2As shown, the second current mirror group includes: PMOS transistor M6, PMOS transistor M8, NMOS transistor M11, and NMOS transistor M12. The gate and source of PMOS transistor M6 are connected to the gate and source of PMOS transistor M2, respectively; the gate and source of PMOS transistor M8 are connected to the gate and source of PMOS transistor M4, respectively; the drain of NMOS transistor M11 is connected to the drains of both PMOS transistors M6 and M8; the gate and source of NMOS transistor M12 are connected to the gate and source of NMOS transistor M11, respectively; and the gate of NMOS transistor M11 is connected to its drain. The sources of both NMOS transistors M11 and M12 are grounded.

[0059] like Figure 2 As shown, the input terminal of the first inverter U2 is connected to the drain of the NMOS transistor M12 and to the first current source I1; the input terminal of the first buffer stage U3 is connected to the drain of the PMOS transistor M10 and to the second current source I2; the first inverter U2 and the first buffer stage U3 are respectively connected to the two input terminals of the OR gate U4.

[0060] Specifically, when a pulse higher than the common-mode level passes through the clamping circuit, PMOS transistors M2 and M4 turn on, and current flows through them. PMOS transistors M6 and M8 mirror this current and transmit it to NMOS transistor M11. NMOS transistor M11 then mirrors this current to NMOS transistor M12, making the input of the first inverter U2 low (the current of the first current source I1 is less than the current output of PMOS transistor M12) and the output high, thus making the output of OR gate U4 high (i.e., the first level). When a pulse lower than the common-mode level passes through the clamping circuit, NMOS transistors M1 and M3 turn on, and current flows through them. NMOS transistors M5 and M7 mirror this current and transmit it to PMOS transistor M9. OS transistor M9 then mirrors the current to PMOS transistor M10, making both the input and output of the first buffer stage U3 high (the current from the second current source I2 is smaller, less than the current output from PMOS transistor M10), which in turn makes the output of OR gate U4 high (i.e., the first level). When the signal level passing through the clamping circuit is the common-mode level and there is no pulse, NMOS transistors M1, M3, M2, and M4 are all turned off, so there is no current at PMOS transistors M10 and M12. Finally, the first inverter U2 and the first buffer stage U3 output low levels under the action of the first current source I1 and the second current source I2, respectively, which in turn makes OR gate U4 output low levels (i.e., the second level); thus, the detection of pulses is finally realized.

[0061] Figure 3A schematic diagram of the detection signal processing circuit in one embodiment of this invention is shown. Figure 3 As shown, the detection signal processing circuit may include: a buffer U5, a delay unit and a first SR flip-flop U6, wherein the input terminal of the buffer U5 is connected to the output terminal of the signal detection circuit and has two output terminals; the two input terminals of the first SR flip-flop U6 are respectively connected to the two output terminals of the buffer U5, and a delay unit is also provided between one of the output terminals of the buffer U5 and the first SR flip-flop U6.

[0062] Specifically, the pulse signal output from one output terminal of buffer U5 is delayed by the delay unit, resulting in a certain time error with the pulse signal at the other output terminal of buffer U5. Then, the pulse width modulation function is realized by forming the first SR flip-flop U6 based on two NOR gates.

[0063] Figure 4 A schematic diagram of the signal correction circuit in one embodiment of this invention is shown. Figure 4 As shown, the signal correction circuit may include: a second inverter U7, a second SR flip-flop U8, a second buffer stage U9, a third buffer stage U10, and a third SR flip-flop U11, wherein the input terminal of the second inverter U7 is connected to the output voltage signal DE of the demodulation circuit. MOD One of the two inputs of the second SR flip-flop U8 is connected to the output of the second inverter U7, and the other is connected to the pulse signal DE output by the detection signal processing circuit. TECT The input terminals of the second buffer stage U9 and the third buffer stage U10 are respectively connected to the two output terminals of the second SR flip-flop U8, and the two input terminals of the third SR flip-flop U11 are respectively connected to the output terminals of the second buffer stage U9 and the third buffer stage U10.

[0064] In another embodiment, such as Figure 4 As shown, in addition to the above structure, the signal correction circuit may also include a fourth buffer stage U12 and a fifth buffer stage U13. The input terminals of the two buffer stages are respectively connected to the two output terminals of the third SR flip-flop U11, and their output terminals are the output terminals of the signal correction circuit.

[0065] In summary, the interference suppression correction circuit in this embodiment, by setting up a clamping circuit including a pair of NMOS transistors and a pair of PMOS transistors, and by setting the pair of NMOS transistors to turn off and the pair of PMOS transistors to turn on when the output signal of the isolator includes a transient pulse higher than the common-mode level, achieves a reduction in the pulse amplitude of the transient pulse; and by setting the pair of NMOS transistors to turn on and the pair of PMOS transistors to turn off when the output signal of the isolator includes a transient pulse lower than the common-mode level, achieves an increase in the pulse amplitude of the transient pulse, and ultimately achieves effective suppression of common-mode transient interference.

[0066] Furthermore, by setting up a signal detection circuit connected to the clamping circuit, it detects whether a transient pulse has passed through the clamping circuit and converts the detection result into a pulse voltage signal, which is then transmitted to a signal correction circuit connected to the signal detection circuit and the output of the demodulation circuit. This allows the signal correction circuit to perform digital logic compensation on the problematic demodulated waveform (the demodulated waveform corresponding to the transient pulse), thereby further eliminating the impact of common-mode transient interference on the signal transmission of the digital isolation circuit.

[0067] Example 2

[0068] Figure 1 A schematic diagram of the structure of a digital isolation circuit in one embodiment of this invention is shown, as follows: Figure 1 As shown, it includes the interference suppression and correction circuit in Embodiment 1 above. It also includes a transmitting circuit, a receiving amplifier circuit, and a receiving demodulation circuit.

[0069] Figure 5 A schematic diagram of the receiver demodulation circuit in one embodiment of this invention is shown. Figure 5 As shown, the demodulation circuit may include: a PMOS transistor M13, whose gate is connected to the output terminal V of the first bias voltage. BIAS1 The source is connected to the high-level output terminal V of the drive power supply. DD The sources of PMOS transistors M14, M15, and M16 are all connected to the drain of PMOS transistor M13, and the gate of PMOS transistor M14 is connected to the inverting input V. IN The gate of PMOS transistor M15 is connected to the non-inverting input V. IP The gate of PMOS transistor M16 is connected to the common-mode voltage V. REF PMOS transistors M17 and M18 have their gates interconnected, and their sources are both connected to the high-level output terminal V of the drive power supply. DD PMOS transistors M19 and M20 have their gates interconnected and connected to the output terminal V of the second bias voltage. BIAS2 The source of PMOS transistor M19 is connected to the drain of PMOS transistor M17, and the source of PMOS transistor M20 is connected to the drain of PMOS transistor M18; the gates of NMOS transistors M21 and M22 are interconnected and connected to the output terminal V of the third bias voltage. BIAS3The drain of NMOS transistor M21 is connected to the drain of PMOS transistor M19 and the gate of PMOS transistor M17; the drain of NMOS transistor M22 is connected to the drain of PMOS transistor M20; the gates of NMOS transistors M23 and M24 are interconnected and connected to the output terminal V of the fourth bias voltage. BIAS4 Both sources are connected to the low-level output terminal V of the drive power supply. SS The drain of NMOS transistor M23 is connected to the source of NMOS transistor M21, the drain of PMOS transistor M14, and the drain of PMOS transistor M15. The drain of NMOS transistor M24 is connected to the source of NMOS transistor M22 and the drain of PMOS transistor M16. The gates of PMOS transistors M25 and M26 are interconnected and connected between the drains of PMOS transistor M20 and NMOS transistor M22. Their drains are interconnected and output signal DE. MOD The source of PMOS transistor M25 is connected to the high-level output terminal V of the drive power supply. DD The source of NMOS transistor M26 is connected to the low-level output terminal V of the drive power supply. SS .

[0070] The digital isolation circuit in this embodiment effectively suppresses common-mode transient interference through an interference suppression correction circuit, and has a high common-mode transient immunity capability.

[0071] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. An interference suppression and correction circuit, characterized in that, The receiving end of the digital isolation circuit includes: A clamping circuit is connected to the output of the isolator. The clamping circuit includes a pair of NMOS transistors and a pair of PMOS transistors. The clamping circuit has a first state where, when the output signal of the isolator includes a transient pulse higher than the common-mode level, the pair of NMOS transistors are turned off and the pair of PMOS transistors are turned on to reduce the transient pulse; a second state where, when the output signal of the isolator includes a transient pulse lower than the common-mode level, the pair of NMOS transistors are turned on and the pair of PMOS transistors are turned off to increase the transient pulse; and a third state where, when the output signal of the isolator is the common-mode level, both the pair of NMOS transistors and the pair of PMOS transistors are turned off. A signal detection circuit, connected to the clamping circuit, is used to output a first level when the clamping circuit is in the first state and the second state, and to output a second level when the clamping circuit is in the third state; A signal correction circuit, with its input terminal connected to the signal detection circuit and the demodulation circuit, corrects the demodulated signal based on the output level of the signal detection circuit; the input terminal of the demodulation circuit is connected to the clamping circuit. The signal detection circuit includes: A first current mirror group connected to the pair of NMOS transistors is used to acquire and output the current at the pair of NMOS transistors; A second current mirror group connected to the pair of PMOS transistors is used to acquire and output the current at the pair of PMOS transistors; A first inverter and a first buffer stage are respectively connected to the first current mirror group and the second current mirror group, and an OR gate with two input terminals respectively connected to the output terminals of the first inverter and the first buffer stage; the delay of the first buffer stage is the same as the delay of the first inverter; The pair of NMOS transistors includes NMOS transistor M1 and NMOS transistor M3, and the pair of PMOS transistors includes PMOS transistor M2 and PMOS transistor M4; The gates of both the NMOS transistor M1 and the PMOS transistor M2 are connected to the reference voltage. The drain of the NMOS transistor M1 is connected to the high-level output terminal of the driving power supply, and its source is connected to the source of the PMOS transistor M2 and connected to the non-inverting input terminal and the non-inverting output terminal. The drain of the PMOS transistor M2 is grounded. The gates of both the NMOS transistor M3 and the PMOS transistor M4 are connected to the reference voltage. The drain of the NMOS transistor M3 is connected to the high-level output terminal of the driving power supply, and its source is connected to the source of the PMOS transistor M4 and connected to the inverting input terminal and the inverting output terminal. The drain of the PMOS transistor M4 is grounded.

2. The interference suppression and correction circuit according to claim 1, characterized in that, The first current mirror group includes: NMOS transistors M5, M7, M9, and M10 are used. The gate and source of NMOS transistor M5 are connected to the gate and source of NMOS transistor M1, respectively. The gate and source of NMOS transistor M7 are connected to the gate and source of NMOS transistor M3, respectively. The drain of PMOS transistor M9 is connected to the drain of both NMOS transistor M5 and NMOS transistor M7. The gate and source of PMOS transistor M10 are connected to the gate and source of PMOS transistor M9, respectively. The gate of PMOS transistor M9 is also connected to the drain of PMOS transistor M9. The sources of both PMOS transistors M9 and M10 are connected to the high-level output terminal of the driving power supply. The second current mirror group includes: PMOS transistors M6, M8, M11, and M12 are used. The gate and source of PMOS transistor M6 are connected to the gate and source of PMOS transistor M2, respectively. The gate and source of PMOS transistor M8 are connected to the gate and source of PMOS transistor M4, respectively. The drain of NMOS transistor M11 is connected to the drain of both PMOS transistors M6 and M8. The gate and source of NMOS transistor M12 are connected to the gate and source of NMOS transistor M11, respectively. The gate of NMOS transistor M11 is connected to the drain of NMOS transistor M11. The sources of both NMOS transistors M11 and M12 are grounded. The input terminal of the first inverter is connected to the drain of the NMOS transistor M12 and is connected to the first current source; The input terminal of the first buffer stage is connected to the drain of the PMOS transistor M10 and is connected to the second current source.

3. The interference suppression and correction circuit according to claim 1 or 2, characterized in that, Also includes: A detection signal processing circuit is connected between the signal detection circuit and the signal correction circuit to process the pulse signal output by the signal detection circuit and output the processed pulse signal to the signal correction circuit.

4. The interference suppression and correction circuit according to claim 3, characterized in that, The detection signal processing circuit includes: A buffer, the input of which is connected to the output of the signal detection circuit, and which has two outputs; The first SR flip-flop has two input terminals connected to the two output terminals of the buffer, and a delay unit is provided between one of the output terminals of the buffer and the first SR flip-flop.

5. The interference suppression and correction circuit according to claim 4, characterized in that, The signal correction circuit includes: The second inverter has its input terminal connected to the output voltage signal of the demodulation circuit. The second SR flip-flop has one of its two input terminals connected to the output terminal of the second inverter, and the other connected to the pulse signal output by the detection signal processing circuit; The second and third buffer stages are respectively connected to the two outputs of the second SR flip-flop. The third SR flip-flop has its two inputs connected to the outputs of the second buffer stage and the third buffer stage, respectively.

6. A digital isolation circuit, characterized in that, Its receiving end includes the interference suppression correction circuit as described in any one of claims 1-5.

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