Mechanism for transferring light between layers of a multi-chip photonic assembly

Abstract

The present disclosure relates to mechanisms for transferring light between layers of a multi-chip photonic assembly. A multi-chip photonic assembly includes a first photonic integrated circuit and a second photonic integrated circuit having first and second waveguides, the first and second photonic integrated circuits vertically stacked such that a first vertical dimension of the first and second waveguides occupies different horizontal planes in the stack. At least one of the first and second waveguides includes a region having a second vertical dimension that is greater than the first vertical dimension and horizontally overlaps and / or vertically contacts the other waveguide. Light changes mode vertically through one of the waveguides from the first vertical dimension to the other vertical dimension such that the light moves from one waveguide to the other waveguide.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 247,726, filed September 23, 2021, and U.S. Provisional Patent Application No. 63 / 310,397, filed February 15, 2022, pursuant to Section 119(e) of Title 35 of the United States Code, the contents of each of which are incorporated herein by reference in their entirety. Technical Field

[0003] The described implementation scheme relates generally to photonic integrated circuits. More specifically, this implementation scheme relates to a mechanism for transmitting light between photonic integrated circuits. Background Technology

[0004] Microelectronics involves the design and fabrication (or microfabrication) of very small electronic components. An example of such devices (i.e., digital integrated circuits) can be made of semiconductor materials and can include components such as transistors, capacitors, inductors, resistors, diodes, insulators, and conductors. Wiring techniques, such as wire bonding, are commonly used in digital integrated circuits and other microelectronics due to the typically small size of components, leads, and pads. Various techniques can be used to connect multiple digital integrated circuits to build complex systems.

[0005] Some typical integrated circuits can be multilayer circuits, where electrical signals are routed through traces on opposite sides of a single substrate or traces defined on various stacked substrates. Vias can extend through the substrate to allow electrical signals to travel from one layer or one substrate or one side to another layer or another substrate or another side. Typically, such vias are formed with copper filler.

[0006] Photonic integrated circuits (or integrated optical circuits) are devices that integrate certain photonic functions, thereby typically replacing electrical signals with photonic (e.g., light-based) signals. In some ways, photonic integrated circuits resemble digital integrated circuits. The main difference between photonic and digital integrated circuits is that photonic integrated circuits utilize light instead of electricity as the signal medium, which in turn requires the use of optical components instead of conventional circuits. While electrical signals can be propagated across layers via vias in typical integrated circuits, there are few such options for optical signals in photonic integrated circuits. Therefore, optical signals are typically routed within a single layer or plane of such circuits, thus constraining design options. Summary of the Invention

[0007] This disclosure relates to a multi-chip photonic component. A first photonic integrated circuit and a second photonic integrated circuit having a first waveguide and a second waveguide are vertically stacked such that a first vertical dimension of the first waveguide and the second waveguide occupies a different horizontal plane in the stack. At least one of the first waveguide and the second waveguide includes a region having a second vertical dimension that is larger than the first vertical dimension and horizontally overlaps with and / or vertically contacts another waveguide. Light moves vertically from the first vertical dimension to the other vertical dimension through one of these waveguides, changing its mode vertically, such that light moves from one waveguide to the other.

[0008] In various embodiments, the multi-chip photonic component includes: a first photonic integrated circuit including a first waveguide having a first region occupying a first horizontal plane and having a first vertical dimension, and a second region having a second vertical dimension larger than the first vertical dimension, the second region including a first adiabatic cone. The multi-chip photonic component further includes: a second photonic integrated circuit including a second waveguide vertically stacked on top of the first photonic integrated circuit, the second waveguide having a third region occupying a second horizontal plane and having a third vertical dimension, and a fourth region having a fourth vertical dimension larger than the third vertical dimension, the fourth region including a second adiabatic cone. The second region is positioned in the second horizontal plane. The second region and the fourth region alter the mode of light traveling between the first photonic integrated circuit and the second photonic integrated circuit.

[0009] In some examples, the second region overlaps with the fourth region in the first and second horizontal planes. In various embodiments of such examples, the multi-chip photonic assembly further includes an anti-reflective coating positioned between the second and fourth regions. In some embodiments of such examples, the first adiabatic cone tapers horizontally from a first side of the second region facing the fourth region toward a second side of the second region opposite to the first side. In several embodiments of such examples, the first adiabatic cone tapers vertically from a first side of the second region facing the fourth region toward a second side of the second region opposite to the first side. In some embodiments of such examples, the second and fourth regions cooperate to define a gap between the second and fourth regions, and the gap is filled with at least one of air or an optically transparent bottom filler.

[0010] In many examples, the second region includes a first angled facet, and the fourth region includes a second angled facet facing the first angled facet in the first horizontal plane and the second horizontal plane.

[0011] In some embodiments, a multi-chip photonic component includes: a first photonic integrated circuit including a first waveguide having a first region occupying a first horizontal plane and having a first vertical dimension, and a second region having a second vertical dimension larger than the first vertical dimension, the second region having a first adiabatic cone. The multi-chip photonic component further includes: a second photonic integrated circuit including a second waveguide and vertically stacked on top of the first photonic integrated circuit, the second waveguide having a third region occupying a second horizontal plane and having a third vertical dimension, and a fourth region having a fourth vertical dimension larger than the third vertical dimension, the fourth region including a second adiabatic cone. The second region is in vertical contact with the second waveguide. The second region and the fourth region alter the mode of light traveling between the first photonic integrated circuit and the second photonic integrated circuit.

[0012] In various examples, the second region is vertically contacted with the second waveguide via an optically transparent adhesive. In some examples, the multi-chip photonic assembly further includes an adiabatic transfer region in which the second adiabatic cone vertically overlaps with the first adiabatic cone. In various specific implementations of such examples, the light travels between the first and second waveguides where the second region is vertically contacted with the second waveguide.

[0013] In some examples, the multi-chip photonic component further includes a capping material positioned between the first waveguide and the second waveguide. In many examples, the first and second adiabatic cones taper relative to each other. In some examples, the second region is adjacent to the fourth region and positioned relative to the third region.

[0014] In several embodiments, the multi-chip photonic component includes: a first photonic integrated circuit including a first waveguide having a first region occupying a first horizontal plane and having a first vertical dimension, and a second region having a second vertical dimension larger than the first vertical dimension. The multi-chip photonic component further includes: a second photonic integrated circuit including a second waveguide occupying a second horizontal plane, vertically stacked on top of the first photonic integrated circuit. The second region is positioned within the second horizontal plane. The second region alters the mode of light traveling between the first and second photonic integrated circuits.

[0015] In various examples, the second region transmits the light traveling between the first photonic integrated circuit and the second photonic integrated circuit using interference between optical modes. In some examples, the second region has a uniform horizontal dimension from a first side of the second region facing the second waveguide to a second side of the second region opposite to the first side. In many examples, the second vertical dimension is uniform from the first side of the second region facing the second waveguide to the second side of the second region opposite to the first side. In various examples, the first waveguide horizontally defines a gap between the second region and the second waveguide. In some examples, the second waveguide has a third vertical dimension smaller than the second vertical dimension.

[0016] In various examples, a multi-chip photonic component includes: a first photonic integrated circuit having a first waveguide, the first waveguide having a first region occupying a first horizontal plane and having a first vertical dimension, and a second region having a second vertical dimension larger than the first vertical dimension. The second region includes a first waveguide material and a second waveguide material, the second waveguide material covering the first waveguide material and having a lower refractive index compared to the first waveguide material. The multi-chip photonic component further includes: a second photonic integrated circuit having a second waveguide and vertically stacked on top of the first photonic integrated circuit. The second waveguide has a third region occupying a second horizontal plane and having a third vertical dimension, and a fourth region having a fourth vertical dimension larger than the third vertical dimension. The fourth region includes a third waveguide material and a fourth waveguide material, the fourth waveguide material covering the third first waveguide material and having a lower refractive index compared to the third waveguide material. The second region is positioned in the second horizontal plane, and the second region and the fourth region alter the mode of light traveling between the first photonic integrated circuit and the second photonic integrated circuit.

[0017] In some examples, the first region includes a first segment of the first waveguide material, the second region includes a second segment of the first waveguide material, and the width of the second segment is thermally tapered in the second region. Additionally or alternatively, the third region includes a third segment of the third waveguide material, the second region includes a fourth segment of the fourth waveguide material, and the width of the fourth segment is thermally tapered in the fourth region. In some cases, the second segment terminates before the distal end of the second region. Additionally or alternatively, the fourth segment terminates before the distal end of the fourth region.

[0018] In many examples, the first waveguide material and the third waveguide material are the same material. Additionally or alternatively, the second waveguide material and the fourth waveguide material are the same material. In some examples, the first photonic integrated circuit defines a cavity, and the fourth region extends at least partially into the cavity of the first photonic device. Additionally or alternatively, the second photonic integrated circuit defines a cavity, and the second region extends at least partially into the cavity of the second photonic device. Attached Figure Description

[0019] This disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein similar reference numerals denote similar structural elements.

[0020] Figure 1 A top view of a first exemplary multi-chip photonic component is depicted.

[0021] Figure 2A A top view of a second exemplary multi-chip photonic component is depicted.

[0022] Figure 2B Depicting Figure 2A A side view of a multi-chip photonic component.

[0023] Figure 3 A side view of a third exemplary multi-chip photonic component is depicted.

[0024] Figure 4A A side view of a fourth exemplary multi-chip photonic component is depicted.

[0025] Figure 4B Depicting from Figure 4A A top view of the first photonic integrated circuit with the multi-chip photonic component removed.

[0026] Figure 4C Depicting from Figure 4A A bottom view of the second photonic integrated circuit with the multi-chip photonic component removed, where the substrate has been removed for clarity.

[0027] Figure 4D Depicting Figure 4A A side view of an alternative implementation of a multi-chip photonic component.

[0028] Figure 5A A side view of a fifth exemplary multi-chip photonic component is depicted.

[0029] Figure 5B Depicting Figure 5A A top view of the multi-chip photonic assembly, in which the substrate and buried oxide of the second integrated circuit have been removed for clarity.

[0030] Figure 6A A side view of a sixth exemplary multi-chip photonic component is depicted.

[0031] Figure 6B Depicting from Figure 6A A top view of the first photonic integrated circuit with the multi-chip photonic component removed.

[0032] Figure 6C Depicting from Figure 6A A bottom view of the second photonic integrated circuit with the multi-chip photonic component removed, where the substrate has been removed for clarity.

[0033] Figure 7A An exemplary wafer for use in photonic integrated circuits is depicted. The wafer can be used to fabricate... Figures 1 to 6C and Figures 8A to 8C One or more of the first photonic integrated circuit and / or the second photonic integrated circuit.

[0034] Figure 7B Depicting Figure 7A An exemplary wafer after an epitaxial growth operation has been performed.

[0035] Figure 7C Depicting Figure 7B The wafer after the first etching operation.

[0036] Figure 7D Depicting Figure 7C The wafer after the second etching operation.

[0037] Figure 7E Depicting Figure 7D The wafer after performing a deep cavity etching operation.

[0038] Figure 8A A side view of a seventh exemplary multi-chip photonic component is depicted.

[0039] Figure 8B Depicting Figure 8A A top view of the multi-chip photonic assembly, with the second photonic chip removed for clarity.

[0040] Figure 8C Depicting Figure 8A A bottom view of the multi-chip photonic assembly, with the first photonic chip removed for clarity. Detailed Implementation

[0041] Reference will now be made specifically to the representative embodiments shown in the accompanying drawings. It should be understood that the following description is not intended to limit the embodiments to a single preferred embodiment. Rather, it is intended to cover alternative forms, modifications, and equivalents that may be included within the substance and scope of the embodiments defined by the appended claims.

[0042] The following description includes sample systems, methods, and apparatuses embodying various elements of this disclosure. However, it should be understood that the described disclosure may be implemented in many forms other than those described herein.

[0043] The ability to flexibly connect multiple digital integrated circuit chips together is crucial for building complex systems in microelectronics. Similar flexibility for photonic integrated circuits, such as flip-chip or side-by-side arrangements, is also valuable. For example, separating the functionality of photonic integrated circuits between two or more chips in a flip-chip configuration can result in a much smaller overall footprint, which can be particularly important for mobile or wearable applications where space is extremely limited. This also increases modularity, giving photonic system designers the flexibility to mix and match different components, which can be useful for applications like rapid prototyping or optimal wavelength combining during production. Separation also opens up new manufacturing possibilities because different chips can operate with separate, potentially incompatible process flows.

[0044] For example, a photonic integrated circuit may include a Mach-Zehnder interferometer, an echelle grating, and an optical phased array passive delay line network. The optical phased array passive delay line network can occupy a relatively large area of ​​the photonic integrated circuit. By dividing the photonic integrated circuit into a first photonic integrated circuit with a Mach-Zehnder interferometer and an echelle grating, and a second photonic integrated circuit with an optical phased array passive delay line network that can be coupled to the first photonic circuit in a flip-chip or other arrangement, a much smaller overall footprint can be achieved.

[0045] By another example, a photonic integrated circuit may include a first wafer having a first crystal orientation and a second wafer having a second crystal orientation. When the two orientations are different, the two wafers are separated from each other. However, light can be transmitted from one wafer (or a component on that wafer) to the other wafer (or the second component on that wafer) as part of the operation of the photonic integrated circuit. The embodiments described herein facilitate the use of these wafers in the same multi-chip photonic assembly by simplifying light transmission between wafers with different crystal orientations, while saving space in the overall assembly.

[0046] In yet another example, a photonic integrated circuit may include a laser and a grating that require precise matching of their optical wavelengths. Separating the laser and grating onto different photonic integrated circuits allows for optimal wavelength combining of the laser and grating during manufacturing, enabling the photonic integrated circuit including the laser to be used with photonic integrated circuits including gratings that are appropriately matched to the laser.

[0047] In yet another example, dividing the components of a photonic integrated circuit into multiple photonic integrated circuits can increase yield. This may be due to the fact that components that do not meet one or more sets of requirements or criteria may result in only the corresponding photonic integrated circuit being included, rather than a photonic integrated circuit that includes all of those components.

[0048] One of the main challenges of multi-chip architectures in photonics is the difficulty in transferring light from one chip to another without significant light loss. This disclosure addresses this problem by providing a mechanism to transfer light between photonic chips, such as those arranged in a flip-chip configuration, without inducing large optical losses.

[0049] The following disclosure relates to a multi-chip photonic component. A first photonic integrated circuit and a second photonic integrated circuit having a first waveguide and a second waveguide can be vertically stacked such that a first portion of the first waveguide and the second waveguide (having a first vertical dimension) occupies a different horizontal plane in the stack. At least one of the first waveguide and the second waveguide includes a region having a second vertical dimension, which is larger than the first vertical dimension; the second vertical dimension horizontally overlaps with and / or vertically contacts another waveguide. Light moves vertically from the first vertical dimension to the other vertical dimension through one of these waveguides, changing its mode vertically, such that the light moves from one waveguide to the other.

[0050] The following is for reference Figures 1 to 8C These embodiments and other embodiments will be discussed herein. However, those skilled in the art will readily understand that the detailed descriptions given herein with respect to the accompanying drawings are for illustrative purposes only and should not be construed as limiting.

[0051] Figure 1 A top view of a first exemplary multi-chip photonic assembly 100 is depicted. The multi-chip photonic assembly 100 includes a first photonic integrated circuit 110 coupled to a second photonic integrated circuit 120 in a side-by-side arrangement. When the first photonic integrated circuit 110 and the second photonic integrated circuit 120 are coupled in side-by-side, the total area occupied by the multi-chip photonic assembly 100 is the same as the total area occupied by the first photonic integrated circuit 110 plus the total area occupied by the second photonic integrated circuit 120.

[0052] Figure 2A A top view of a second exemplary multi-chip photonic component 200 is depicted, while Figure 2B Depicting Figure 2A Side view of the multi-chip photonic component 200. About Figure 2A and Figure 2BThe multi-chip photonic component 200 includes a first photonic integrated circuit 210, which is coupled to a second photonic integrated circuit 220 in a flip-chip arrangement. Typically, and for example for comparative purposes, the first photonic integrated circuit 210 and... Figure 1 The first photonic integrated circuit 110 shown has the same area, and the second photonic integrated circuit 220 is the same as... Figure 1 The second photonic integrated circuit 120 has the same area. When the first photonic integrated circuit 210 and the second photonic integrated circuit 220 are stacked vertically (e.g., one on top of the other), the total area occupied by the multi-chip photonic assembly 200 is significantly smaller than that of the first photonic integrated circuit 210 and the second photonic integrated circuit 220. Figure 1 The overall area occupied by the multi-chip photonic component 100. However, in order for the first photonic integrated circuit 210 and the second photonic integrated circuit 220 to operate together, light must be transmitted between the first photonic integrated circuit and the second photonic integrated circuit.

[0053] Figure 3 A side view of a third exemplary multi-chip photonic assembly 300 is depicted. The multi-chip photonic assembly 300 may include a first photonic integrated circuit 310 (or a bottom chip) coupled to a second photonic integrated circuit 320 (or a top chip), arranged in a flip-chip configuration (similar to...). Figures 2A to 2B The arrangement shown (relative to vertical axis 361) is vertically stacked. The first photonic integrated circuit 310 may include a first substrate 311 (such as silicon), a first buried oxide layer 312, and a first waveguide 313. Similarly, the second photonic integrated circuit 320 may include a second substrate 321 (such as silicon), a second buried oxide layer 322, and a second waveguide 323. Generally, the term "buried oxide layer" as used herein is intended to cover any buried low-refractive-index optical cladding layer made of any suitable material having a lower refractive index than the waveguide material (or material), with silicon oxide being an only example of such a buried oxide layer. Similarly, the waveguide discussed herein may be made of silicon, combinations of materials such as high-refractive-index materials having lower-refractive-index cladding layers (e.g., Si / / SiO2, Si / SiN, etc.). In other words, the first photonic integrated circuit and / or the second photonic integrated circuit may optionally include one or more additional low-refractive-index optical cladding layers to provide optical constraint on the waveguide in one or more lateral directions.

[0054] The first photonic integrated circuit 310 defines a cavity 351 such that the first waveguide 313 and the second waveguide 323 (both of which may have uniform vertical dimensions) can occupy the same horizontal plane (relative to the horizontal axis 360). Light 350 can be transmitted between the first waveguide 313 and the second waveguide 323, and thus light 350 is transmitted between the first photonic integrated circuit 310 and the second photonic integrated circuit 320.

[0055] Direct optical coupling between the first waveguide 313 and the second waveguide 323 in the same horizontal plane can be very efficient optically. For example, the optical loss can be less than 0.5 dB.

[0056] However, when the first waveguide 313 and the second waveguide 323 are in the same horizontal plane, the second photonic integrated circuit 320 protrudes into the cavity 351 defined in the first photonic integrated circuit 310 (or vice versa) to align the waveguides 313 and 323. While this does transmit optical signals between adjacent or combined photonic integrated circuits, it does not change the layer or plane through which the optical signals propagate. Furthermore, when combined, the occupied area of ​​the first waveguide 313 and the second waveguide 323 is not reduced because they are inevitably in the same horizontal plane. Since the optical signals are not vertical (e.g., Figure 3 The vertical axis 361 propagates upwards or downwards, so the overall area occupied by the component may not decrease.

[0057] To achieve a reduced footprint, one or more mechanisms can be used to couple light between waveguides in two different horizontal planes of the component. Such mechanisms can operate as "photonic vias".

[0058] A specific implementation of the "thermally adiabatic mating coupler" uses an adiabatic cone to gradually extend the optical mode of a waveguide on a first chip in the vertical direction. Once the mode is extended, light can propagate across a small air gap (or filler gap, etc.) to a target waveguide on another chip with the same mode distribution. The thermally adiabatic mating coupler exhibits very low optical loss (e.g., very little light is scattered or dissipated when coupled between waveguides), good tolerance to misalignment between chips, and broadband wavelength performance (e.g., a relatively large set of optical wavelengths can be coupled between waveguides). Furthermore, some embodiments may use an anti-reflective coating to coat the edges of any one or both waveguides to reduce back reflection. Similarly, one or both waveguides may have angled facets to reduce back reflection.

[0059] As an example of the aforementioned, Figure 4A This is a side view of a fourth exemplary multi-chip photonic component 400. The multi-chip photonic component 400 can implement photonic vias using an adiabatic mating coupler mechanism.

[0060] The multi-chip photonic assembly 400 may include a first photonic integrated circuit 410 (or a bottom chip) coupled to a second photonic integrated circuit 420 (or a top chip), which are stacked vertically in a flip-chip arrangement (relative to a vertical axis 460). The first photonic integrated circuit 410 may include a first substrate 411 (such as silicon), a first buried oxide layer 412, and a first waveguide 413 (such as a silicon waveguide). Similarly, the second photonic integrated circuit 420 may include a second substrate 421 (such as silicon), a second buried oxide layer 422, and a second waveguide 423 (such as a silicon waveguide). The first and / or second photonic integrated circuits may optionally include additional low-refractive-index capping layers (not shown) to provide optical confinement, as described below. Figure 4D As depicted. Light 450 (which may include one or more wavelengths supporting a narrowband or broadband embodiment) may be transmitted between the first waveguide 413 and the second waveguide 423, and thus between the first photonic integrated circuit 410 and the second photonic integrated circuit 420.

[0061] The first waveguide 413 may have a first vertical dimension corresponding to a first region, which is smaller in height than the second region 414, and the second region has a second vertical dimension larger than the first dimension. Similarly, the second waveguide 423 may have a third vertical dimension corresponding to a third region, which is smaller in height than the fourth region 424, and the fourth region has a fourth vertical dimension larger than the third dimension. The first region of the first waveguide 413 may occupy a different horizontal plane (relative to the horizontal axis 461) from the third region of the second waveguide 423. However, the second region 414 of the first waveguide 413 may occupy the same and / or similar horizontal plane as the fourth region 424 of the second waveguide 423, such that the second region 414 and the fourth region 424 have vertical facets that face each other horizontally across the coupling gap 453.

[0062] As light 450 travels from the first side of the first waveguide 413 corresponding to the first region (i.e., along the horizontal axis 461) to the second side of the first waveguide 413 corresponding to the second region 414, the mode of light 450 can change, thereby expanding corresponding to the larger vertical dimension of the second region 414. Then, light can travel across the coupling gap 453 from the vertical facet of the second region 414 to the vertical facet of the fourth region 424. From there, light 450 can travel from the first side of the second waveguide 423 corresponding to the fourth region 424 to the second side of the second waveguide 423 corresponding to the third region (i.e., along the horizontal axis 461). As light 450 travels in this way, the mode of light 450 can change, thereby contracting as the larger vertical dimension of the fourth region 424 changes to the smaller vertical dimension of the third region of the second waveguide 423. In this way, the mode of light 450 can change from the first horizontal plane of the first region of the first waveguide 413 to the second horizontal plane of the third region of the second waveguide 423. In other words, light 450 travels in the vertical stacking direction (i.e., vertical axis 460) by means of the second region 414 and the fourth region 424.

[0063] Figure 4B Depicting from Figure 4A A top view of the first photonic integrated circuit 410 removed from the multi-chip photonic assembly 400. As shown, the first waveguide 413 may have a width 454, and the second region 414 may form an adiabatic cone. The adiabatic cone may taper from a second side of the first waveguide 413 corresponding to the second region 414 toward a first side of the first waveguide 413 corresponding to the first region. In other words, the width of the second region 414 decreases along the horizontal axis 461 from the second side of the first waveguide 413 toward the first side of the first waveguide 413 until the second region 414 terminates. This adiabatic cone can function to extend the mode of the light 450. In this way, the second region 414 may be one of the adiabatic mating couplers mentioned above.

[0064] Area 414 in Figure 4A and 4B The diagram shows a region 414 with a uniform vertical dimension. However, it should be understood that this is an example. In various specific embodiments, the vertical dimension of the second region 414 may be varied from the vertical dimension of the first region of the first waveguide 413 by tilting, bending, stepping, or otherwise altering to the maximum vertical dimension of the second region 414. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0065] Figure 4C Depicting from Figure 4AA bottom view of the second photonic integrated circuit 420 removed from the multi-chip photonic assembly 400, wherein the substrate 421 has been removed for clarity. As shown, the fourth region 424 can be formed into an adiabatic cone. The adiabatic cone tapers from the second side of the second waveguide 423 corresponding to the fourth region 424 toward the first side of the second waveguide 423 corresponding to the third region. In other words, the width of the fourth region 424 decreases along the horizontal axis 461 from the second side of the second waveguide 423 toward the first side of the second waveguide 413 until the fourth region 424 terminates. This adiabatic cone can function to contract the pattern of light 450. In this way, the fourth region 424 can be another adiabatic mating coupler in the aforementioned adiabatic mating coupler. The coupling between photonic circuits can be bidirectional, so that light introduced into the second waveguide 423 is transmitted to the first waveguide 413. In this case, the adiabatic cone formed by the fourth region 424 will expand the mode of light, and the adiabatic cone formed by the second region 414 will contract the mode of light 450.

[0066] Area 424 Figure 4A and Figure 4C The diagram shows a region 424 with a uniform vertical dimension. However, it should be understood that this is an example. In various specific embodiments, the vertical dimension of the fourth region 424 may be varied from the vertical dimension of the third region of the second waveguide 423 by tilting, bending, stepping, or otherwise altering to the maximum vertical dimension of the fourth region 424. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0067] Refer again Figure 4A A first region of the first waveguide 413 can be separated from the second waveguide 423 by a vertical gap 452. This vertical gap 452 may provide space for one or more layers of overlay material (such as oxides as mentioned above), air, one or more coupling structures (not shown) coupling the first photonic integrated circuit 410 to the second photonic integrated circuit 420 (such as one or more adhesives; epoxy resin or other bottom fillers; pillar and bump configurations in which one or more pillars disposed on one of the first photonic integrated circuit 410 and the second photonic integrated circuit 420 (such as pillars formed using one or more of the first waveguide 413 and / or the second waveguide 423) are connected to one or more gold or other solder bumps located on the other of the first photonic integrated circuit 410 and the second photonic integrated circuit 420, the solder bumps flowing back to them to bond to the pillars, etc.), one or more anti-reflective coatings, etc. The vertical gap 452 also prevents the first region of the first waveguide 413 from contacting the second waveguide 423. Although the photonic integrated circuits 410 and 420 are in... Figure 4AThe diagram shows a flip-chip arrangement for coupling, but this does not require electrical connections between the photonic integrated circuits. Electrical connections can be made between the photonic integrated circuits if needed (e.g., to allow electrical signal transmission between them).

[0068] The second vertical dimension of the second region 414 and the fourth vertical dimension of the fourth region 424 can have a minimum height. This can be expressed by the following formula: h min =2h strip + Vertical gap, where h min This indicates the minimum height of region 414 or region 424, 2h. strip The vertical gap 452 represents twice the height of the other portions of the corresponding waveguides (i.e., the first region of the first waveguide 413 for the second region 414 and the third region of the second waveguide 423 for the fourth region 424), and "vertical gap" refers to the gap 452. For example, the 8-micrometer height of the second vertical dimension of the second region 414 and the fourth vertical dimension of the fourth region 424 can leave a 3-micrometer height for the first region of the first waveguide 413 and the third region of the second waveguide 423 and a 2-micrometer height for the vertical gap 452 (this can leave space for oxides and / or other covering layers and / or other materials).

[0069] To accommodate the fourth vertical dimension of the fourth region 424, the first photonic integrated circuit 410 defines a cavity 456 (“first cavity”). The cavity 456 extends at least partially through the first buried oxide layer 412 of the first photonic integrated circuit 410. Figure 4A In the variant shown, cavity 456 extends completely through the first buried oxide layer 412 and at least partially through the first substrate 411. When as... Figure 4A When the first photonic integrated circuit 410 and the second photonic integrated circuit 420 are stacked vertically, the fourth region 424 of the second waveguide 423 extends at least partially into the cavity 456 of the first photonic integrated circuit 410. This allows a portion of the fourth region 424 of the second waveguide 423 to occupy the same horizontal plane (relative to the horizontal axis 461) as a portion of the first region of the first waveguide 413.

[0070] Similarly, to accommodate the second vertical dimension of the second region 414, the second photonic integrated circuit 420 defines a cavity 455 (“second cavity”). The cavity 455 extends at least partially through the second buried oxide layer 422 of the second photonic integrated circuit 420. Figure 4A In the variant shown, cavity 455 extends completely through the second buried oxide layer 422 and at least partially through the second substrate 421. When as... Figure 4AWhen the first photonic integrated circuit 410 and the second photonic integrated circuit 420 are stacked vertically, the second region 414 of the first waveguide 413 extends at least partially into the cavity 455 of the second photonic integrated circuit 420. This allows a portion of the second region 414 of the first waveguide 413 to occupy the same horizontal plane (relative to the horizontal axis 461) as a portion of the third region of the second waveguide 423.

[0071] The first photonic integrated circuit 410 and the second photonic integrated circuit 420 can each be fabricated by epitaxial growth and subsequent etching. For example, the wafer may have a silicon substrate covered by a buried oxide layer, which itself is covered by a silicon layer (e.g., a 3-micron silicon layer). Silicon can be added by epitaxial growth prior to subsequent etching. Etching can be used to define waveguides (e.g., first waveguide 413 and second waveguide 423) and cavities (e.g., cavities 455 and 456) of the multi-chip photonic assembly 400, as described below. Figures 7A to 7E Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0072] The embodiment of the thermally abutment coupler illustrated and described above can use an optical mode that thermally transmits vertically extended and / or contracted light 450. This embodiment can provide large cross-sections of the first waveguide 413 and the second waveguide 423 at the coupling gap 453, which can provide good tolerance for misalignment.

[0073] Although the tolerances for misalignment have been discussed above, it should be understood that this is an example. Misalignment can result in greater loss of light 450 transmission, thereby causing parasitic light and / or other light 450 modes that can be sources of noise. However, in some specific implementations, some such misalignments may be acceptable and / or otherwise considered. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0074] The embodiment of the thermally adiabatic coupler illustrated and described above can have low coupling losses (e.g., at least less than 1 dB). The thermally adiabatic cone allows for very wideband performance. The large first waveguide 413 and second waveguide 423 provide good tolerance for misalignment. However, the cone can be quite long on each side of the coupling gap 453, such as approximately 700 micrometers or more. Furthermore, the novel silicon growth and etching can lead to challenging fabrication.

[0075] Figure 4D Depicting Figure 4AA side view of an alternative embodiment of the multi-chip photonic assembly 400. In this alternative embodiment, one or more first capping material layers 465 (e.g., a material with a lower refractive index compared to the first waveguide 413, such as an oxide) are positioned on the first waveguide 413 facing the second waveguide 423, and one or more second capping material layers 462 (e.g., a material with a lower refractive index compared to the first waveguide 413, such as an oxide) are positioned on the second waveguide 423 facing the first waveguide 413. These capping layers can provide optical confinement for the first waveguide 413 and the second waveguide 423. The space between the first capping material layer 465 and the second capping material layer 462 can be filled by a bottom filler 463, such as an optically clear epoxy resin. The bottom filler 463 can mechanically couple the first photonic integrated circuit 410 and the second photonic integrated circuit 420.

[0076] Additionally or alternatively, the second region 414 and the fourth region 424 have laterally angled facets facing each other (e.g., when the second region and the fourth region extend from the first side surface to the other side surface or as...). Figure 4D (As shown, the entry and exit from the page is not perpendicular), and one or more anti-reflective coatings 464 are provided on those angled facets. It should be understood that vertical angled facets can replace lateral angled facets (e.g., such facets are not perpendicular because they extend from the base to the top surface, or from...). Figure 4D (The top of the page extends to the bottom) is used.

[0077] In some embodiments, the first cover layer material layer 465 may be applied to the entire surface of the first waveguide 413 and then selectively removed in portions (such as any area through which light 450 is to pass, including vertical facets along the second region 414). In other embodiments, the first cover layer material layer 465 may be selectively applied to portions of the surface of the first waveguide 413, such as using one or more masks, so that the areas from which light exits the waveguide are not covered.

[0078] Similarly, in some embodiments, the second cover layer material layer 462 may be applied to the entire surface of the second waveguide 423 and then selectively removed in portions (such as any area through which light 450 is to pass, including the vertical facets along the fourth region 424). In other embodiments, the second cover layer material layer 462 may be selectively applied to portions of the surface of the second waveguide 423, such as using one or more masks, so that the areas from which light exits the waveguide are not covered.

[0079] Although relative to Figures 4A to 4C and / or Figure 4DThe multi-chip photonic assembly 400 is illustrated and described as including specific components arranged in a particular manner, but it should be understood that this is an example. Other configurations are possible and contemplated in various specific embodiments without departing from the scope of this disclosure.

[0080] By way of example, the multi-chip photonic assembly 400 is illustrated and described as having a first photonic integrated circuit 410 coupled to a second photonic integrated circuit 420. However, in various specific embodiments, any number (such as three, ten, etc.) of photonic integrated circuits may be coupled together. Various configurations are possible and contemplated without departing from the scope of this disclosure. In addition, each photonic integrated circuit (of the multi-chip photonic assembly 400 and other multi-chip photonic assemblies described herein) may include additional photonic components (e.g., beam splitters, multiplexers, external couplers, additional waveguides) not shown herein.

[0081] As another example, light 450 is illustrated and described as traveling from a first photonic integrated circuit 410 to a second photonic integrated circuit 420. However, it should be understood that this is an example. In various examples, light 450 may travel from the second photonic integrated circuit 420 to the first photonic integrated circuit 410. In still other examples, light 450 may travel from the first photonic integrated circuit 410 to the second photonic integrated circuit 420 at some times and / or at some locations, and from the second photonic integrated circuit 420 to the first photonic integrated circuit 410 at other times and / or at other locations. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0082] In yet another example, the adiabatic cone of the second region 414 and the adiabatic cone of the fourth region 424 are illustrated as having the same length. However, it should be understood that this is merely an example. In various specific embodiments, the adiabatic cone of the second region 414 and the adiabatic cone of the fourth region 424 may have different lengths. The lengths of the adiabatic cones of the second region 414 and the fourth region 424 may be wavelength- and / or geometry-dependent. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0083] In various specific implementations, the multi-chip photonic component may include: a first photonic integrated circuit, the first photonic integrated circuit including a first waveguide having a first region occupying a first horizontal plane and having a first vertical dimension, and a second region having a second vertical dimension larger than the first vertical dimension, the second region including a first adiabatic cone. The multi-chip photonic component may also include: a second photonic integrated circuit, the second photonic integrated circuit including a second waveguide and vertically stacked on the first photonic integrated circuit, the second waveguide having a third region occupying a second horizontal plane and having a third vertical dimension, and a fourth region having a fourth vertical dimension larger than the third vertical dimension, the fourth region including a second adiabatic cone. The second region may be positioned in the second horizontal plane. The second region and the fourth region may alter the mode of light traveling between the first photonic integrated circuit and the second photonic integrated circuit.

[0084] In some examples, the second region may overlap with the fourth region in a first horizontal plane and a second horizontal plane. In various such examples, the multi-chip photonic assembly may also include an anti-reflective coating positioned between the second and fourth regions. In some such examples, the first adiabatic cone may taper horizontally from a first side of the second region facing the fourth region toward a second side of the second region opposite to the first side. In many such examples, the first adiabatic cone may taper vertically from a first side of the second region facing the fourth region toward a second side of the second region opposite to the first side. In some such examples, the second and fourth regions may cooperate to define a gap between the second and fourth regions, and this gap may be filled with at least one of air or an optically transparent underfill.

[0085] In many examples, the second region may include the first angled facet, and the fourth region may include the second angled facet facing the first angled facet in the first horizontal plane and the second horizontal plane.

[0086] The "adiabatic cone transfer" implementation relies on direct contact between waveguides on two chips to transfer light. When the bottom waveguide narrows and the top waveguide widens, light can be transferred directly from the bottom waveguide to the top waveguide without propagating through any air gap. This implementation offers very low loss, extremely wideband wavelength performance, and the potential for very low back reflection.

[0087] For example, Figure 5A A side view of a fifth exemplary multi-chip photonic component 500 is depicted. The multi-chip photonic component 500 can realize photonic vias using an adiabatic cone transfer mechanism.

[0088] The multi-chip photonic assembly 500 may include a first photonic integrated circuit 510 (or a bottom chip) coupled to a second photonic integrated circuit 520 (or a top chip), which are stacked vertically in a flip-chip arrangement (relative to a vertical axis 560). The first photonic integrated circuit 510 may include a first substrate 511 (such as silicon), a first buried oxide layer 512, and a first waveguide 513 (such as a silicon waveguide). Similarly, the second photonic integrated circuit 520 may include a second substrate 521 (such as silicon), a second buried oxide layer 522, and a second waveguide 523 (such as a silicon waveguide). Light 550 (which may include one or more wavelengths supporting a narrowband or broadband embodiment) may be transmitted between the first waveguide 513 and the second waveguide 523, thus transmitting light 550 between the first photonic integrated circuit 510 and the second photonic integrated circuit 520.

[0089] The first waveguide 513 may have a first vertical dimension corresponding to a first region, which is smaller in height than the second region 514, and the second region has a second vertical dimension larger than the first dimension. Similarly, the second waveguide 523 may have a third vertical dimension corresponding to a third region, which is smaller in height than the fourth region 524, and the fourth region has a fourth vertical dimension larger than the third dimension. The first waveguide 513 and the second waveguide 523 may occupy different horizontal planes (relative to the horizontal axis 561). However, a portion of the second region 514 of the first waveguide 513 may vertically contact a portion of the fourth region 524 of the second waveguide 523 in the thermally insulating transfer region 555. If one or more optically transparent adhesives and / or other optically transparent materials are positioned between a portion of the second region 514 of the first waveguide 513 and a portion of the fourth region 524 of the second waveguide 523, that portion of the second region may still vertically contact that portion of the fourth region in the thermally insulating transfer region 555.

[0090] Figure 5B Depicting Figure 5A A top view of the multi-chip photonic assembly 500, wherein the second substrate 521 and the second buried oxide 522 of the second integrated circuit 520 are removed for clarity. As shown, a first region of the first waveguide 513 may have a width 554, and a second region 514 and a fourth region 524 may each form an adiabatic cone. The adiabatic cone of the second region 514 may taper from a first side of the first waveguide 513 corresponding to the first region toward a second side of the first waveguide 513 corresponding to the second region 514. Similarly, the adiabatic cone of the fourth region 524 may taper from a first side of the second waveguide 523 corresponding to the third region toward a second side of the second waveguide 523 corresponding to the fourth region 524. These adiabatic cones may function to extend and reduce the mode of light 550, respectively.

[0091] about Figure 5A and Figure 5B As light 550 travels from the first side of the first waveguide 513 corresponding to the first region to the second side of the first waveguide 513 corresponding to the second region 514, the mode of light 550 can change, thus expanding corresponding to the larger vertical dimension of the second region 514. When the second region 514 narrows and the fourth region 524 widens, light 550 can travel directly from the first waveguide 513 to the second waveguide 523 without propagating through any air gap (this can result in very low loss, extremely wideband wavelength performance, and extremely low back reflection). From there, light 550 can travel from the first side of the second waveguide 523 corresponding to the fourth region 524 to the second side of the second waveguide 523 corresponding to the third region. As light 550 travels in this way, the mode of light 550 can change, thus contracting as the larger vertical dimension of the fourth region 524 changes to the smaller vertical dimension of the third region of the second waveguide 523. In this way, the mode of optical 550 can be changed from the first horizontal plane of the first region of the first waveguide 513 to the second horizontal plane of the third region of the second waveguide 523.

[0092] Area 514 in Figure 5A and Figure 5B The diagram shows a region 514 with uniform vertical dimensions. However, it should be understood that this is an example. In various specific embodiments, the vertical dimensions of the second region 514 may be varied from the vertical dimensions of the first region of the first waveguide 513 by tilting, bending, stepping, or otherwise altering to the maximum vertical dimensions of the second region 514. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0093] Area 4, 524 Figure 5A and Figure 5B The diagram shows a region 524 with a uniform vertical dimension. However, it should be understood that this is an example. In various specific embodiments, the vertical dimension of the fourth region 524 may be varied from the vertical dimension of the third region of the second waveguide 523 by tilting, bending, stepping, or otherwise altering to the maximum vertical dimension of the fourth region 524. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0094] Refer again Figure 5AA first region of the first waveguide 513 may be separated from the second waveguide 523 by a vertical gap 552. This vertical gap 552 may provide space for one or more layers of overlay material (such as oxides), air, one or more coupling structures (not shown) coupling the first photonic integrated circuit 510 to the second photonic integrated circuit 520 (such as one or more adhesives; epoxy resin or other bottom fillers; post and bump configurations in which one or more posts disposed on one of the first photonic integrated circuit 510 and the second photonic integrated circuit 520 (such as those formed using one or more of the first waveguide 513 and / or the second waveguide 523) are connected to one or more gold or other solder bumps located on the other of the first photonic integrated circuit 510 and the second photonic integrated circuit 520, the solder bumps flowing back thereto to bond to the posts, etc.), one or more anti-reflective coatings, etc. The vertical gap 552 also prevents the first region of the first waveguide 513 from contacting the second waveguide 523.

[0095] The second vertical dimension of the second region 514 and the fourth vertical dimension of the fourth region 524 can have a minimum height. This can be expressed by the following formula: h min =s trip + Vertical gap / 2, where h min This represents the minimum height of region 514 or region 524, h. strip This indicates the height of the other portions of the corresponding waveguides (i.e., the first region of the first waveguide 513 for the second region 514 and the third region of the second waveguide 523 for the fourth region 524), and vertical gap / 2 indicates half of the gap 552 in the vertical direction. For example, a height of 4 micrometers for the second vertical dimension of the second region 514 and the fourth vertical dimension of the fourth region 524 can leave 3 micrometers for the first region of the first waveguide 513 and the third region of the second waveguide 523 and leave 2 micrometers for the gap 552 in the vertical direction (this can leave space for the oxide capping layer and / or other materials).

[0096] The first photonic integrated circuit 510 and the second photonic integrated circuit 520 can be fabricated by epitaxial growth and subsequent etching. For example, the wafer may have a silicon substrate covered by a buried oxide layer, which itself is covered by a 3-micron silicon layer. A 1-micron silicon layer can be added by epitaxial growth prior to subsequent etching. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0097] The adiabatic cone transfer embodiment illustrated and described above can have low coupling losses (e.g., less than 1 dB), allow for very wide bandwidth performance, and require relatively little epitaxial growth (e.g., epitaxial silicon growth) (e.g., 1 micrometer epitaxial growth compared to the 5 micrometer epitaxial growth of the adiabatic butt coupler embodiment illustrated and discussed above). However, performance can be sensitive to the presence of any vertical gap between the second region 514 and the fourth region 524. For example, a 100-nanometer oxide gap can reduce transmittance to less than 10 percent. Furthermore, this adiabatic cone transfer embodiment can require a considerably long adiabatic cone, such as exceeding 1000 micrometers.

[0098] Although relative to Figures 5A to 5B The multi-chip photonic assembly 500 is illustrated and described as including specific components arranged in a particular manner, but it should be understood that this is an example. Other configurations are possible and contemplated in various specific embodiments without departing from the scope of this disclosure.

[0099] By way of example, the multi-chip photonic component 500 is illustrated and described as having a first photonic integrated circuit 510 coupled to a second photonic integrated circuit 520. However, in various specific embodiments, any number (such as three, ten, etc.) of photonic integrated circuits may be coupled together. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0100] As another example, light 550 is illustrated and described as traveling from a first photonic integrated circuit 510 to a second photonic integrated circuit 520. However, it should be understood that this is an example. In various examples, light 550 may travel from the second photonic integrated circuit 520 to the first photonic integrated circuit 510. In still other examples, light 550 may travel from the first photonic integrated circuit 510 to the second photonic integrated circuit 520 at some times and / or at some locations, and from the second photonic integrated circuit 520 to the first photonic integrated circuit 510 at other times and / or at other locations. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0101] In yet another example, the adiabatic cone of the second region 514 and the adiabatic cone of the fourth region 524 are illustrated as having the same length. However, it should be understood that this is merely an example. In various specific embodiments, the adiabatic cone of the second region 514 and the adiabatic cone of the fourth region 524 may have different lengths. The lengths of the adiabatic cones of the second region 514 and the fourth region 524 may be wavelength- and / or geometry-dependent. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0102] In some specific implementations, the multi-chip photonic component may include: a first photonic integrated circuit, the first photonic integrated circuit including a first waveguide having a first region occupying a first horizontal plane and having a first vertical dimension, and a second region having a second vertical dimension larger than the first vertical dimension, the second region having a first adiabatic cone. The multi-chip photonic component may further include: a second photonic integrated circuit, the second photonic integrated circuit including a second waveguide and vertically stacked on the first photonic integrated circuit, the second waveguide having a third region occupying a second horizontal plane and having a third vertical dimension, and a fourth region having a fourth vertical dimension larger than the third vertical dimension, the fourth region including a second adiabatic cone. The second region may vertically contact the second waveguide. The second region and the fourth region may alter the mode of light traveling between the first photonic integrated circuit and the second photonic integrated circuit.

[0103] In various examples, the second region may vertically contact the second waveguide via an optically transparent adhesive. In some examples, the multi-chip photonic assembly may also include an adiabatic transfer region in which a second adiabatic cone vertically overlaps with a first adiabatic cone. In various such examples, light may travel between the first and second waveguides where the second region vertically contacts the second waveguide.

[0104] In some examples, the multi-chip photonic component may further include a capping material positioned between the first and second waveguides. In many examples, the first and second adiabatic cones may taper relative to each other. In some examples, the second region may be adjacent to the fourth region and positioned relative to the third region.

[0105] A vertical multimode interferometric coupler implementation relies on interference between optical modes to transmit light. After propagating a certain distance, the input optical mode on the bottom plane can be imaged to a mirror position on the top plane, and the light can then propagate across a small air gap to reach the target waveguide on another chip. This implementation offers the potential for very low loss and good tolerance to misalignment between chips. Anti-reflective coatings and angled facets can be used to minimize back reflections at the gap.

[0106] For example, Figure 6A A side view depicting a sixth exemplary multi-chip photonic component 600 is shown. The multi-chip photonic component 600 can realize photonic vias using a vertical multimode interference coupler mechanism.

[0107] The multi-chip photonic assembly 600 may include a first photonic integrated circuit 610 (or a bottom chip) coupled to a second photonic integrated circuit 620 (or a top chip), and they are stacked vertically in a flip-chip arrangement (relative to a vertical axis 660). The first photonic integrated circuit 610 may include a first substrate 611 (such as silicon), a first buried oxide layer 612, and a first waveguide 613 (such as a silicon waveguide). Similarly, the second photonic integrated circuit 620 may include a second substrate 621 (such as silicon), a first buried oxide layer 622, and a second waveguide 623 (such as a silicon waveguide). Light 650 (which may include one or more wavelengths) may be transmitted between the first waveguide 613 and the second waveguide 623, thus transmitting light 650 between the first photonic integrated circuit 610 and the second photonic integrated circuit 620.

[0108] The first waveguide 613 may have a first vertical dimension corresponding to a first region, which is smaller in height than the second region 614, which has a second vertical dimension larger than the first dimension. The second waveguide 623 may have a third vertical dimension. The first region of the first waveguide 613 may occupy a different horizontal plane (relative to the horizontal axis 661) from the second waveguide 623. However, the second region 614 of the first waveguide 613 may occupy the same and / or similar horizontal plane as the second waveguide 623, such that the second region 614 and the second waveguide 623 have vertical facets that face each other horizontally across the coupling gap 653.

[0109] As light 650 travels from the first side of the first waveguide 613 corresponding to the first region to the second side of the first waveguide 613 corresponding to the second region 614, the change in height of the first waveguide 613 from the first region to the second region 614 splits the light into multiple optical modes. The size of the second region 614 is set such that interference between the optical modes, after propagating a certain distance through the second region 614, causes the input optical mode on the bottom plane of the second region 614 to be imaged onto a mirror position on the top plane of the second region 614. Then, light 650 can propagate across the coupling gap 653 to reach the second waveguide 623. From there, light 650 can travel from the first side of the second waveguide 623 near the coupling gap 653 to the second side of the second waveguide 623 opposite to the first side. In this way, the mode of light 650 can be changed from the first horizontal plane of the first region of the first waveguide 613 to the second horizontal plane of the second waveguide 623.

[0110] Figure 6B Depicting from Figure 6A A top view of the first photonic integrated circuit 610 removed from the multi-chip photonic assembly 600. As shown, the first waveguide 613 may have a width of 654, which can be measured in single-digit micrometers. Also shown, reference Figure 6A and Figure 6BAs shown, the second region 614 may have a uniform horizontal dimension extending from the first side of the second region 614 (facing the second waveguide 623) to a second side of the second region 614 opposite to the first side.

[0111] Area 614 in Figure 6A and Figure 6B The diagram shows a region 614 with a uniform vertical dimension. However, it should be understood that this is an example. In various specific embodiments, the vertical dimension of the second region 614 may be varied from the vertical dimension of the first region of the first waveguide 613 by tilting, bending, stepping, or otherwise altering to the maximum vertical dimension of the second region 614. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0112] Figure 6C Depicting from Figure 4A A bottom view of the second photonic integrated circuit 620 removed from the multi-chip photonic component 600, wherein the substrate 621 has been removed for clarity.

[0113] Refer again Figure 6A A first region of the first waveguide 613 may be separated from the second waveguide 623 by a vertical gap 652. This vertical gap 652 may provide space for one or more layers of overlay material (e.g., a material with a lower refractive index than the waveguide, such as an oxide), air, one or more coupling structures (not shown) coupling the first photonic integrated circuit 610 to the second photonic integrated circuit 620 (such as one or more adhesives; epoxy resin or other bottom fillers; pillar and bump configurations in which one or more pillars disposed on one of the first photonic integrated circuit 610 and the second photonic integrated circuit 620 (such as pillars formed using one or more of the first waveguide 613 and / or the second waveguide 623) are connected to one or more gold or other solder bumps located on the other of the first photonic integrated circuit 610 and the second photonic integrated circuit 620, which flow back to the pillars, etc.), one or more anti-reflective coatings, etc. The vertical gap 652 also prevents the first region of the first waveguide 613 from contacting the second waveguide 623.

[0114] The second vertical dimension of the second region 614 can have a minimum height. This can be expressed by the following formula: h min =2h strip + Vertical gap, where h min This indicates the minimum height of region 614 in the second area, 2h. stripThe vertical gap represents twice the height of the first region of the first waveguide 613, and the vertical gap represents the gap 652 in the vertical direction. For example, the 8-micrometer height of the second vertical dimension of the second region 614 and the fourth vertical dimension of the fourth region 624 can leave a 3-micrometer height for the first region of the first waveguide 613 and the second waveguide 623 and a 2-micrometer height for the vertical gap 652 (this can leave space for the oxide coating and / or other materials).

[0115] To accommodate the second vertical dimension of the second region 614, the second photonic integrated circuit 620 defines a cavity 655. The cavity 655 extends at least partially through the first buried oxide layer 622 of the second photonic integrated circuit 620. Figure 6A In the variant shown, cavity 655 extends completely through the first buried oxide layer 622 and at least partially through the second substrate 621. When as... Figure 6A When the first photonic integrated circuit 610 and the second photonic integrated circuit 620 are stacked vertically, the second region 614 of the first waveguide 613 extends at least partially into the cavity 655 of the second photonic integrated circuit 620. This allows a portion of the second region 614 of the first waveguide 613 to occupy the same horizontal plane (relative to the horizontal axis 661) as a portion of the second waveguide 623.

[0116] The first photonic integrated circuit 610 can be fabricated via epitaxial growth and subsequent etching. For example, the wafer may have a silicon substrate covered by a buried oxide layer, which itself is covered by a 3-micron silicon layer. Silicon can be added via epitaxial growth prior to subsequent etching. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0117] The specific implementation of this multimode interference coupler illustrated and described above can rely on multimode interference to shift the optical modes of light 650 to different planes. The relatively large cross-section of the first waveguide 613 at the coupling gap 653 provides good tolerance for misalignment. Peak transmission can be quite high, such as having a loss of less than 1 dB. However, multimode interference can be a narrowband device. Higher bandwidth can increase loss, and multimode interference can be used for pre-multiplexers (and / or multiplexers can be used to narrow the band before the multimode interference coupler, and demultiplexers can be used to widen the band after the multimode interference coupler). Furthermore, novel silicon growth and etching can lead to challenging fabrication.

[0118] Although the tolerance for misalignment has been discussed above, it should be understood that this is an example. Misalignment can result in greater loss of light 650 transmission, thereby causing parasitic light and / or other light 650 modes that can be sources of noise. However, in some specific implementations, some such misalignment may be acceptable and / or otherwise considered. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0119] Although relative to Figures 6A to 6C The multi-chip photonic assembly 600 is illustrated and described as including specific components arranged in a particular manner, but it should be understood that this is an example. Other configurations are possible and contemplated in various specific embodiments without departing from the scope of this disclosure.

[0120] By way of example, the multi-chip photonic component 600 is illustrated and described as having a first photonic integrated circuit 610 coupled to a second photonic integrated circuit 620. However, in various specific embodiments, any number (such as three, ten, etc.) of photonic integrated circuits may be coupled together. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0121] As another example, light 650 is illustrated and described as traveling from a first photonic integrated circuit 610 to a second photonic integrated circuit 620. However, it should be understood that this is an example. In various examples, light 650 may travel from the second photonic integrated circuit 620 to the first photonic integrated circuit 610. In still other examples, light 650 may travel from the first photonic integrated circuit 610 to the second photonic integrated circuit 620 at some times and / or at some locations, and from the second photonic integrated circuit 620 to the first photonic integrated circuit 610 at other times and / or at other locations. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0122] In several specific embodiments, the multi-chip photonic component may include: a first photonic integrated circuit, the first photonic integrated circuit including a first waveguide having a first region occupying a first horizontal plane and having a first vertical dimension, and a second region having a second vertical dimension larger than the first vertical dimension. The multi-chip photonic component may further include: a second photonic integrated circuit, the second photonic integrated circuit including a second waveguide occupying a second horizontal plane and vertically stacked on top of the first photonic integrated circuit. The second region may be positioned in the second horizontal plane. The second region may alter the mode of light traveling between the first photonic integrated circuit and the second photonic integrated circuit.

[0123] In various examples, the second region may transmit light traveling between the first and second photonic integrated circuits using interference between optical modes. In some examples, the second region may have a uniform horizontal dimension from a first side of the second region facing the second waveguide to a second side of the second region opposite to the first side. In many examples, the second vertical dimension may be uniform from the first side of the second region facing the second waveguide to the second side of the second region opposite to the first side. In various examples, the first waveguide may horizontally define a gap between the second region and the second waveguide. In some examples, the second waveguide may have a third vertical dimension smaller than the second vertical dimension.

[0124] Figures 7A to 7E The fabrication of photonic integrated circuits is illustrated. Figure 7A An exemplary wafer for use in photonic integrated circuits is depicted. The wafer can be used to fabricate... Figures 1 to 6C and Figures 8A to 8C One or more of the first photonic integrated circuits 410, 510, 610, 802 and / or the second photonic integrated circuits 420, 520, 620, 804. The wafer may include a substrate 711 (such as a silicon substrate), a buried oxide layer 712, and a layer 713 (such as a silicon layer). For example, the height of the buried oxide layer 712 may be one micrometer, and the layer 713 may be a three-micrometer silicon layer, but these are exemplary measurements and provided by way of illustration. Actual measurement results may vary in different embodiments.

[0125] Figure 7B Depicting Figure 7A An exemplary wafer after performing an epitaxial growth operation. This can result in the epitaxial growth of layer 713, thereby providing a thicker layer for processing and feature formation.

[0126] Figure 7C Depicting Figure 7B The wafer after the first etching operation. The first etching operation removes a portion of layer 713 so that a portion of layer 713 protrudes from the rest of the surface.

[0127] Figure 7D Depicting Figure 7C The wafer after performing a second etching operation. This second etching operation removes an entire area of ​​layer 713, thereby exposing one or more portions of the buried oxide layer 712.

[0128] Figure 7E Depicting Figure 7D The wafer after a deep cavity etching operation. This deep cavity etching operation can remove the entire area of ​​the buried oxide layer 712 and / or a portion of the substrate 711.

[0129] Available Figure 7EOne or more additional operations are then performed. Such additional operations may include one or more back-end processing steps, flip-chip bonding, etc. Various configurations are possible and contemplated without departing from the scope of this disclosure.

[0130] Figure 8A A side view of a sixth exemplary multi-chip photonic assembly 800 is shown. Similar to the above description... Figures 4A to 4D The multi-chip photonic component 400 and multi-chip photonic component 800 describe a pattern of light that is vertically extended before it is transmitted between photonic integrated circuits. Instead of using a cone (extended towards the facets of the waveguide) to vertically extend the pattern in the multi-chip photonic component 400, the multi-chip photonic component 800 uses waveguide segments made of two different waveguide materials to extend the pattern.

[0131] The multi-chip photonic assembly 800 may include a first photonic integrated circuit 802 (or a bottom chip) coupled to a second photonic integrated circuit 804 (or a top chip), which are stacked vertically in a flip-chip arrangement (relative to the vertical axis 860). The first photonic integrated circuit 802 may include a first substrate 810 (such as silicon), a first waveguide 806, and a first buried oxide layer 808 located between the first substrate 810 and the first waveguide 806. Similarly, the second photonic integrated circuit 804 may include a second substrate 826 (such as silicon), a second waveguide 822, and a second buried oxide layer 824 located between the second substrate 826 and the second waveguide 822. The first and / or second photonic integrated circuits may optionally include an additional low-refractive-index capping layer (not shown) having a lower refractive index than the materials of the first and second waveguides, thereby providing optical confinement as discussed above. Light 850 (which in...) Figure 8B and Figure 8C The light 850 can be transmitted between the first waveguide 806 and the second waveguide 822, and may include one or more wavelengths supporting narrowband or broadband implementations.

[0132] Figure 8B Depicting from Figure 8A A top view of the first photonic integrated circuit 802 removed from the multi-chip photonic assembly 800. The first waveguide 806 is formed of a first waveguide material (e.g., silicon), which is partially covered by a second waveguide material (e.g., silicon nitride, polymer, etc.) having a lower refractive index compared to the first waveguide material. Figure 8A and Figure 8BAs shown, the first waveguide 806 includes a first region connected to a second region (i.e., the distal end of the first region is coupled to the proximal end of the second region). The first region is formed by a first segment 814 (also referred to as "first segment 814") of the first waveguide material, and the second region is formed by a second segment 816 (also referred to as "second segment 816") of the first waveguide material and a segment 818 (also referred to as "fifth segment 818") of the second waveguide material covering the second segment 816. The first segment 814 and the second segment 816 may be formed as a monolithic component, and in these cases, the interface between the first and second regions is defined by adding the segment 818 of the second waveguide material to the second region. The fifth segment 818 is higher than the second segment 816 and at least as wide, such that the outer dimensions of the fifth segment 818 define the outer dimensions of the second region.

[0133] The first region has a vertical dimension (“first vertical dimension”) that is smaller in height than the vertical dimension of the second region (“second vertical dimension”). In some cases, the second region has a larger width compared to the first region. These dimensions also determine the size of the vertical facet 820 at the distal end of the first waveguide 806. The first segment 814 has a width (“first width”) at the junction of the first and second regions (i.e., at the distal end of the first region). The second segment 816 is thermally tapered in the second region such that the width of the second segment 816 narrows from the first width (in the direction from the proximal end of the second region toward the distal end / vertical facet of the second region). In some cases, the second segment 816 terminates before the distal end of the second region. In these cases, the vertical facet 820 at the distal end of the second region is formed entirely of a segment 818 of the second waveguide material.

[0134] Figure 8C Depicting from Figure 8A A top view of the second photonic integrated circuit 804 removed from the multi-chip photonic assembly 800. The second waveguide 822 is formed of a third waveguide material (e.g., silicon), which is partially covered by a fourth waveguide material (e.g., silicon nitride, polymer, etc.) having a lower refractive index compared to the third waveguide material. It should be understood that the first waveguide material (from the first waveguide 806) may be the same material as or a different material from the third waveguide material (from the second waveguide 822). Similarly, the second waveguide material (from the first waveguide 806) may be the same material as or a different material from the fourth waveguide material (from the second waveguide).

[0135] like Figure 8A and Figure 8CAs shown, the second waveguide 808 includes a third region connected to the fourth region (i.e., the distal end of the third region is coupled to the proximal end of the fourth region). The third region is formed by a first segment 830 (also referred to as "third segment 830") of the third waveguide material, and the fourth region is formed by a second segment 832 (also referred to as "fourth segment 832") of the third waveguide material and a segment 834 (also referred to as "sixth segment 834") of the fourth waveguide material covering the fourth segment 832. The third segment 830 and the fourth segment 832 may be formed as a monolithic component, and in these cases, the interface between the third and fourth regions is defined by adding the segment 834 of the fourth waveguide material to the fourth region. The sixth segment 834 is higher than the fourth segment 832 and at least as wide, such that the outer dimensions of the sixth segment 834 define the outer dimensions of the fourth region.

[0136] The third region has a vertical dimension (“third vertical dimension”) that is smaller in height than the vertical dimension of the fourth region (“fourth vertical dimension”). In some cases, the fourth region has a larger width compared to the third region. These dimensions also determine the size of the vertical facet 836 at the distal end of the second waveguide 822. The third segment 814 has a width (“second width”, which may be the same as or different from the first width) at the junction of the third and fourth regions (i.e., at the distal end of the third region). The fourth segment 816 thermally tapers in the fourth region such that the width of the fourth segment 816 narrows from the second width (in the direction from the proximal end of the fourth region toward the distal end / vertical facet of the fourth region). In some cases, the fourth segment 816 terminates before the distal end of the fourth region. In these cases, the vertical facet 836 at the distal end of the second region is formed entirely of the segment 818 of the second waveguide material.

[0137] When Figure 8A When the first photonic integrated circuit 802 and the second photonic integrated circuit 804 are stacked vertically, the distal end of the first waveguide 806 faces the distal end of the second waveguide 822. This positions the vertical facet 820 of the first waveguide 806 facing the vertical facet 836 of the second waveguide 822, and separates them horizontally (i.e., along the horizontal axis 861) by a gap 838. In this way, the fifth segment 818 can occupy a common horizontal plane (relative to the horizontal axis 861) with the sixth segment 834. Conversely, the first segment 814 and the second segment 816 of the first waveguide material are positioned in a different horizontal plane (relative to the horizontal axis 861) than the third segment 830 and the fourth segment 832 of the third waveguide material.

[0138] When light 850 (e.g., at the proximal end of the first waveguide) is introduced into the first waveguide 806, it travels along the first waveguide material from the first region to the second region. As light 850 travels from the first segment 814 to the second segment 816, the narrowing width of the second segment 816 may no longer be able to confine the light 850, causing the mode to extend into the second waveguide material (i.e., the fifth segment 818). When the mode extends, the second waveguide material will come into play to confine the light 850. The light will travel through the second waveguide material in the second region until it reaches the vertical facet 820 of the first waveguide 806.

[0139] Light will cross the gap 838 from the vertical facet 820 of the first waveguide 806 to the vertical facet 836 of the second waveguide 822. From there, light 850 is constrained by and travels through the fourth waveguide material in the fourth region (i.e., the sixth segment 834). As the width of the fourth segment 832 increases (i.e., towards the proximal end of the fourth region), light 850 will begin to couple into and be constrained by the third waveguide material (thus, a contraction mode). When light 850 reaches the proximal end of the fourth region, light 850 can be completely constrained by the third waveguide material. In other words, light 850 can enter the second waveguide 822 through the sixth segment 834, couple into the fourth segment 832 of the third waveguide material, and then be transmitted to the third segment 830 of the third waveguide material. In this way, light 850 can be transmitted from the proximal end of the first waveguide 806 to the proximal end of the second waveguide 822. Similarly, light introduced into the proximal end of the second waveguide 822 can be transmitted to the proximal end of the first waveguide 806. This results in light being transmitted from a first horizontal plane in one photonic integrated circuit to a different horizontal plane in another photonic integrated circuit.

[0140] Although the second region of the first waveguide 806 and the fourth region of the second waveguide 822 are in Figure 8A The diagram shows regions with uniform vertical dimensions, but in some cases, the second and / or fourth regions have varying vertical dimensions. For example, the height of the fifth segment 818 (and therefore the height of the second region) may be varied from the vertical dimension of the first region by tilting, bending, stepping, or otherwise changing to the maximum vertical dimension of the second region. Additionally or alternatively, the height of the sixth segment 834 (and therefore the height of the fourth region) may be varied from the vertical dimension of the third region by tilting, bending, stepping, or otherwise changing to the maximum vertical dimension of the fourth region.

[0141] As discussed above regarding other multi-chip photonic components, the first photonic integrated circuit 802 can be vertically separated from the second photonic integrated circuit 802 to provide space for one or more cladding material layers (such as oxides mentioned above), air, and one or more coupling structures (such as one or more adhesives, epoxy resins, or other underfills, pillars, and bump configurations discussed above) between the waveguides of the different photonic integrated circuits. Although photonic integrated circuits 802 and 804 are... Figure 8A The diagram shows a flip-chip arrangement for coupling, but this does not require electrical connections between the photonic integrated circuits. Electrical connections can be made between the photonic integrated circuits if needed (e.g., to allow electrical signal transmission between them).

[0142] To accommodate the fourth vertical dimension of the fourth region of the second waveguide 822, the first photonic integrated circuit 802 defines a cavity 812. The cavity 812 extends at least partially through the first buried oxide layer 808 of the first photonic integrated circuit 802. Figure 8A In the variant shown, cavity 812 extends completely through the first buried oxide layer 808 and at least partially through the first substrate 810. When as... Figure 8A When the first photonic integrated circuit 802 and the second photonic integrated circuit 804 are stacked vertically, the fourth region (specifically, the sixth segment 834) of the second waveguide 822 extends at least partially into the cavity 812 of the first photonic integrated circuit 802. This allows a portion of the fourth region of the second waveguide 822 to occupy the same horizontal plane (relative to the horizontal axis 861) as a portion of the first region of the first waveguide 806.

[0143] Similarly, to accommodate the second vertical dimension of the second region of the first waveguide 806, the second photonic integrated circuit 804 defines a cavity 828. The cavity 828 extends at least partially through the second buried oxide layer 824 of the second photonic integrated circuit 804. Figure 8A In the variant shown, cavity 828 extends completely through the second buried oxide layer 824 and at least partially through the second substrate 826. When as... Figure 8A When the first photonic integrated circuit 802 and the second photonic integrated circuit 804 are stacked vertically, a second region of the first waveguide 806 extends at least partially into the cavity 828 of the second photonic integrated circuit 804. This allows a portion of the second region of the first waveguide 806 to occupy the same horizontal plane (relative to the horizontal axis 861) as a portion of the third region of the second waveguide 822. The first photonic integrated circuit 802 and the second photonic integrated circuit 804 can be fabricated by additional steps such as those discussed above (e.g., using epitaxial growth and subsequent etching) to deposit and etch additional waveguide material.

[0144] As described above and illustrated in the accompanying drawings, this disclosure relates to a multi-chip photonic assembly. A first photonic integrated circuit and a second photonic integrated circuit having a first waveguide and a second waveguide can be vertically stacked such that a first vertical dimension of the first waveguide and the second waveguide occupies a different horizontal plane in the stack. At least one of the first waveguide and the second waveguide includes a region having a second vertical dimension that is larger than the first vertical dimension and horizontally overlaps with and / or vertically contacts the other waveguide. Light moves vertically from the first vertical dimension to the other vertical dimension through one of these waveguides, changing its mode vertically, such that the light moves from one waveguide to the other.

[0145] While many implementations have been illustrated and described above, it should be understood that these are examples. Various techniques of individual implementations may be combined in various specific implementations without departing from the scope of this disclosure.

[0146] For illustrative purposes, the foregoing description uses specific names to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that specific details are not required to practice the described embodiments. Therefore, the foregoing description of specific embodiments described herein is presented for illustrative and descriptive purposes. They are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. It will be apparent to those skilled in the art that many modifications and variations are possible in light of the teachings above.

Claims

1. A multi-chip photonic component, comprising: A first photonic integrated circuit, the first photonic integrated circuit including a first waveguide, the first waveguide having: A first region, the first region occupying a first horizontal plane and having a first vertical dimension; and A second region, having a second vertical dimension larger than the first vertical dimension, the second region comprising a first adiabatic cone; and The second photonic integrated circuit includes a second waveguide vertically stacked on top of the first photonic integrated circuit, and the second waveguide has: A third region, the third region occupying a second horizontal plane and having a third vertical dimension; and A fourth region, having a fourth vertical dimension larger than the third vertical dimension, includes a second adiabatic cone; wherein: The second region is located in the second horizontal plane; The second region and the fourth region alter the pattern of light traveling between the first photonic integrated circuit and the second photonic integrated circuit; and The first adiabatic cone tapers horizontally, causing the width of the second region to decrease from the first side of the second region facing the fourth region until the second region ends.

2. The multi-chip photonic component of claim 1, wherein the second region overlaps with the fourth region in the first horizontal plane and the second horizontal plane.

3. The multi-chip photonic component according to claim 2, further comprising: An anti-reflective coating is positioned between the second region and the fourth region.

4. The multi-chip photonic assembly of claim 2, wherein the first adiabatic cone tapers horizontally from a first side of the second region facing the fourth region toward a second side of the second region opposite to the first side.

5. The multi-chip photonic assembly of claim 2, wherein the first adiabatic cone tapers vertically from a first side of the second region facing the fourth region toward a second side of the second region opposite to the first side.

6. The multi-chip photonic component according to claim 2, wherein: The second region and the fourth region cooperate to define a gap between the second region and the fourth region; and The gap is filled with at least one of air or an optically transparent bottom filler.

7. The multi-chip photonic component according to claim 1, wherein: The second region includes a first angled facet; and The fourth region includes a second angled facet, which faces the first angled facet in the first horizontal plane and the second horizontal plane.

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