A control method for reducing chip power consumption

Abstract

The application discloses a kind of control methods for reducing chip power consumption, detects equipment state by clock control module, determines the processing mode of clock gating according to equipment state and controls clock control module work, carries out dynamic voltage regulation, dynamic frequency control to functional unit hardware module by dynamic voltage regulation frequency control module, hardware automatic monitoring method is used to carry out clock and voltage control, software dependency is weak, easy to operate, control, and the application scenario of the embodiment of the application weak dependence, convenient expansion.In addition, the embodiment of the application can dynamically control clock, voltage according to the working state of module, to reduce the purpose of chip power consumption, control is simple, easy to realize.The embodiment of the application can be widely applied to chip low power consumption design technical field.

Description

Technical Field

[0001] This invention relates to the field of low-power chip design technology, and in particular to a control method for reducing chip power consumption. Background Technology

[0002] With the rapid development of integrated circuit technology, transistor dimensions and chip area are constantly shrinking, chip integration and performance are continuously improving, and chip operating frequencies are getting higher and higher, leading to increasingly higher power consumption. This increased power consumption significantly impacts the battery life of electronic devices; therefore, low-power design has become an important component of chip design.

[0003] Existing technologies provide low-power solutions for specific chips or scenarios, have limited scalability, cannot be used in certain independent devices, and rely on external control, making them unsuitable for hardware automation. Furthermore, existing technologies, by refining the working scenario and dividing it into multiple operating modes, activate different numbers of functional units based on these modes. This results in high design complexity and consumes a significant amount of circuit space. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an automated, easy-to-control, and easily expandable control method for reducing chip power consumption.

[0005] This invention provides a control method for reducing chip power consumption, comprising: detecting device status through a clock control module, and determining a clock gating processing mode based on the device status; wherein the device status includes at least one of the following: working state, idle state, and delay state; controlling the clock control module to work according to the clock gating processing mode; wherein the clock control module includes a status collection submodule, a command buffer submodule, a delay submodule, and a clock gating submodule; and performing dynamic voltage and frequency modulation control on the functional unit hardware module through a dynamic voltage and frequency modulation control module; wherein the dynamic voltage and frequency modulation control module is composed of a decoding component, a status control component, a frequency modulation component, and a voltage modulation component.

[0006] Optionally, the step of detecting the device status through the clock control module and determining the clock gating processing method based on the device status includes: receiving the status information and configuration command of the functional unit through the status collection submodule; wherein, the status information includes at least one of the following: the interrupt flag signal of the functional unit, the algorithm completion flag signal, and the state of the state machine; the configuration command includes: configuration information sent from the host to the functional unit; when the functional unit is detected to be in a busy state, the device status is marked as a working state, and the clock is enabled through the clock gating submodule; when the functional unit is detected to be in an idle state, the device status is marked as a delayed state; when the delayed state ends, the clock is turned off through clock gating, and the device status is marked as an idle state.

[0007] Optionally, controlling the clock control module to work according to the clock gating processing method includes: loading configuration commands through the command buffer submodule and counting the configuration commands in the counter cache; when all the configuration commands in the command buffer submodule are completed and the count value in the delay counter is equal to the set threshold, the clock of the execution unit is turned off through the clock gating submodule.

[0008] Optionally, loading the configuration command through the command buffer submodule and counting the configuration command in the counter cache includes: loading the configuration command and parsing the type of the configuration command through the command recording unit; re-encoding the configuration command in the command recording unit to form a first configuration command in a unified format; and grouping and counting the first configuration command in the counter cache according to the type of the first configuration command.

[0009] Optionally, the step of shutting down the clock of the execution unit through the clock gating submodule when the count value of the delay counting submodule is equal to the set threshold and all the configuration commands in the command buffer submodule are completed includes: when the configuration command of the execution unit is completed, clearing the configuration command in the counter cache; when the value of the command counter is cleared, initiating a clock shutdown request; and shutting down the clock of the execution unit through the clock gating submodule.

[0010] Optionally, the dynamic voltage and frequency regulation control of the functional unit hardware module via the dynamic voltage and frequency regulation control module includes: setting the default state of the dynamic voltage and frequency regulation control module to an idle state; when it is determined that the functional unit hardware needs voltage regulation, the dynamic voltage and frequency regulation control module enters the voltage regulation state; when it is determined that the functional unit hardware needs frequency regulation but not voltage regulation, the dynamic voltage and frequency regulation control module enters the frequency regulation state; and determining the operation of the dynamic voltage and frequency regulation control module based on its state.

[0011] Optionally, determining the operation of the dynamic voltage and frequency regulation control module based on its state includes: when the dynamic voltage and frequency regulation control module is in an idle state, the module queries a data table to determine whether voltage regulation and / or frequency regulation is required; when the module is in a voltage regulation state, it initiates a voltage regulation request to the system voltage regulation module as needed; if a voltage regulation failure is received, it enters an idle state; if a voltage regulation success is received, it enters a delay state; when the module is in a delay state, it performs voltage stabilization; and when the module is in a frequency regulation state, it initiates a frequency regulation request to the system frequency regulation module.

[0012] Embodiments of the present invention also provide a control device for reducing chip power consumption, comprising: a first module, the first module being configured to detect the device status through a clock control module and determine a clock gating processing method based on the device status; a second module, the second module being configured to control the clock control module to operate according to the clock gating processing method; and a third module, the third module being configured to perform dynamic voltage and frequency regulation control on the functional unit hardware module through a dynamic voltage and frequency regulation control module.

[0013] Embodiments of the present invention also provide an electronic device, including a processor and a memory; the memory is used to store a program; the processor executes the program to implement the method described above.

[0014] Embodiments of the present invention also provide a computer-readable storage medium storing a program that is executed by a processor to implement the method described above.

[0015] The beneficial effects of the embodiments of the present invention are as follows: The embodiments of the present invention detect the device status through a clock control module, determine the clock gating processing method based on the device status, and control the clock control module to operate. A dynamic voltage and frequency modulation control module dynamically regulates the voltage and frequency of the functional unit hardware modules. This employs a hardware-based automatic monitoring method for clock and voltage control, resulting in weak software dependence, ease of operation and control, and weak application scenario dependence, facilitating expansion. Furthermore, the embodiments of the present invention can dynamically control the clock and voltage according to the module's operating status, thereby reducing chip power consumption. The control is simple and easy to implement. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of the method steps provided in the embodiments of the present invention;

[0018] Figure 2 This is a module design structure diagram provided in an embodiment of the present invention;

[0019] Figure 3 This is a flowchart of the clock gating process provided in an embodiment of the present invention;

[0020] Figure 4 This is a structural diagram of the clock control module provided in an embodiment of the present invention;

[0021] Figure 5 This is a clock control timing diagram provided in an embodiment of the present invention;

[0022] Figure 6 This is a structural diagram of the command recording unit provided in an embodiment of the present invention;

[0023] Figure 7 This is a structural diagram of the command clearing unit provided in an embodiment of the present invention;

[0024] Figure 8 This is a structural diagram of the dynamic voltage and frequency regulation control module provided in an embodiment of the present invention;

[0025] Figure 9 This is a flowchart of the dynamic voltage and frequency regulation control module according to an embodiment of the present invention;

[0026] Figure 10 This is a diagram illustrating the low-power control application provided in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0028] To address the problems of existing technologies relying on external control, lacking hardware automation, and being highly complex, this invention proposes a control method to reduce chip power consumption, referring to... Figure 1 , Figure 1This is a flowchart of the method steps provided in an embodiment of the present invention, including: detecting the device status through a clock control module, and determining the clock gating processing mode based on the device status; wherein the device status includes at least one of the following: working state, idle state, and delay state. Controlling the clock control module to work according to the clock gating processing mode; wherein the clock control module includes a status collection submodule, a command buffer submodule, a delay submodule, and a clock gating submodule; dynamically adjusting the voltage and frequency of the functional unit hardware module through a dynamic voltage and frequency modulation control module; wherein the dynamic voltage and frequency modulation control module consists of a decoding component, a status control component, a frequency modulation component, and a voltage adjustment component.

[0029] Specifically, refer to Figure 2 , Figure 2 This is a module design structure diagram provided by the present invention. The low-power control module (power_ctrl) of this embodiment includes a clock control module (clk_ctrl), a dynamic voltage and frequency modulation control module (dvfs_ctrl), a configuration register, and a clock generation module. The configuration register stores configuration commands, and the clock generation module generates the clock signal. The clock control module interacts with the function module via a general-purpose I / O port (GPIO interface). The function module can be, for example, an encryption engine or a DSP (Digital Signal Processing). The clock control module performs clock gating control of the function module, and the dynamic voltage and frequency modulation control module performs dynamic voltage and frequency modulation control. This embodiment includes the following steps S100–S300:

[0030] S100: The device status is detected by the clock control module, and the clock gating processing method is determined according to the device status.

[0031] Specifically, refer to Figure 3 , Figure 3 This is a clock gating processing flowchart provided in an embodiment of the present invention. The device state may include at least one of a working state, an idle state, and a delay state. In this embodiment, refer to... Figure 4 , Figure 4 This is a structural diagram of a clock control module provided in an embodiment of the present invention. The clock control module includes a status collection submodule, a command buffer submodule, a delay submodule, and a clock gating submodule. (Refer to...) Figure 3 Step S100 includes the following steps S110 to S140:

[0032] S110. The status information and configuration commands of the functional unit are received through the status collection submodule. The status information includes at least one of the following: an interrupt flag signal of the functional unit, an algorithm completion flag signal, or the state of the state machine. The configuration commands include: configuration information sent from the host to the functional unit. Based on the status information, the clock control module can detect and determine the current status of the functional unit.

[0033] S120. When a functional unit is detected to be in a busy state, the device status is marked as working, and the clock enable is turned on through the clock gating submodule.

[0034] Specifically, the clock gating submodule is used to turn the clock on and off. (See reference...) Figure 5 , Figure 5 This is a clock control timing diagram provided in an embodiment of the present invention. When a functional unit receives a configuration command from the host, the internal state of the functional unit is busy. The clock control module detects the busy state of the functional unit, marks the device state as working, and enables the clock through the clock gating submodule, keeping the clock on. The working state of the functional unit includes a set of states such as pending interrupt, state machine state, and command buffer clock request.

[0035] S130. When a functional unit is detected to be in an idle state, the device state is marked as a delayed state.

[0036] Specifically, to prevent the clock from being turned off during operation, when the functional unit is detected to be in an idle state, the device status is marked as a delayed state. The delayed submodule consists of a delayed counter, which is responsible for delay counting in the delayed state. The delayed count value can be configured by the host.

[0037] S140. When the delay state ends, the clock is turned off by clock gating, and the device state is marked as idle.

[0038] S200: Control the clock control module to work according to the clock gating processing method.

[0039] Specifically, based on the clock gating processing method, the command buffer submodule in the clock control module operates, referring to... Figure 6 and Figure 7 , Figure 6 This is a command record structure diagram provided in an embodiment of the present invention. Figure 7 This is a command clearing structure diagram provided in an embodiment of the present invention. The command buffer submodule includes a command recording unit and a command clearing unit. Step S200 includes the following steps S210 to S220:

[0040] S210. Load configuration commands through the command buffer submodule and count the configuration commands in the counter cache.

[0041] Specifically, step S210 includes the following steps S211 to S212:

[0042] S211. Load the configuration command and parse the type of the configuration command through the command record unit. In the command record unit, re-encode the configuration command to form a first configuration command in a unified format.

[0043] Specifically, refer to Figure 6 , Figure 6 This is a structural diagram of the command recording unit provided in an embodiment of the present invention. The command buffer module loads configuration commands, and the command recording unit performs command parsing operations to parse the type of the configuration command and re-encode the configuration command. The command re-encoding unifies the command format to form a first configuration command with a unified format. To improve design versatility, the command parsing operation needs to adapt to the commands of various functional units in the SoC chip.

[0044] S212. Based on the type of the first configuration command, group and count the first configuration commands in the counter cache.

[0045] Specifically, the counter cache performs a group counting operation based on the type of the first configuration command. The number of groups in the counter cache can be adjusted according to the number of functional unit command types.

[0046] In addition, the counter cache values ​​of each configuration command are monitored in real time through clock demand collection operations.

[0047] The command buffer submodule reduces the required storage capacity and achieves low area consumption through command parsing, command re-encoding, and command counting operations.

[0048] S220. When all configuration commands in the command buffer submodule are completed and the count value in the delay counter is equal to the set threshold, the clock of the execution unit is turned off through the clock gating submodule.

[0049] In some embodiments, the host intermittently issues configuration commands, and the functional unit performs only brief operations, followed by a short interval before resuming operation. A number of clock cycles elapse between the issuance of a command and the functional unit indicating it is busy. The clock is only turned off when the delay counter equals a set threshold and all commands in the command buffer have been completed. This prevents the functional unit from malfunctioning due to the clock being turned off while it is operating.

[0050] Specifically, step S220 includes the following steps S221 to S223:

[0051] S221. When the configuration command of the execution unit is completed, the configuration command is cleared from the counter cache.

[0052] Specifically, command clearing is performed by the command clearing unit of the command buffer module, see reference. Figure 7 , Figure 7 This is a structural diagram of the command clearing unit provided in an embodiment of the present invention. Each algorithm unit of the functional unit sends the command completion flag to the counter cache, and then the counter cache performs a command clearing operation.

[0053] S222. When the value of the command counter has been cleared, a clock shutdown request is initiated.

[0054] Specifically, the clock request module monitors the counter values ​​of each command in real time. If the counters have been cleared, the clock can initiate a clock shutdown request; otherwise, the clock continues to operate.

[0055] S223. When a clock shutdown request is received, the clock of the execution unit is shut down through the clock gating submodule.

[0056] Specifically, when a clock shutdown request is received, the system enters a delay state. After the delay state ends, the clock gating submodule shuts down the clock of the execution unit.

[0057] This invention provides a hardware-automated clock gating mechanism that coordinates commands and clocks through hardware-automated command buffering and delays. This mechanism controls the clock, improves the stability of the clock gating function, prevents the clock from being frequently turned off, reduces software behavior, and lowers the consumption of the clock tree.

[0058] S300 uses a dynamic voltage and frequency control module to dynamically adjust the voltage and frequency of the functional unit hardware modules.

[0059] Reference Figure 8 , Figure 8 This is a structural diagram of the dynamic voltage and frequency regulation control module provided in this embodiment of the invention. The dynamic voltage and frequency regulation control module (dvfs_ctrl) of this embodiment of the invention comprises a decoding component, a state control component, a frequency regulation component, and a voltage regulation component. The functional unit interacts with the dynamic voltage and frequency regulation control module through the GPIO port, including: the functional unit sending frequency and voltage regulation requests (gpio_req) and voltage data (gpio_data) to the dynamic voltage and frequency regulation control module; and the dynamic voltage and frequency regulation control module sending a feedback signal (gpio_ack) to the functional unit, wherein the voltage data includes frequency regulation information and voltage regulation information.

[0060] Specifically, the moving platform voltage and frequency modulation control module of this embodiment is configured with a VF table. The VF table records the clock source, frequency division control, and voltage information corresponding to each gear position. The VF table of this embodiment is shown in Table 1, which is the VF table provided in this embodiment:

[0061] Table 1

[0062] Bit index describe 31：24 gear 23：16 Clock source 15：8 Clock division 7：0 Voltage

[0063] The VF table in this embodiment of the invention has 32 bits, as shown in Table 1. It can be understood that when looking up the table, bits 0 to 7 represent voltage. The VF table is consulted based on the voltage data range sent by the functional unit to determine the switching clock and voltage, thereby realizing the switching of frequency and voltage. The VF table can be specified according to the working scenario of the functional unit. It should be noted that Table 1 is merely an example and does not limit the specific data of the VF table in this invention.

[0064] Specifically, step S300 includes the following steps S310 to S340:

[0065] S310. Set the default state of the dynamic voltage and frequency regulation control module to idle state.

[0066] S320. When it is determined that the functional unit hardware needs to adjust the voltage, the dynamic voltage and frequency adjustment control module enters the voltage adjustment state.

[0067] S330. When it is determined that the functional unit hardware needs to adjust the frequency but not the voltage, the dynamic voltage and frequency adjustment control module enters the frequency adjustment state.

[0068] S340. Determine the operation of the dynamic voltage and frequency regulation control module based on its status.

[0069] Specifically, in this embodiment of the invention, the dynamic voltage and frequency regulation module communicates with the system voltage regulation module and the system frequency regulation module using a one-time handshake. Optionally, in other embodiments, other communication methods may be used. The system voltage regulation module can be a PMU (Power Management Unit) or a VC (Voltage Control Module). See reference... Figure 9 , Figure 9 This is a flowchart of the dynamic voltage and frequency regulation control module according to an embodiment of the present invention. Step S340 includes the following steps S341 to S344:

[0070] S341. When the dynamic voltage and frequency regulation control module is in an idle state, the dynamic voltage and frequency regulation control module queries the data table to determine whether voltage regulation and / or frequency regulation are required.

[0071] S342. When the dynamic voltage and frequency regulation control module is in the voltage regulation state, the dynamic voltage and frequency regulation control module initiates a voltage regulation request to the system voltage regulation module according to the demand. When it receives feedback that the voltage regulation failed, it enters the idle state. When it receives feedback that the voltage regulation was successful, it enters the delay state.

[0072] Specifically, in the voltage regulation state, the dynamic voltage and frequency regulation control module sends a boost request to the system voltage regulation module. If the voltage regulation fails, the dynamic voltage and frequency regulation control module enters the idle state. If the voltage regulation is successful, the dynamic voltage and frequency regulation control module enters the delay state.

[0073] S343. When the dynamic voltage and frequency regulation control module is in the delay state, the dynamic voltage and frequency regulation control module performs voltage stabilization.

[0074] S344. When the dynamic voltage and frequency regulation control module is in frequency regulation state, the dynamic voltage and frequency regulation control module initiates a frequency regulation request to the system frequency regulation module.

[0075] Specifically, in frequency modulation mode, frequency upscaling or downscaling operations can be performed. If voltage and frequency upscaling are required, voltage upscaling is performed first and then frequency upscaling is performed. If frequency upscaling is required without voltage adjustment, frequency upscaling is performed directly. If frequency and voltage downscaling are required, frequency downscaling is performed first and then voltage downscaling is performed to ensure switching efficiency.

[0076] Embodiments of the present invention also provide a control device for reducing chip power consumption, comprising: a first module, the first module being configured to detect the device status through a clock control module and determine a clock gating processing method based on the device status; a second module, the second module being configured to control the clock control module to operate according to the clock gating processing method; and a third module, the third module being configured to perform dynamic voltage and frequency regulation control on the functional unit hardware module through a dynamic voltage and frequency regulation control module.

[0077] Embodiments of the present invention also provide an electronic device, including a processor and a memory; the memory is used to store a program; the processor executes the program to implement the method described above.

[0078] Embodiments of the present invention also provide a computer-readable storage medium storing a program that is executed by a processor to implement the method described above.

[0079] The embodiments of the present invention have the following beneficial effects:

[0080] 1. The embodiments of the present invention use hardware automatic monitoring and predefined thresholds to control the clock and voltage, which can dynamically control the clock and voltage of the module according to the working scenario, thereby reducing the power consumption of the chip. It has weak software dependence and is easy to operate and control.

[0081] 2. By configuring the command buffer submodule and delay submodule to coordinate commands and clock, the stability of clock gating function can be improved and abnormalities caused by frequent clock shutdown can be prevented.

[0082] 3. The embodiments of the present invention can be easily designed into modules inside the SoC chip, have weak application scenario dependence, and are easy to expand.

[0083] The following is an application scenario provided by an embodiment of the present invention:

[0084] Reference Figure 10 , Figure 10 This is an application diagram of low-power control provided by an embodiment of the present invention. The embodiment of the present invention can utilize functional modules in a SoC chip, using a clock control module to detect device status and determine the clock gating processing method based on the device status; controlling the clock control module to operate according to the clock gating processing method; and using a dynamic voltage and frequency modulation control module to perform dynamic voltage and frequency modulation control on the functional unit hardware modules. This enables fine-grained control of the clock and / or voltage of each functional unit.

[0085] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0086] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0087] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0089] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0090] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0091] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0092] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0093] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A control method for reducing chip power consumption, characterized in that, include: The device status is detected by the clock control module, and the clock gating processing method is determined based on the device status; wherein, the device status includes at least one of the following: working status, idle status, and delay status; The clock control module is controlled to operate according to the clock gating processing method; wherein, the clock control module includes a status collection submodule, a command buffer submodule, a delay submodule and a clock gating submodule; The functional unit hardware module is dynamically controlled for voltage and frequency regulation through a dynamic voltage and frequency regulation control module. This module comprises a decoding component, a status control component, a frequency regulation component, and a voltage regulation component. The module is equipped with a 32-bit VF table, which records the clock source, frequency division control, and voltage information corresponding to each voltage level. Bits 0-7 represent the voltage. The VF table is queried based on the voltage data level sent by the functional unit to determine the switching clock and voltage. The method of controlling the clock control module according to the clock gating process includes: The configuration command is loaded through the command buffer submodule, and the configuration command is counted in the counter cache; When all the configuration commands in the command buffer submodule are completed and the count value in the delay counter is equal to the set threshold, the clock of the execution unit is turned off through the clock gating submodule. The step of loading configuration commands through the command buffer submodule and counting the configuration commands in the counter cache includes: The configuration command is loaded and its type is parsed through the command recording unit. The configuration command is then re-encoded in the command recording unit to form a first configuration command in a unified format. Based on the type of the first configuration command, the first configuration command is grouped and counted in the counter cache; When all configuration commands in the command buffer submodule are completed and the count value in the delay counter equals the set threshold, the clock of the execution unit is turned off through the clock gating submodule, including: When the configuration command of the execution unit is completed, the configuration command is cleared from the counter cache; Once the command counter value has been cleared, a clock shutdown request is initiated. The clock of the execution unit is turned off by the clock gating submodule.

2. The control method for reducing chip power consumption according to claim 1, characterized in that, The process of detecting device status through a clock control module and determining the clock gating method based on the device status includes: The status information and configuration commands of the functional unit are received through the status collection submodule; wherein, the status information includes at least one of the following: the interrupt flag signal of the functional unit, the algorithm completion flag signal, and the state of the state machine; the configuration commands include: configuration information sent from the host to the functional unit; When the functional unit is detected to be in a busy state, the device status is marked as working, and the clock enable is turned on through the clock gating submodule. When the functional unit is detected to be in an idle state, the device state is marked as a delayed state; When the delay state ends, the clock is turned off via clock gating, and the device state is marked as idle.

3. The control method for reducing chip power consumption according to claim 1, characterized in that, The dynamic voltage and frequency control of the functional unit hardware module through the dynamic voltage and frequency control module includes: Assume the default state of the dynamic voltage and frequency regulation control module is idle. When it is determined that the functional unit hardware needs to adjust the voltage, the dynamic voltage and frequency adjustment control module enters the voltage adjustment state. When it is determined that the functional unit hardware needs to be frequency-adjusted but not voltage-adjusted, the dynamic voltage and frequency adjustment control module enters the frequency adjustment state. The operation of the dynamic voltage and frequency regulation control module is determined based on its status.

4. The control method for reducing chip power consumption according to claim 3, characterized in that, The step of determining the operation of the dynamic voltage and frequency regulation control module based on its state includes: When the dynamic voltage and frequency regulation control module is in an idle state, the dynamic voltage and frequency regulation control module queries the data table to determine whether voltage regulation and / or frequency regulation is required. When the dynamic voltage and frequency regulation control module is in the voltage regulation state, the dynamic voltage and frequency regulation control module initiates a voltage regulation request to the system voltage regulation module according to the demand. When it receives feedback that the voltage regulation failed, it enters the idle state. When it receives feedback that the voltage regulation was successful, it enters the delay state. When the dynamic voltage and frequency regulation control module is in the delay state, the dynamic voltage and frequency regulation control module performs voltage stabilization operation. When the dynamic voltage and frequency regulation control module is in frequency regulation state, the dynamic voltage and frequency regulation control module initiates a frequency regulation request to the system frequency regulation module.

5. A control device for reducing chip power consumption, characterized in that, The control device for reducing chip power consumption performs the method as described in any one of claims 1 to 4, comprising: The first module is used to detect the device status through the clock control module and determine the clock gating processing method based on the device status. The second module is used to control the clock control module to work according to the clock gating processing method; The third module is used to dynamically adjust the voltage and frequency of the functional unit hardware module through the dynamic voltage and frequency adjustment control module.

6. An electronic device, characterized in that, Including the processor and memory; The memory is used to store programs; The processor executes the program to implement the method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The storage medium stores a program that is executed by a processor to implement the method as described in any one of claims 1 to 4.

Images