Memory management method, memory storage device and memory control circuit unit

Abstract

The present application provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises: sending a sequence of erase instructions to indicate erasing a first physical erase unit in a rewritable non-volatile memory module; and sending a sequence of write instructions corresponding to the erasing of the first physical erase unit to indicate performing a padding write operation on a second physical erase unit in the rewritable non-volatile memory module. The padding write operation is used to store padding data into the second physical erase unit. Thus, the use efficiency of the physical erase unit can be improved.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a memory management method, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] Generally, each physical erase unit in a rewritable non-volatile memory module can be erased and written to independently. However, in practice, there may be some correlation between physical erase units A and B within the same rewritable non-volatile memory module. This correlation can cause write operations to physical erase unit B to easily fail after erasing physical erase unit A. Therefore, a solution is needed to address this issue. Summary of the Invention

[0004] This invention provides a memory management method, a memory storage device, and a memory control circuit unit, which can improve the efficiency of physical erasure units.

[0005] An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical erase units. The memory management method includes: sending an erase instruction sequence, wherein the erase instruction sequence is used to instruct the erasure of a first physical erase unit among the plurality of physical erase units; and corresponding to the erasure of the first physical erase unit, sending a write instruction sequence, wherein the write instruction sequence is used to instruct a fill write operation to be performed on a second physical erase unit among the plurality of physical erase units. The fill write operation is used to store fill data into the second physical erase unit.

[0006] In an exemplary embodiment of the present invention, the memory management method further includes: ignoring write failure events corresponding to the fill write operation after performing the fill write operation.

[0007] In one exemplary embodiment of the present invention, the filling data is not mapped by any logical unit.

[0008] In one exemplary embodiment of the present invention, during the fill write operation, the fill data is stored in an entity programming unit within the second entity erase unit.

[0009] In an exemplary embodiment of the present invention, the operation of sending the write instruction sequence corresponding to the erasure of the first entity erasure unit includes: corresponding to the erasure of the first entity erasure unit, caching the identification information corresponding to the second entity erasure unit; and sending the write instruction sequence according to the identification information before performing a normal write operation on the second entity erasure unit.

[0010] In one exemplary embodiment of the present invention, the second entity erasure unit includes at least a portion of the entity erasure units that are not fully written.

[0011] In an exemplary embodiment of the present invention, the memory management method further includes: corresponding to the erasure of the first entity erasure unit, reading identification information of at least one entity erasure unit associated with the first entity erasure unit from management information; and determining the second entity erasure unit from the plurality of entity erasure units based on the identification information.

[0012] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The rewritable non-volatile memory module includes a plurality of physical erase units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: send an erase instruction sequence, wherein the erase instruction sequence instructs the erasure of a first physical erase unit among the plurality of physical erase units; and, corresponding to the erasure of the first physical erase unit, send a write instruction sequence, wherein the write instruction sequence instructs a fill write operation to be performed on a second physical erase unit among the plurality of physical erase units, and the fill write operation is configured to store fill data in the second physical erase unit.

[0013] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: ignore write failure events corresponding to the fill write operation after performing the fill write operation.

[0014] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to send the write instruction sequence corresponding to the erasure of the first entity erasure unit includes: corresponding to the erasure of the first entity erasure unit, caching the identification information corresponding to the second entity erasure unit; and sending the write instruction sequence according to the identification information before performing a normal write operation on the second entity erasure unit.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: read identification information of at least one entity erasure unit associated with the first entity erasure unit from management information corresponding to the erasure of the first entity erasure unit; and determine the second entity erasure unit from the plurality of entity erasure units based on the identification information.

[0016] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical erase units. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used to: send an erase instruction sequence, wherein the erase instruction sequence is used to instruct the erasure of a first physical erase unit among the plurality of physical erase units; and corresponding to the erasure of the first physical erase unit, send a write instruction sequence, wherein the write instruction sequence is used to instruct a fill write operation to be performed on a second physical erase unit among the plurality of physical erase units, and the fill write operation is used to store fill data in the second physical erase unit.

[0017] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: ignore write failure events corresponding to the fill write operation after performing the fill write operation.

[0018] In an exemplary embodiment of the present invention, the operation of the memory management circuit to send the write instruction sequence corresponding to the erasure of the first entity erasure unit includes: corresponding to the erasure of the first entity erasure unit, caching the identification information corresponding to the second entity erasure unit; and sending the write instruction sequence according to the identification information before performing a normal write operation on the second entity erasure unit.

[0019] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: read identification information of at least one entity erasure unit associated with the first entity erasure unit from management information corresponding to the erasure of the first entity erasure unit; and determine the second entity erasure unit from the plurality of entity erasure units based on the identification information.

[0020] Based on the above, after erasing the first physical erase unit in the rewritable non-volatile memory module, a corresponding fill write operation can be performed to store the fill data into the second physical erase unit in the rewritable non-volatile memory module. Specifically, after performing the fill write operation, the second physical erase unit can be used normally without being affected by the erasure by the first physical erase unit. Therefore, the utilization efficiency of the physical erase unit can be effectively improved. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram illustrating the filling and writing operation performed on the second entity eraser unit after erasing the first entity eraser unit, as shown in an exemplary embodiment of the present invention.

[0028] Figure 8 This is a schematic diagram illustrating the normal write operation performed on the second entity erase unit after a fill write operation is performed on the second entity erase unit, as shown in an exemplary embodiment of the present invention.

[0029] Figure 9This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention;

[0030] Figure 10 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Detailed Implementation

[0031] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0032] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0033] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0034] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be connected to the system bus 110.

[0035] In one exemplary embodiment, the host system 11 buffers a data transfer interface 114 connected to a memory storage device 10. For example, the host system 11 buffers the data transfer interface 114 to store data in or read data from the memory storage device 10. Furthermore, the host system 11 buffers a system bus 110 connected to an I / O device 12. For example, the host system 11 buffers the system bus 110 to transmit output signals to or receive input signals from the I / O device 12.

[0036] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be located on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. By buffering the data transfer interfaces 114, the motherboard 20 may buffer wired or wireless connections to the memory storage device 10.

[0037] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also buffer system bus 110 connections to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may buffer wireless transmission device 207 access to the wireless memory storage device 204.

[0038] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0039] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0040] Please refer to Figure 3The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0041] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0042] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0043] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can buffer communication between the connection interface unit 41 and the host system 11. In one exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0044] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0045] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0046] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. Applying a write voltage to the control gate buffer changes the amount of electrons in the charge trapping layer, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. Applying a read voltage buffer determines which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0047] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0048] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a page or a sector. If the physical programming unit is a page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 sectors, and the size of one sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer sectors, and the size of each sector may be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a block.

[0049] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0050] Please refer to Figure 5The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to a description of the operation of the memory control circuit unit 42.

[0051] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0052] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0053] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0054] The host interface 52 is connected to the memory management circuitry 51. The memory management circuitry 51 buffers communication between the host interface 52 and the host system 11. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be buffered by the host interface 52 before being transmitted to the memory management circuitry 51. Furthermore, the memory management circuitry 51 can buffer the transmission of data from the host interface 52 to the host system 11. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the invention is not limited thereto, and the host interface 52 may also be compatible with SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0055] Memory interface 53 is connected to memory management circuitry 51 and used to access rewritable non-volatile memory module 43. For example, memory management circuitry 51 may buffer memory interface 53 to access rewritable non-volatile memory module 43. That is, data to be written to rewritable non-volatile memory module 43 is buffered and converted by memory interface 53 into a format acceptable to rewritable non-volatile memory module 43. Specifically, if memory management circuitry 51 needs to access rewritable non-volatile memory module 43, memory interface 53 transmits a corresponding sequence of instructions. For example, these sequence of instructions may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by memory management circuitry 51 and buffered by memory interface 53 to be transmitted to rewritable non-volatile memory module 43. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0056] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0057] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0058] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0059] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0060] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0061] Please refer to Figure 6 The memory management circuit 51 can logically group the physical erase units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. Each physical erase unit may include multiple physical programmable units.

[0062] The entity erasure units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 The user data of the host system 11). For example, entity erasure units 610(0) to 610(A) in storage area 601 may store valid data and / or invalid data. Entity erasure units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity erasure unit does not store valid data, this entity erasure unit may be associated (or added) to free area 602. In addition, entity erasure units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity erasure units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0063] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map entity erase units 610(0) to 610(A) in memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logical addresses.

[0064] It should be noted that a logical unit can be mapped to one or more entity erase units. If an entity erase unit is currently mapped to a logical unit, it means that the data currently stored in this entity erase unit includes valid data. Conversely, if an entity erase unit is not currently mapped to any logical unit, it means that the data currently stored in this entity erase unit is invalid data.

[0065] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and entity erasure units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0066] In one exemplary embodiment, memory management circuitry 51 may send an erase instruction sequence to rewritable non-volatile memory module 43. This erase instruction sequence may be used to instruct the rewritable non-volatile memory module 43 to erase a physical erase unit (also referred to as a first physical erase unit) to clear the data in the first physical erase unit. For example, the first physical erase unit may include… Figure 6 One of the entity erasure units 610(0) to 610(A) in the storage area 601.

[0067] Corresponding to (or in response to) the erasure of the first physical erase unit, the memory management circuit 51 may send a write instruction sequence to the rewritable non-volatile memory module 43. This write instruction sequence instructs the rewritable non-volatile memory module 43 to perform a dummy write operation on another physical erase unit (also referred to as a second physical erase unit). Specifically, this dummy write operation can be used to store dummy data into the second physical erase unit. The total number of second physical erase units may be one or more.

[0068] In one exemplary embodiment, the padding data is not mapped to any logical unit. That is, the padding data does not include any valid data. For example, the padding data may include a series of meaningless bits (e.g., a series of bits "0" or "1") or consist of such meaningless bits.

[0069] In one exemplary embodiment, during the fill write operation, the fill data is stored in one of the entity programmable units within the second entity erase unit. For example, the fill data may be stored in a first entity programmable unit within the second entity erase unit that is not yet used or is about to be used. Furthermore, in one exemplary embodiment, the fill data may also be stored in multiple entity programmable units within the second entity erase unit that are not yet used or are about to be used; this is not a limitation of the invention.

[0070] In one exemplary embodiment, after performing the fill write operation, the memory management circuit 51 may ignore the write failure event corresponding to the fill write operation. For example, the write failure event corresponding to the fill write operation may reflect that the fill write operation failed. Alternatively, even if the fill write operation fails, the memory management circuit 51 may not perform any related error handling for the write failure event.

[0071] In one exemplary embodiment, the memory management circuit 51 can also perform normal write operations. For example, a normal write operation can be used to transfer data from... Figure 1 The host system 11 stores data in a rewritable non-volatile memory module 43. In one exemplary embodiment, when a write failure event corresponding to a normal write operation is received, the memory management circuit 51 may perform error handling for the write failure event. For example, this error handling may include correctly restoring the data to a preset memory address or reporting a write failure message to the host system 11. Figure 1 The host system 11, etc.

[0072] Figure 7 This is a schematic diagram illustrating the filling and writing operation performed on the second entity eraser unit after erasing the first entity eraser unit, as shown in an exemplary embodiment of the present invention.

[0073] Please refer to Figure 7 After an erase operation is performed on entity erase unit 71 (i.e., the first entity erase unit), a fill write operation can be performed on entity erase unit 72 (i.e., the second entity erase unit) in response to this erase operation. For example, assuming that entity programming units 701(0) to 701(N) in entity erase unit 72 already have stored data (e.g., valid data), then the first entity programming unit in entity erase unit 72 that has not yet been used or is about to be used is entity programming unit 701(N+1). Therefore, in the fill write operation on entity erase unit 72, fill data can be written to entity programming unit 701(N+1).

[0074] In particular, even if the data write operation (i.e., the fill write operation) to the physical programming unit 701 (N+1) fails, the memory management circuit 51 can ignore the write failure event corresponding to the physical programming unit 701 (N+1) or the fill write operation. Alternatively, from another perspective, regardless of whether the data write operation (i.e., the fill write operation) to the physical programming unit 701 (N+1) is successful or not, the memory management circuit 51 will not perform error handling procedures such as rewriting data for the physical programming unit 701 (N+1) or the fill data.

[0075] In one exemplary embodiment, after the fill write operation is performed on the second physical erase unit, the memory management circuit 51 may send another write instruction sequence to the rewritable non-volatile memory module 43. This write instruction sequence is used to instruct the rewritable non-volatile memory module 43 to perform a normal write operation on the second physical erase unit. For example, this normal write operation can be used to write normal data (e.g., from...) to the second physical erase unit. Figure 1 The data of the host system 11 is stored in the second entity erasure unit.

[0076] Figure 8 This is a schematic diagram illustrating the normal write operation performed on the second entity erase unit after a fill write operation is performed on the second entity erase unit, as shown in an exemplary embodiment of the present invention.

[0077] Please refer to Figure 8 , continuing Figure 7 In an exemplary embodiment, after a padding write operation is performed on entity erase unit 72 to write padding data to entity programming unit 701 (N+1), a normal write operation can be performed regardless of whether the data write operation (i.e., the padding write operation) on entity programming unit 701 (N+1) was successful. This normal write operation can be used to write normal data (e.g., from...) Figure 1 The data of the host system 11 is written to the first entity programming unit in the entity erasure unit 72 that has not yet been used or is about to be used.

[0078] by Figure 8 For example, after attempting to write padding data to entity programming unit 701 (N+1), even if the write operation to entity programming unit 701 (N+1) fails, the next piece of data (i.e., normal data) can still be normally stored in entity programming unit 701 (N+2). Furthermore, more data can be subsequently stored in other entity programming units in entity erasure unit 72 that are not yet used or are about to be used, unaffected by the write status of padding data in entity programming unit 701 (N+1) (e.g., a write failure status).

[0079] In one exemplary embodiment, after each erase operation on the first physical erase unit, the memory management circuit 51 instructs the second physical erase unit to perform the fill write operation. However, in another exemplary embodiment, after the erase operation on the first physical erase unit, the memory management circuit 51 may temporarily refrain from performing the fill write operation on the second physical erase unit until new data (i.e., normal data) needs to be stored in the second physical erase unit.

[0080] In one exemplary embodiment, after an erasure operation is performed on the first entity erasure unit, the memory management circuit 51 may cache identification information corresponding to the second entity erasure unit in relation to the erasure of the first entity erasure unit. For example, this identification information may be stored in... Figure 5 The information is stored in the buffer memory 55. For example, this identification information may include the number, address information, or other information that can be used to identify the second entity erase unit. Before a normal write operation is required to store new data on the second entity erase unit, the memory management circuit 51 may temporarily refrain from performing the fill write operation on the second entity erase unit.

[0081] In one exemplary embodiment, after determining that a normal write operation needs to be performed on the second entity erase unit to store new data (e.g., after receiving a message from...), Figure 1 After receiving the write instruction from the host system 11, before performing a normal write operation on the second physical erase unit, the memory management circuit 51 can first send a corresponding write instruction sequence according to the identification information to instruct the rewritable non-volatile memory module 43 to perform the fill write operation on the second physical erase unit. After performing the fill write operation, the memory management circuit 51 can then send another write instruction sequence to instruct the second physical erase unit to perform the normal write operation. This avoids the situation where multiple fill data entries are continuously stored in the second physical erase unit before the new data is stored there, due to the first physical erase unit being erased multiple times. For operational details regarding the normal write operation, please refer to [reference needed]. Figure 8 Examples and implementations are not elaborated here.

[0082] In one exemplary embodiment, cached in Figure 5 The identification information in the buffer memory 55 may be lost when the memory storage device 10 is turned off or powered off. Therefore, after the memory storage device 10 is turned on or powered on again, the memory management circuit 51 may not perform the fill write operation on the second physical erase unit.

[0083] In one exemplary embodiment, if the memory storage device 10 is restarted or powered on again after an erase operation is performed on the first physical erase unit, the erase operation may not affect the data write operation of the second physical erase unit after the restart or power-on. Therefore, even if cached in Figure 5 The identification information in the buffer memory 55 disappears when the memory storage device 10 is turned off or powered off, but this does not affect the subsequent data writing performance of the second entity erasure unit.

[0084] In one exemplary embodiment, the second physical erase unit may include at least partially unwritten physical erase units in the rewritable non-volatile memory module 43. In one exemplary embodiment, the unwritten physical erase units are also referred to as open units or open blocks. In one exemplary embodiment, the second physical erase unit may include all unwritten physical erase units in the rewritable non-volatile memory module 43. In one exemplary embodiment, the second physical erase unit may also include one or more physical erase units in the rewritable non-volatile memory module 43 that have not yet been written with data (e.g., valid data).

[0085] In one exemplary embodiment, the second physical erase unit (only) includes physical erase units in the rewritable non-volatile memory module 43 that have some association with the first physical erase unit. For example, this association may reflect that after an erase operation is performed on the first physical erase unit, a data write operation to the second physical erase unit has a high probability (or even 100%) of failure.

[0086] In one exemplary embodiment, corresponding to the erasure of the first physical erasure unit, the memory management circuit 51 can read the identification information of at least one physical erasure unit associated with the first physical erasure unit from management information. For example, the management information may record the identification information of at least one physical erasure unit associated with the first physical erasure unit. For example, this management information may be stored in the system area of ​​the rewritable non-volatile memory module 43 to prevent modification by the user. The memory management circuit 51 can determine the second physical erasure unit from among the multiple physical erasure units in the rewritable non-volatile memory module 43 based on the obtained identification information.

[0087] In one exemplary embodiment, after an erasure operation is performed on a first physical eraser unit, if a data write operation performed on a certain physical eraser unit has a high probability (or even 100%) of failure, then this physical eraser unit can be considered associated with the first physical eraser unit. The memory management circuit 51 can record the identification information of the physical eraser units associated with the first physical eraser unit in the management information. Subsequently, after an erasure operation is performed on the first physical eraser unit, the memory management circuit 51 can determine, based on the management information, to perform a fill write operation on a specific physical eraser unit (i.e., the second physical eraser unit). In particular, after a fill write operation is performed on the second physical eraser unit, the second physical eraser unit can be used to store data normally, no longer affected by the erasure of the first physical eraser unit.

[0088] Figure 9 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention.

[0089] Please refer to Figure 9 In step S901, an erase command sequence is sent, wherein the erase command sequence is used to instruct the erasure of a first physical erase unit in the rewritable non-volatile memory module. In step S902, corresponding to the erasure of the first physical erase unit, a write command sequence is sent, wherein the write command sequence is used to instruct a fill write operation to be performed on a second physical erase unit in the rewritable non-volatile memory module. In particular, the fill write operation is used to store fill data into the second physical erase unit.

[0090] Figure 10 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention.

[0091] Please refer to Figure 10 In step S1001, an erase instruction sequence is sent, wherein the erase instruction sequence is used to instruct the erasure of the first physical erase unit in the rewritable non-volatile memory module. In step S1002, corresponding to the erasure of the first physical erase unit, the identification information corresponding to the second physical erase unit is cached. In step S1003, it is determined whether a normal write operation needs to be performed on the second physical erase unit. If (or in response to) the normal write operation on the second physical erase unit is not required temporarily, step S1003 can be repeated.

[0092] On the other hand, if (or in response to) the need to perform a normal write operation on the second entity erase unit to store data, in step S1004, a write instruction sequence is sent according to the cached identification information, wherein the write instruction sequence is used to instruct the second entity erase unit to perform a fill write operation. After performing the fill write operation, regardless of whether the fill write operation is successful, in step S1005, a write instruction sequence is sent, wherein the write instruction sequence is used to instruct the second entity erase unit to perform a normal write operation. It should be noted that... Figure 9 and Figure 10 The exemplary embodiments can be matched with Figure 7 and Figure 8 The following are exemplary embodiments for implementation, and the relevant details will not be elaborated here.

[0093] However, Figure 9 and Figure 10 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 9 and Figure 10 Each step can be implemented as multiple pieces of code or circuits; this application does not impose any restrictions. Furthermore, Figure 9 and Figure 10 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this case does not impose any restrictions.

[0094] In summary, the memory management method, memory storage device, and memory control circuit unit provided in this embodiment of the invention can perform a fill-write operation on a second physical eraser associated with the first physical eraser after an erase operation is performed on the first physical eraser. Specifically, after the fill-write operation is performed, the second physical eraser can be used normally without being affected by the erase operation of the first physical eraser. Therefore, the utilization efficiency of the physical eraser can be effectively improved.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical erasure units, and the memory management method includes: Sending an erase command sequence, wherein the erase command sequence is used to instruct the erasure of a first entity erase unit among the plurality of entity erase units; and Before performing a normal write operation on the second entity erase unit associated with the first entity erase unit among the plurality of entity erase units, a write instruction sequence is sent corresponding to the erasure of the first entity erase unit, wherein the write instruction sequence is used to instruct the second entity erase unit to perform a fill write operation, and The fill write operation is used to store the fill data into the second entity erase unit, and the fill data is not mapped by any logical unit.

2. The memory management method according to claim 1 further includes: After performing the fill write operation, write failure events corresponding to the fill write operation are ignored.

3. The memory management method according to claim 1, wherein in the fill write operation, the fill data is stored in an entity programmable unit of the second entity erase unit.

4. The memory management method according to claim 1, wherein the operation of sending the write instruction sequence corresponding to the erasure of the first entity erasure unit includes: Corresponding to the erasure by the first entity erasure unit, the identification information corresponding to the second entity erasure unit is cached; as well as Before performing a normal write operation on the second entity erasure unit, the write instruction sequence is sent according to the identification information.

5. The memory management method according to claim 1, wherein the second entity erase unit includes at least a portion of the entity erase units that are not fully written.

6. The memory management method according to claim 1, further comprising: Corresponding to the erasure by the first entity erasure unit, the identification information of at least one entity erasure unit associated with the first entity erasure unit is read from the management information; and The second entity erasure unit is determined from the plurality of entity erasure units based on the identification information.

7. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical erasure units; as well as The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Sending an erase command sequence, wherein the erase command sequence is used to instruct the erasure of a first entity erase unit among the plurality of entity erase units; and Before performing a normal write operation on the second entity erase unit associated with the first entity erase unit among the plurality of entity erase units, a write instruction sequence is sent corresponding to the erasure of the first entity erase unit, wherein the write instruction sequence is used to instruct the second entity erase unit to perform a fill write operation, and The fill write operation is used to store the fill data into the second entity erase unit, and the fill data is not mapped by any logical unit.

8. The memory storage device according to claim 7, wherein the memory control circuit unit is further configured to: After performing the fill write operation, write failure events corresponding to the fill write operation are ignored.

9. The memory storage device of claim 7, wherein in the fill write operation, the fill data is stored in an entity programming unit of the second entity erase unit.

10. The memory storage device of claim 7, wherein the operation of the memory control circuit unit sending the write instruction sequence corresponding to the erasure of the first physical erasure unit includes: Corresponding to the erasure by the first entity erasure unit, the identification information corresponding to the second entity erasure unit is cached; as well as Before performing a normal write operation on the second entity erasure unit, the write instruction sequence is sent according to the identification information.

11. The memory storage device of claim 7, wherein the second physical erase unit comprises at least a portion of the plurality of physical erase units that are not fully written.

12. The memory storage device according to claim 7, wherein the memory control circuit unit is further configured to: Corresponding to the erasure by the first entity erasure unit, identification information of at least one entity erasure unit associated with the first entity erasure unit is read from the management information; and The second entity erasure unit is determined from the plurality of entity erasure units based on the identification information.

13. A memory control circuit unit, characterized in that, This is used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical erase units, and the memory control circuit unit includes: Host interface, used to connect to the host system; A memory interface for connecting to the rewritable non-volatile memory module; and The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: Sending an erase command sequence, wherein the erase command sequence is used to instruct the erasure of a first entity erase unit among the plurality of entity erase units; and Before performing a normal write operation on the second entity erase unit associated with the first entity erase unit among the plurality of entity erase units, a write instruction sequence is sent corresponding to the erasure of the first entity erase unit, wherein the write instruction sequence is used to instruct the second entity erase unit to perform a fill write operation, and The fill write operation is used to store the fill data into the second entity erase unit, and the fill data is not mapped by any logical unit.

14. The memory control circuit unit according to claim 13, wherein the memory management circuit is further configured to: After performing the fill write operation, write failure events corresponding to the fill write operation are ignored.

15. The memory control circuit unit of claim 13, wherein in the fill write operation, the fill data is stored in an entity programming unit of the second entity erase unit.

16. The memory control circuit unit of claim 13, wherein the operation of the memory management circuit sending the write instruction sequence corresponding to the erasure of the first physical erasure unit includes: Corresponding to the erasure by the first entity erasure unit, the identification information corresponding to the second entity erasure unit is cached; as well as Before performing a normal write operation on the second entity erasure unit, the write instruction sequence is sent according to the identification information.

17. The memory control circuit unit of claim 13, wherein the second physical erase unit includes at least a portion of the plurality of physical erase units that are not fully written.

18. The memory control circuit unit according to claim 13, wherein the memory management circuit is further configured to: Corresponding to the erasure by the first entity erasure unit, identification information of at least one entity erasure unit associated with the first entity erasure unit is read from the management information; and The second entity erasure unit is determined from the plurality of entity erasure units based on the identification information.

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