Memory device and method of operating a memory device

Abstract

Embodiments of the present invention disclose a memory device and a method of operating a memory device. Embodiments disclosed herein relate to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell for storing data. In one aspect, the memory device includes an output driver configured to generate an output signal indicative of the stored data in response to a sleep tracking signal indicating that the memory cell is in an operational state, and to generate an output signal having a predetermined voltage independent of the stored data in response to the sleep tracking signal indicating that the memory cell is in a sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal, causing the memory cell to operate in either the sleep state or the operational state.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory devices and methods for operating memory devices. Background Technology

[0002] The development of electronic devices such as computers, portable devices, smartphones, and Internet of Things (IoT) devices has driven increased demand for memory devices. Typically, memory devices can be volatile or non-volatile. Volatile memory devices can store data while powered on, but may lose the stored data once power is off. Unlike volatile memory devices, non-volatile memory devices retain data even after power is turned off, but may be slower than volatile memory devices. Summary of the Invention

[0003] According to one aspect of an embodiment of the present invention, a memory device is provided, comprising: a memory cell for storing data; and an output driver coupled to the memory cell, the output driver being configured to: generate an output signal indicating stored data in response to a sleep tracking signal indicating that the memory cell is in an operating state, and generate an output signal having a predetermined voltage independent of the stored data in response to a sleep tracking signal indicating that the memory cell is in a sleep state, wherein the sleep tracking signal is delayed from a sleep control signal that causes the memory cell to operate in a sleep state or an operating state.

[0004] According to another aspect of the present invention, a memory device is provided, comprising: a memory cell for storing data; a delay circuit configured to: receive a sleep tracking signal indicating whether the memory cell is in a sleep state or an operating state, and delay the sleep tracking signal to obtain a delayed sleep tracking signal; and a wake-up detection circuit coupled to the delay circuit, the wake-up detection circuit generating a wake-up completion signal based on the delayed sleep tracking signal, indicating whether the memory cell has completed transitioning from a sleep state to an operating state.

[0005] According to another aspect of the present invention, a method for operating a memory device is provided, comprising: generating a sleep control signal by a controller to cause a memory cell to transition from a sleep state to an operating state at a first time; detecting by the controller that the memory cell has transitioned from a sleep state to an operating state at a second time after the first time; coupling an output driver to the memory cell by the controller to maintain an output signal having a predetermined voltage independent of the data stored in the memory cell until the second time; and generating an output signal indicating the data stored in the memory cell after the second time by the controller. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic block diagram of an example memory device according to some embodiments is shown.

[0008] Figure 2 The illustration shows a schematic block diagram of an example memory device including circuitry for performing a wake-up sequence according to some embodiments.

[0009] Figure 3 The illustrations depict some embodiments. Figure 2 A schematic diagram of the memory controller portion of the system.

[0010] Figure 4 The illustration shows a timing diagram of a wake-up sequence for a memory device according to some embodiments.

[0011] Figure 5 The illustrations depict some embodiments. Figure 2 A schematic diagram of the memory controller portion of the system.

[0012] Figure 6 The diagram illustrates a power detection circuit according to some embodiments.

[0013] Figure 7 The illustration shows a timing diagram of a wake-up sequence for a memory device according to some embodiments.

[0014] Figure 8 The illustrations depict some embodiments. Figure 2 A schematic diagram of the memory controller portion of the system.

[0015] Figures 9A to 9D A schematic diagram of a delay circuit according to some embodiments is shown.

[0016] Figure 10 The illustrations depict some embodiments. Figure 2 A schematic diagram of the memory controller portion of the system.

[0017] Figure 11 This is a flowchart illustrating a method for performing a wake-up sequence by a memory device according to some embodiments.

[0018] Figure 12 This is an example block diagram of a computing system according to some embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0021] The disclosure herein relates to reducing power consumption of a memory device during transition from a sleep state to an operating state. In one aspect, the memory device includes memory cells for storing data. In another aspect, the memory device includes an output driver configured to: generate an output signal indicating stored data in response to a sleep tracking signal indicating that the memory cell is in an operating state, and generate an output signal having a predetermined voltage independent of the stored data in response to a sleep tracking signal indicating that the memory cell is in a sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal that causes the memory cell to enter a sleep state or an operating state.

[0022] Advantageously, the memory device can reduce power consumption when transitioning from a sleep state to an operating state. In one aspect, the controller can generate a sleep control signal that causes a memory cell to enter a sleep state or an operating state. In response to the sleep control signal, the memory cell can correspondingly enter a sleep state or an operating state. In one aspect, the sleep control signal is propagated through multiple buffer circuits to cause a set of memory cells to enter a sleep state or an operating state. For example, a first buffer circuit can receive the sleep control signal and generate a first delayed control signal to configure a first subset of the set of memory cells in a sleep state or an operating state. Each remaining buffer circuit can receive a delayed control signal from the preceding buffer circuit and generate a corresponding delayed control signal to configure a corresponding subset of the set of memory cells in a sleep state or an operating state. The sleep control signal propagated through the last buffer circuit of the set of buffer circuits can be a sleep tracking signal indicating whether the transition of the set of memory cells from a sleep state to an operating state is complete. Due to the capacitive load of the memory cells and / or the number of buffer circuits, the sleep tracking signal may be delayed relative to the sleep control signal. In one aspect, by enabling the output driver to generate an output signal with a predetermined voltage in response to a sleep control signal, the power consumption of the output driver can be reduced or eliminated when the memory cells do not sufficiently transition from sleep to operation.

[0023] In one aspect, the memory device includes a delay circuit to delay a sleep tracking signal. The memory device may also include a wake-up detection circuit coupled to the delay circuit. The wake-up detection circuit may generate a wake-up completion signal based on the delayed sleep tracking signal, indicating whether the transition of the memory cell from a sleep state to an operating state is complete. For example, in response to a delayed sleep tracking signal having a high voltage (e.g., 1V) indicating that the memory cell is in a sleep state, the wake-up completion signal may have a high voltage (e.g., 1V) to indicate that the transition of the memory cell from a sleep state to an operating state is not complete. Conversely, in response to a delayed sleep tracking signal having a low voltage (e.g., 0V) or a logic value "0" indicating that the memory cell is in an operating state, the wake-up completion signal may have a low voltage (e.g., 0V) to indicate that the transition of the memory cell from a sleep state to an operating state is not complete.

[0024] In one aspect, the memory device includes a power supply detection circuit configured to detect an internal supply voltage provided to one or more circuits in an output driver and generate a power supply detection signal voltage indicating whether the internal supply voltage has reached a threshold voltage. A wake-up detection circuit may further generate a wake-up completion signal based on the power supply detection signal. For example, in response to a power supply detection signal with a high voltage (e.g., 1V) indicating that the internal supply voltage has not yet reached the threshold voltage, the wake-up completion signal may have a high voltage (e.g., 1V) to indicate that the transition from a sleep state to an operating state of the memory cell is not yet complete. Conversely, in response to a power supply detection signal with a low voltage (e.g., 0V) indicating that the internal supply voltage has reached the threshold voltage, the wake-up completion signal may have a low voltage (e.g., 0V) to indicate that the transition from a sleep state to an operating state of the memory cell is complete.

[0025] Advantageously, the wake-up detection circuit can accurately generate a wake-up completion signal when the memory cell and output driver have transitioned from a sleep state to an operating state. In one aspect, the internal supply voltage provided to one or more circuits of the output driver can change in response to a sleep control signal. For example, when the output driver is in a sleep state, the internal supply voltage can be set to a first voltage (e.g., 0V), while when the output driver is in an operating state, the internal supply voltage can be set to a second voltage (e.g., 1V). Due to capacitive load, changes in the internal supply voltage may be delayed relative to changes in the sleep control signal. By having the wake-up detection circuit generate the wake-up completion signal based on a delayed sleep tracking signal and / or a power supply detection signal, the wake-up completion signal can be accurately generated when the internal supply voltage reaches a sufficient voltage to make the output driver operable. Therefore, premature operations such as reading data stored in the memory cell can be avoided before the memory cell and output driver have sufficiently transitioned from a sleep state to an operating state, allowing the memory device to operate reliably with reduced power consumption.

[0026] In some embodiments, one or more components may be implemented as one or more transistors. Transistors in this disclosure are shown as having a specific type (N-type or P-type), but embodiments are not limited thereto. A transistor may be any suitable type of transistor, including but not limited to metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, FinFETs, planar MOS transistors with raised source / drain electrodes, nanosheet FETs, nanowire FETs, etc. Furthermore, one or more transistors shown or described herein may be implemented as two or more transistors connected in parallel.

[0027] Figure 1This is a schematic diagram of a memory device 100 according to one embodiment. In some embodiments, the memory device 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to a corresponding word line WL and a corresponding bit line BL. The memory controller 105 may write data to or read data from the memory array 120 according to electrical signals through the word line WL and the bit line BL. In other embodiments, the memory device 100 includes a... Figure 1 Show more, fewer, or different components.

[0028] Memory array 120 is a hardware component for storing data. In one aspect, memory array 120 is implemented as a semiconductor memory device. Memory array 120 includes a plurality of storage circuits or memory cells 125. Memory array 120 includes word lines WL0, WL1…WLJ, each extending in a first direction (e.g., the X direction), and bit lines BL0, BL1…BLK, each extending in a second direction (e.g., the Y direction). Word lines WL and bit lines BL can be conductive metal or conductive rails. In one aspect, each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and can be operated according to a voltage or current passing through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes a bit line BL, BLB coupled to one or more memory cells 125 in a group of memory cells 125 disposed along the second direction (e.g., the Y direction). Bit lines BL, BLB can receive and / or provide differential signals. Each memory cell 125 may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, each memory cell 125 is implemented as a static random access memory (SRAM) cell or other type of memory cell. In some embodiments, the memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0029] Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes bit line controller 112, word line controller 114, and master controller 110. Bit line controller 112, word line controller 114, and master controller 110 may be implemented as logic circuitry, analog circuitry, or a combination thereof. In one configuration, word line controller 114 is circuitry that provides voltage or current through one or more word lines WL of memory array 120, and bit line controller 112 is circuitry that provides or senses voltage or current through one or more bit lines BL of memory array 120. In one configuration, master controller 110 is circuitry that provides control signals or clock signals to synchronize the operation of bit line controller 112 and word line controller 114. In some embodiments, master controller 110 is implemented as or includes a processor and a non-transitory computer-readable medium storing instructions that, when executed by the processor, cause the processor to perform one or more functions of master controller 110 or memory controller 105 described herein. Bit line controller 112 may be coupled to bit line BL of memory array 120, and word line controller 114 may be coupled to word line WL of memory array 120. In some embodiments, memory controller 105 includes more, fewer, or different... Figure 1 The components shown.

[0030] In one example, the master controller 110 may generate control signals to coordinate the operation of the bit line controller 112 and the word line controller 114. For example, the master controller 110 may generate one or more enable signals to enable or disable operation. In one method, to write data to memory cell 125, the master controller 110 may cause the word line controller 114 to apply a voltage or current to memory cell 125 through word line WL coupled to memory cell 125, and cause the bit line controller 112 to apply a voltage or current corresponding to the data to be stored in memory cell 125 through bit line BL coupled to memory cell 125. In one method, to read data from memory cell 125, the master controller 110 may cause the word line controller 114 to apply a voltage or current to memory cell 125 through word line WL coupled to memory cell 125, and cause the bit line controller 112 to sense a voltage or current corresponding to the data stored in memory cell 125 through bit line BL coupled to memory cell 125.

[0031] In some embodiments, the main controller 110 includes a sleep control circuit 175 and a wake-up detection circuit 185. Through these components, the main controller 110 can execute a wake-up sequence and report the status of the memory device 100.

[0032] The sleep control circuit 175 is a circuit that generates a sleep control signal to cause one or more components of the memory cell 125 and the memory controller 105 (e.g., bit line controller 112 and word line controller 114) to enter a sleep state (also referred to as a "power management state") or an operational state. For example, a sleep control signal with a first voltage (e.g., 0V) can cause one or more components of the memory controller 105 (e.g., bit line controller 112 and word line controller 114) to enter an operational state. For example, a sleep control signal with a second voltage (e.g., 1V) can cause one or more components of the memory controller 105 (e.g., bit line controller 112 and word line controller 114) to enter a sleep state. In the sleep state, the memory cell 125 and one or more components of the memory controller 105 can be powered down or can consume less power than in the operational state. In the operational state, the memory cell 125 and one or more components of the memory controller 105 can be fully operated to support reading or writing data and can consume more power than in the sleep state.

[0033] The wake-up detection circuit 185 is a circuit that generates a wake-up completion signal, indicating whether the wake-up sequence has been completed. In one aspect, the wake-up detection circuit 185 can receive a sleep tracking signal. The sleep tracking signal can be a signal that tracks the state of a group of memory cells 125. For example, the sleep tracking signal can indicate whether the group of memory cells 125 is in a sleep state or an operating state. Based on the sleep tracking signal, the wake-up detection circuit 185 can determine whether the wake-up sequence has been completed and generate a wake-up completion signal accordingly. Based on the wake-up completion signal, the memory device 100 can perform various operations. For example, in response to a wake-up completion signal indicating that the memory cell 125 has not yet completed the wake-up sequence, the memory device 100 may not perform a read or write operation. For example, in response to a wake-up completion signal indicating that the memory cell 125 has completed the wake-up sequence, the memory device 100 can perform a read or write operation. The following describes... Figures 2 to 11 A detailed description of the implementation and operation of the wake-up detection circuit 185 is provided.

[0034] Figure 2 The illustration shows a schematic block diagram of an example memory device 100 including circuitry for performing a wake-up sequence according to some embodiments. In some embodiments, the memory device 100 includes a memory controller 105 disposed below a memory array 120.

[0035] In some embodiments, the memory array 120 may be divided into regions, and each region may be configured individually or independently. In one example, the memory array 120 may be divided into a top region and a bottom region. The memory array 120 may include an interface circuit 215A that receives a top control signal TOP and a clock signal ICLK from the memory controller 105, and operates the memory cells 125 in the top region of the memory array 120 according to the top control signal TOP and the clock signal ICLK. The memory array 120 may include an interface circuit 215B that receives a bottom control signal BOT and a clock signal ICLK from the memory controller 105, and operates the memory cells 125 in the bottom region of the memory array 120 according to the bottom control signal BOT and the clock signal ICLK.

[0036] In one aspect, interface circuits 215A and 215B receive a sleep control signal SLP or a delayed version of the sleep control signal SLP from memory controller 105, and change the state of memory cell 125 according to the sleep control signal SLP. The sleep control signal can be a signal that causes memory cell 125 to enter a sleep state or an operating state. For example, memory array 120 includes buffer circuits 245A...245C for propagating the sleep control signal SLP. Buffer circuits 245A...245C can be cascaded to propagate the sleep control signal SLP. Each buffer circuit 245 can delay the sleep control signal or a delayed sleep control signal, thereby allowing the corresponding region of the memory cell to be controlled individually or independently. Instead of configuring the state of a large set of memory cells simultaneously, configuring the state of a subset or region of memory cells according to the delayed control signal can help prevent a large current from passing through the set of memory cells in a short period of time to protect the memory cells. In one configuration, interface circuit 215B receives the sleep control signal SLP and causes memory cell 125 in the left portion 205A of the bottom region to enter a sleep state or an operating state according to the sleep control signal SLP. Buffer circuit 245A can delay the sleep control signal SLP to obtain a first delayed signal 208A. Interface circuit 215B can receive the first delayed signal 208A and, based on the first delayed signal 208A, cause the memory cell 125 in the right portion 205B of the bottom region to enter a sleep state or an operating state. Buffer circuit 245B can delay the first delayed signal 208A to obtain a second delayed signal 208B. Interface circuit 215A can receive the second delayed signal 208B and, based on the second delayed signal 208B, cause the memory cell 125 in the left portion 205C of the top region to enter a sleep state or an operating state. Buffer circuit 245C can delay the second delayed signal 208B to obtain a sleep tracking signal SLP_TRK. Interface circuit 215A can receive the sleep tracking signal SLP_TRK and, based on the sleep tracking signal SLP_TRK, cause the memory cell 125 in the right portion 205D of the top region to enter a sleep state or an operating state. In one aspect, the sleep tracking signal SLP_TRK is the last delayed signal of the sleep control signal SLP propagated through buffer circuits 245A…245C. Although in Figure 2 Three buffer circuits 245A…245C are shown, but memory device 100 may include a different number of buffer circuits 245.

[0037] In some embodiments, the memory controller 105 includes a sleep control circuit 175, wake-up detection circuits 185A and 185B, a decoder 230, output drivers 280A and 280B, and delay circuits 290A, 290B, 295A, 295B, and 292. These components can operate together to configure the state of the memory array 120 and generate signals that report the state of the memory array 120. In some embodiments, the memory controller 105 includes a... Figure 2 Show more, fewer, or different components.

[0038] In some embodiments, decoder 230 is, for example, a component that receives a clock signal CLK, an enable signal CEB, and an address signal ADR[N:0] from a host device or processor, and accordingly generates a clock signal ICLK, a top control signal TOP, and a bottom control signal BOT. In some embodiments, decoder 230 may be replaced by different components that can perform the functions of decoder 230 disclosed herein. For example, decoder 230 may generate a clock signal ICLK with pulses of clock signal CLK in response to enable signal CEB, enabling clock signal ICLK to be provided to a top region or a bottom region. Decoder 230 may select a top region or a bottom region based on address signal ADR[N:0], and thereby generate top control signal TOP or bottom control signal BOT. For example, in response to address signal ADR[N:0] indicating a top region of a memory cell, decoder 230 may generate top control signal TOP to enable clock signal ICLK to be provided to the top region of the memory cell. For example, in response to the address signal ADR[N:0] indicating the bottom region of the memory cell, the decoder 230 can generate a bottom control signal BOT to enable the clock signal ICLK to be provided to the bottom region of the memory cell.

[0039] In some embodiments, the sleep control circuit 175 receives a signal DSLP and a signal SD, and generates a sleep control signal SLP based on the signals DSLP and SD. The signals DSLP and SD can be signals used to configure the memory device 100 into a sleep state or an operating state. The signal DSLP can be provided from a first device (e.g., a processor or an external host device), while the signal SD can be provided from a second device (e.g., a controller or an internal device). The sleep control circuit 175 can be implemented as an OR gate. The sleep control circuit 175 can perform an OR operation on the signals DSLP and SD to generate the sleep control signal SLP. For example, the sleep control circuit 175 can generate a sleep control signal SLP with a high voltage (e.g., 1V) in response to either the signal DSLP or the signal SD having a high voltage (e.g., 1V). For example, the sleep control circuit 175 can generate a sleep control signal SLP with a low voltage (e.g., 0V) in response to both the signals DSLP and SD having a low voltage (e.g., 0V). In some embodiments, the sleep control circuit 175 may be replaced by different components that can perform the functions of the sleep control circuit 175 disclosed herein.

[0040] In some embodiments, delay circuits 290A, 290B, and 292 are circuits that delay the sleep tracking signal SLP_TRK. Each of delay circuits 290A, 290B, and 292 may include an even number of inverter circuits, one or more amplifier circuits, one or more buffer circuits, one or more resistor delay circuits, adjustable delay circuits, or any delay circuit. Delay circuit 290A may delay the sleep tracking signal SLP_TRK to obtain a delayed signal SLPQ_TRK_LEFT and provide the delayed signal SLPQ_TRK_LEFT to output driver 280A. Delay circuit 290A may operate as a buffer between buffer circuit 245C and output driver 280A to reduce capacitive load at the output of buffer circuit 245C. Similarly, delay circuit 290B may delay the sleep tracking signal SLP_TRK to obtain a delayed signal SLPQ_TRK_RIGHT and provide the delayed signal SLPQ_TRK_RIGHT to output driver 280B. The delay circuit 290B can operate as a buffer between the buffer circuit 245C and the output driver 280B to reduce the capacitive load at the output of the buffer circuit 245C. In some embodiments, the delay circuit 292 receives the delay signal SLPQ_TRK_RIGHT and the delay signal SLPQ_TRK_RIGHT to obtain the delay signal SLPQ_TRKR. The delay circuit 292 can provide the delay signal SLPQ_TRKR to the wake-up detection circuits 185A and 185B. In some embodiments, the delay circuit 292 can receive the delay signal SLPQ_TRK_LEFT (instead of the delay signal SLPQ_TRK_RIGHT) and delay the delay signal SLPQ_TRK_LEFT to obtain the delay signal SLPQ_TRKR.

[0041] In some embodiments, delay circuits 295A and 295B are circuits that delay the sleep control signal SLP. Delay circuit 295A can delay the sleep control signal SLP to obtain a delayed signal SLPQ_LEFT, and provide the delayed signal SLPQ_LEFT to the output driver 280A. Delay circuit 295A can operate as a buffer between the sleep control circuit 175 and the output driver 280A to reduce the capacitive load at the output of the sleep control circuit 175. Similarly, delay circuit 295B can delay the sleep control signal SLP to obtain a delayed signal SLPQ_RIGHT, and provide the delayed signal SLPQ_RIGHT to the output driver 280B. Delay circuit 295B can operate as a buffer between the sleep control circuit 175 and the output driver 280B to reduce the capacitive load at the output of the sleep control circuit 175.

[0042] In some embodiments, output drivers 280A, 280B are circuits that provide data stored by the set of memory cells 125. In one aspect, output driver 280A is coupled to one or more sense amplifiers that amplify a signal corresponding to the data stored in the memory cells 125 in the left region. In another aspect, output driver 280B is coupled to one or more sense amplifiers that amplify a signal corresponding to the data stored in the memory cells 125 in the right region. Output driver 280A can receive a delayed signal SLPQ_TRK_LEFT, a delayed signal SLPQ_LEFT, and an amplified signal from the sense amplifier corresponding to the memory cells 125 in the left region, and accordingly generate output data signals Q1…Qn corresponding to the data stored in the memory cells 125 in the left region. For example, in response to the delay signal SLPQ_TRK_LEFT indicating that the memory cell 125 is in a sleep state or the delay signal SLPQ_LEFT configuring the output driver 280A to a sleep state, the output driver 280A can generate output data signals Q1…Qn with a predetermined voltage (e.g., 0V corresponding to bit "0"). For example, in response to the delay signal SLPQ_TRK_LEFT indicating that the memory cell 125 is in an operating state and the delay signal SLPQ_LEFT configuring the output driver 280A to an operating state, the output driver 280A can generate output data signals Q1…Qn representing the stored data based on the amplified signal from the sense amplifier. For the delay signal SLPQ_TRK_RIGHT, the delay signal SLPQ_RIGHT, and the amplified signal from the sense amplifier corresponding to the memory cell 125 in the right region, the output driver 280B can operate in a manner similar to the output driver 280A, and accordingly generate output data signals Qn+1…Qm corresponding to the data stored by the memory cell 125 in the right region. Referring below... Figures 3 to 4 Provides a detailed description of the configuration and operation of output drivers 280A and 280B.

[0043] In some embodiments, wake-up detection circuits 185A and 185B are circuits that generate wake-up completion signals WAKEUP_DONE_SD and WAKEUP_DONE_DSLP (also referred to as "WAKEUP_DONE"). The wake-up completion signal WAKEUP_DONE can indicate whether the wake-up sequence is complete. In one aspect, wake-up detection circuits 185A and 185B receive a delayed signal SLPQ_TRK_RIGHT or a delayed signal SLPQ_TRK_LEFT, and generate a wake-up completion signal WAKEUP_DONE accordingly. For example, in response to the delayed signal SLPQ_TRK_RIGHT or the delayed signal SLPQ_TRK_LEFT indicating that the memory cell 125 is operating in a sleep state, wake-up detection circuits 185A and 185B can generate a wake-up completion signal WAKEUP_DONE with a first voltage (e.g., 1V) to indicate that the wake-up sequence is not complete. For example, in response to a delay signal SLPQ_TRK_RIGHT or a delay signal SLPQ_TRK_LEFT indicating that memory cell 125 is in an operating state, wake-up detection circuits 185A and 185B can generate a wake-up completion signal WAKEUP_DONE with a second voltage (e.g., 0V) to indicate that the wake-up sequence has been completed. (See below for reference.) Figures 3 to 8 , Figure 10 and Figure 11 Provides a detailed description of the configuration and operation of wake-up detection circuits 185A and 185B.

[0044] Figure 3 The illustrations depict some embodiments. Figure 2A schematic diagram of portion 298A of the memory controller 105 is shown. In one aspect, portion 298A of the memory controller 105 includes output drivers 280B1…280BM, delay circuits 290B, 292, 295 (e.g., 295B), and wake-up detection circuits 185A, 185B. In some embodiments, delay circuit 290B receives a sleep tracking signal SLP_TRK and generates a delayed signal SLPQ_TRK_RIGHT. Output drivers 280B1…280BM can receive the delayed signal SLPQ_TRK_RIGHT and generate output data signals Qn+1…Qm based on the delayed signal SLPQ_TRK_RIGHT. Delay circuit 292 can receive the delayed signal SLPQ_TRK_RIGHT after it has been provided to output driver 280BM, and delay the delayed signal SLPQ_TRK_RIGHT to obtain another delayed signal SLPQ_TRKR. Delay circuit 292 can provide the delayed sleep tracking signal SLPQ_TRKR to delay circuit 330. Delay circuit 292 can operate as a buffer or amplifier to amplify the delayed signal SLPQ_TRK_RIGHT provided to output buffers 280B1…280BM. Delay circuit 330 can receive the delayed signal SLPQ_TRKR and delay it to obtain delayed signal 335. Delay circuit 330 can be used as a buffer or amplifier to amplify the delayed sleep tracking signal SLPQ_TRKR provided from delay circuit 292 via a long metal rail extending along output buffers 280B1…280BM. Delay circuit 330 may include an even number of inverter circuits, one or more amplifier circuits, one or more buffer circuits, one or more resistor delay circuits, adjustable delay circuits, or any delay circuit. Delay circuit 330 can provide the delayed signal 335 to wake-up detection circuits 185A, 185B.

[0045] In some embodiments, the wake-up detection circuit 185A includes or is implemented as an OR gate. The wake-up detection circuit 185A can receive a delayed signal 335 and a signal DSLP, and perform an OR operation between the delayed signal 335 and the signal DSLP according to the OR operation to generate a wake-up complete signal WAKEUP_DONE_DSLP.

[0046] In some embodiments, the wake-up detection circuit 185B includes or is implemented as an OR gate. The wake-up detection circuit 185B can receive a delayed signal 335 and a signal SD, and perform an OR operation between the delayed signal 335 and the signal SD according to the OR operation to generate a wake-up complete signal WAKEUP_DONE_SD.

[0047] In one aspect, each output driver 280 includes a latch circuit 350, a power switch SW, and an output circuit 380. These components can operate together to selectively provide output data Q according to a delayed sleep control signal SLPQ_RIGHT, a delayed sleep tracking signal SLPQ_TRK_RIGHT, or both. For example, in response to the delayed signal SLPQ_TRK_RIGHT indicating that the memory cell 125 is in a sleep state or the delayed signal SLPQ_RIGHT configuring the latch circuit 350 in a sleep state, the output driver 280 can generate an output data signal Q having a predetermined voltage (e.g., 0V corresponding to bit "0"). For example, in response to the delayed signal SLPQ_TRK_RIGHT indicating that the memory cell 125 is in an operating state and the delayed signal SLPQ_RIGHT configuring the latch circuit 350 in an operating state, the output driver 280 can generate an output data signal Q indicating the stored data based on an amplified signal from a sense amplifier coupled to the memory cell 125.

[0048] In one configuration, the power switch SW is implemented as a P-type transistor. In some embodiments, the power switch SW may be replaced by different components capable of performing the functions of the power switch SW disclosed herein. The power switch SW may include a source electrode coupled to a power rail to receive a supply voltage VDD, a gate electrode coupled to the output of delay circuit 295, and a drain electrode coupled to latch circuit 350. The power switch SW may receive a delay sleep control signal SLPQ_RIGHT and selectively supply an internal supply voltage VDDI corresponding to the supply voltage VDD to latch circuit 350 according to the delay sleep control signal SLPQ_RIGHT. For example, the power switch SW may be enabled in response to a delay sleep control signal SLPQ_RIGHT having a low voltage (e.g., 0V) to supply the supply voltage VDD to the internal supply voltage VDDI of latch circuit 350. For example, the power switch SW may be disabled in response to a delay sleep control signal SLPQ_RIGHT having a high voltage (e.g., 1V) to not supply the supply voltage VDD to the internal supply voltage VDDI of latch circuit 350.

[0049] The latch circuit 350 receives and stores an amplified signal corresponding to the data stored in the memory cell from the sense amplifier. In some embodiments, the latch circuit 350 may be replaced by different components capable of performing the functions of the latch circuit 350 disclosed herein. In one configuration, the latch circuit 350 includes an input coupled to the output of the sense amplifier and an output coupled to a first input of the output circuit 380. In this configuration, the latch circuit 350 is enabled when the internal supply voltage VDDI has a sufficient voltage (e.g., greater than 0.7 to 0.9 V), and receives and stores the amplified signal QB from the sense amplifier. When the internal supply voltage VDDI does not have a sufficient voltage, the latch circuit 350 may be disabled or may not be operational, and may not store the amplified signal QB from the sense amplifier.

[0050] Output circuit 380 is a component that generates output data Q based on the stored amplified signal QB from the sense amplifier and the delayed sleep tracking signal SLPQ_TRK_RIGHT. In some embodiments, output circuit 380 is implemented as a NOR circuit. In some embodiments, output circuit 380 may be replaced by different components that can perform the functions of output circuit 380 disclosed herein. In one configuration, output circuit 380 includes a first input coupled to the output of latch circuit 350 and a second input coupled to the output of delay circuit 290B. In this configuration, output circuit 380 may receive the stored amplified signal QB at the first input and the delayed sleep tracking signal SLPQ_TRK_RIGHT at the second input, and perform an OR operation on the stored amplified signal QB and the delayed sleep tracking signal SLPQ_TRK_RIGHT to generate output data Q.

[0051] In some embodiments, delay circuit 295 receives a sleep control signal SLP and generates a control signal SLPQ_RIGHT based on the sleep control signal SLP. The output drivers 280B1…280BM can be enabled or disabled based on the control signal SLPQ_RIGHT. In one configuration, memory controller 105 includes a power switch SW0 coupled to the output of delay circuit 295. In one configuration, power switch SW0 is implemented as a P-type transistor. Power switch SW0 may be a transistor of the same type as power switch SW in output driver 280. In some embodiments, power switch SW0 may be replaced by a different component capable of performing the functions of power switch SW0 disclosed herein. Power switch SW0 may include a source electrode coupled to a power rail to receive a supply voltage VDD, a gate electrode coupled to the output of delay circuit 295, and a drain electrode coupled to a power detection circuit (not shown). In this configuration, the drain electrode of power switch SW0 may have an internal supply voltage VDDI, which may be provided to the power detection circuit to determine the internal supply voltage VDDI supplied to output driver 280.

[0052] Advantageously, the memory device 100 can reduce power consumption when transitioning from a sleep state to an operating state. In one aspect, causing the output circuit 380 to generate an output signal Q with a predetermined voltage (e.g., 0V) in response to a sleep control signal SLP or a control signal SLPQ_RIGHT can cause the output driver 280 to consume power when the memory cell 125 has not sufficiently transitioned from a sleep state to an operating state. By causing the output circuit 380 to generate an output signal Q with a predetermined voltage in response to a sleep tracking signal SLP_TRK or a delayed sleep tracking signal SLPQ_TRK_RIGHT, the power consumption of the output driver 280 is reduced or eliminated when the memory cell 125 has not sufficiently transitioned from a sleep state to an operating state.

[0053] Advantageously, when the memory cell 125 and the output driver 280 have transitioned from a sleep state to an operating state, the wake-up detection circuit 185 can accurately generate a wake-up completion signal WAKEUP_DONE (e.g., WAKEUP_DONE_SD or WAKEUP_DONE_DSLP). In one aspect, the internal supply voltage VDDI provided to one or more circuits of the output driver 280 can be changed in response to a sleep control signal SLP. For example, when the sleep control signal SLP with a second voltage (e.g., 1V) puts the output driver 280 into a sleep state, the internal supply voltage VDDI can be set to a first voltage (e.g., 0V). When the sleep control signal SLP with a first voltage (e.g., 0V) puts the output driver 280 into an operating state, the internal supply voltage VDDI can be set to a second voltage (e.g., 1V). Due to capacitive load, changes in the internal supply voltage VDDI may be delayed relative to changes in the sleep control signal SLP or the control signal SLPQ_RIGHT. By enabling the wake-up detection circuit 185 to generate a wake-up completion signal WAKEUP_DONE based on the delay signal 335, the wake-up completion signal WAKEUP_DONE can be accurately generated when the internal supply voltage VDDI reaches a voltage sufficient to operate the output driver 280. Therefore, premature operations such as reading data stored in the memory cell 125 can be avoided before the memory cell 125 and the output driver 280 have transitioned from a sleep state to an operating state, allowing the memory device 100 to operate reliably with reduced power consumption.

[0054] Figure 4 This is a timing diagram 400 illustrating the wake-up sequence of a memory device 100 according to some embodiments. In one aspect, the memory device 100 operates in an operating state during time period T0, and then enters a sleep state during time period T1. Then, the memory device 100 enters a transition state (or wake-up state) during time period T2, and enters an operating state during time period T3.

[0055] During time period T0, the sleep control circuit 175 generates a sleep control signal SLP with a low voltage (e.g., 0V), causing the memory cell 125 to operate in the operational state. During time period T0, the sleep control signal SLP propagates through buffer circuits 245A…245C, where each buffer circuit 245 can generate a delay control signal to configure a corresponding region of the memory cell. During time period T0, buffer circuit 245C (or the last buffer circuit) generates a sleep tracking signal SLP_TRK with a low voltage (e.g., 0V) to indicate that the memory cell 125 is in the operational state.

[0056] During time period T0, delay circuit 290B receives the sleep tracking signal SLP_TRK and generates a delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) with a low voltage (e.g., 0V) in response to the sleep tracking signal SLP_TRK with a low voltage. Delay circuit 290B can provide the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) to output circuit 380. Delay circuit 292 can receive the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) and generate a delayed sleep tracking signal SLPQ_TRKR with a low voltage (e.g., 0V) in response to the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) with a low voltage, indicating that memory cell 125 and output driver 280 are in an operational state. During time period T0, in response to a delayed sleep tracking signal SLPQ_TRKR with a low voltage (e.g., 0V), the wake-up detection circuit 185 can generate a wake-up completion signal WAKEUP_DONE with a low voltage (e.g., 0V) to indicate that the memory device 100 is operating in the operating state.

[0057] During time period T0, delay circuit 295B (or 295) receives the sleep control signal SLP and generates a control signal SLPQ_RIGHT after or after a delay of the sleep control signal SLP having a low voltage (e.g., 0V). During time period T0, in response to the control signal SLPQ_RIGHT having a low voltage (e.g., 0V), latch circuit 350 can be energized and can provide the stored amplified signal QB to output circuit 380. During time period T0, in response to the delayed sleep tracking signal SLPQ_TRK_RIGHT (or SLPQ_TRK) having a low voltage (e.g., 0V), output circuit 380 can generate an output signal Q indicating the data stored in memory cell 125 based on the stored amplified signal QB. For example, during time period T0, output circuit 380 may generate output signal Q in response to the delayed sleep tracking signal SLPQ_TRK_RIGHT (or SLPQ_TRK) having a low voltage (e.g., 0V), output signal Q indicating that the data stored by memory cell 125 is the inverted (or relative) value of the stored amplified signal QB.

[0058] During time period T1, the sleep control circuit 175 generates a sleep control signal SLP with a high voltage (e.g., 1V), causing the memory cell 125 to operate in a sleep state. During time period T0, the sleep control signal SLP propagates through buffer circuits 245A…245C. During time period T1, due to buffer circuits 245A…245C, after a certain delay, buffer circuit 245C (or the last buffer circuit) generates a sleep tracking signal SLP_TRK with a high voltage (e.g., 1V) to indicate that the memory cell 125 is in a sleep state.

[0059] During time period Tl, delay circuit 290B receives the sleep tracking signal SLP_TRK and generates a delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) with a high voltage (e.g., 1V) in response to the sleep tracking signal SLP_TRK with a high voltage. Delay circuit 290B can provide the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) to output circuit 380. Delay circuit 292 can receive the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) and generate a delayed sleep tracking signal SLPQ_TRKR with a high voltage (e.g., 1V) in response to the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) with a high voltage to indicate that memory cell 125 and output driver 280 are in sleep mode. During time period T1, in response to the delayed sleep tracking signal SLPQ_TRKR having a high voltage (e.g., 1V), the wake-up detection circuit 185 can generate a wake-up completion signal WAKEUP_DONE with a high voltage (e.g., 1V) to indicate that the memory device 100 is operating in a sleep state or that the wake-up sequence has not yet been completed.

[0060] During time period T1, delay circuit 295B (or 295) receives the sleep control signal SLP and generates a control signal SLPQ_RIGHT after or after a delay of the sleep control signal SLP having a high voltage (e.g., 1V). During time period T1, latch circuit 350 may be de-energized in response to the control signal SLPQ_RIGHT having a high voltage (e.g., 1V). Furthermore, during time period T1, in response to the delayed sleep tracking signal SLPQ_TRK_RIGHT (or SLPQ_TRK) having a high voltage (e.g., 1V), output circuit 380 may output signal Q.

[0061] During time period T2, the sleep control circuit 175 generates a sleep control signal SLP with a low voltage (e.g., 0V) to initiate a wake-up sequence. The transition of the sleep control signal SLP from a high voltage (e.g., 1V) to a low voltage (e.g., 0V) can cause the memory cell 125 to transition from a sleep state to an operating state. During time period T2, the sleep control signal SLP propagates through buffer circuits 245A…245C, where each buffer circuit 245 can generate a delay control signal to configure a corresponding region of the memory cell. Due to the delay associated with the buffer circuits 245A…245C, the sleep tracking signal SLP_TRK can be delayed relative to the sleep control signal SLP. During time period T2, after a certain delay (as associated with the buffer circuits 245A…245C) from the sleep control signal SLP to the low voltage (e.g., 0V), the buffer circuit 245C (or the last buffer circuit) generates the sleep tracking signal SLP_TRK with a low voltage (e.g., 0V).

[0062] During time period T2, delay circuit 290B receives the sleep tracking signal SLP_TRK and generates a delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) based on the sleep tracking signal SLP_TRK. During time period T2, due to the delay associated with delay circuit 290B, the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) may still have a high voltage (e.g., 1V). During time period T2, delay circuit 290B can provide the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) to output circuit 380. During time period T2, delay circuit 292 can receive the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) and generate a delayed sleep tracking signal SLPQ_TRKR after the sleep tracking signal SLP_TRK or the delayed sleep tracking signal SLPQ_TRK (or SLPQ_TRK_RIGHT) with a high voltage (e.g., 1V) to indicate that the wake-up procedure has not yet been completed. During time period T2, due to the delay associated with delay circuit 292, the delayed sleep tracking signal SLPQ_TRKR may still have a high voltage (e.g., 1V). During time period T2, in response to the delayed sleep tracking signal SLPQ_TRKR having a high voltage (e.g., 1V), wake-up detection circuit 185 may generate a wake-up completion signal WAKEUP_DONE with a high voltage (e.g., 1V) to indicate that memory device 100 is still operating in sleep mode or the wake-up sequence has not yet been completed.

[0063] During time period T2, delay circuit 295B (or 295) receives the sleep control signal SLP and generates a control signal SLPQ_RIGHT after a certain delay (e.g., a delay associated with delay circuit 295), the control signal SLPQ_RIGHT being either after or delayed from the sleep control signal SLP having a low voltage (e.g., 0V). During time period T2, latch circuit 350 can be energized in response to the control signal SLPQ_RIGHT having a low voltage (e.g., 0V). During time period T2, latch circuit 350 can receive an amplified signal corresponding to the data stored in memory cell 125 and store the amplified signal QB. However, during time period T2, in response to the delayed sleep tracking signal SLPQ_TRK_RIGHT (or SLPQ_TRK) having a high voltage (e.g., 1V), output circuit 380 can maintain the output signal Q at a predetermined voltage (e.g., 0V), regardless of the data stored in memory cell 125.

[0064] During time period T3, the sleep control signal SLP has a low voltage (e.g., 0V). During time period T3, the sleep tracking signal SLP_TRK may have a low voltage (e.g., 0V). During time period T3, the control signal SLPQ_RIGHT may also have a low voltage (e.g., 0V). During time period T3, the delayed sleep tracking signal SLPQ_TRK_RIGHT (or SLPQ_TRK) follows or delays the sleep tracking signal SLP_TRK, which may have a low voltage (e.g., 0V). During time period T3, the latch circuit 350 may still be energized in response to the control signal SLPQ_RIGHT having a low voltage (e.g., 0V) and may provide the stored amplified signal QB to the output circuit 380. During time period T3, in response to the delayed sleep tracking signal SLPQ_TRK_RIGHT (or SLPQ_TRK) having a low voltage (e.g., 0V), the output circuit 380 may generate an output signal Q based on the stored amplified signal QB, the output signal Q indicating the data stored in the memory cell 125. During time period T3, in response to a delayed sleep tracking signal SLPQ_TRK_RIGHT (or SLPQ_TRK) with a low voltage (e.g., 0V), delay circuit 292 can generate a delayed sleep tracking signal SLPQ_TRKR with a low voltage (e.g., 0V). For example, during time period T3, in response to a delayed sleep tracking signal SLPQ_TRK_RIGHT (or SLPQ_TRK) with a low voltage (e.g., 0V), output circuit 380 can generate an output signal Q indicating the data stored in memory cell 125, where output signal Q is the inverse (or relative) value of the stored amplified signal QB. During time period T3, in response to a delayed sleep tracking signal SLPQ_TRKR with a low voltage (e.g., 0V), wake-up detection circuit 185 can generate a wake-up completion signal WAKEUP_DONE with a low voltage (e.g., 0V) to indicate that the memory device 100 has completed its operation or wake-up sequence in the operating state.

[0065] Advantageously, the memory device 100 can reduce power consumption during wake-up or transition from sleep to operation. In one aspect, by causing the output circuit 380 to generate an output signal Q with a predetermined voltage (e.g., 0V) in response to a sleep control signal SLP or a control signal SLPQ_RIGHT, the output driver 280 can be made to consume power when the memory cell 125 has not sufficiently transitioned from sleep to operation. By causing the output circuit 380 to generate an output signal Q with a predetermined voltage in response to a sleep tracking signal SLP_TRK or a delayed sleep tracking signal SLPQ_TRK_RIGHT, the power consumption of the output driver 280 can be reduced or eliminated when the memory cell 125 has not sufficiently transitioned from sleep to operation.

[0066] Figure 5 The illustrations depict some embodiments. Figure 2 A schematic diagram of portion 298B of the memory controller 105. In one aspect, portion 298B of the memory controller 105 is similar to... Figure 3 The memory controller 105 in part 298A includes, except that the memory controller 105 includes the drain electrode coupled to the power switch SW0 and the power detection circuit 520 of the wake-up detection circuits 185A and 185B. Therefore, for the sake of brevity, a detailed description of its repeated parts is omitted here.

[0067] In some embodiments, the power detection circuit 520 includes an input coupled to the drain electrode of the power switch SW0 and an output coupled to the input of the wake-up detection circuits 185A, 185B. In this configuration, the power detection circuit 520 can receive an internal supply voltage VDDI from the power switch SW0 and generate a power detection signal VDDI_RDYB based on the internal supply voltage VDDI. For example, if the internal supply voltage VDDI is higher than a threshold voltage (e.g., 0.7–0.9V), the power detection circuit 520 can generate a power detection signal VDDI_RDYB with a low voltage (e.g., 0V) to indicate that the output driver 280 has sufficient power or internal supply voltage VDDI to operate. For example, if the internal supply voltage VDDI is less than a threshold voltage (e.g., 0.7–0.9V), the power detection circuit 520 can generate a power detection signal VDDI_RDYB with a high voltage (e.g., 1V) to indicate that the output driver 280 does not have sufficient power or internal supply voltage VDDI to operate.

[0068] The wake-up detection circuits 185A and 185B can further generate wake-up completion signals WAKEUP_DONE_SD and WAKEUP_DONE_DSLP based on the power detection signal VDDI_RDYB. For example, the wake-up detection circuit 185A can be implemented as a three-input OR gate, which performs an OR operation on the input signal DSLP, the power detection signal VDDI_RDYB, and the delay signal 335 to generate the wake-up completion signal WAKEUP_DONE_DSLP. Similarly, for example, the wake-up detection circuit 185B can be implemented as a three-input OR gate, which performs an OR operation on the input signal SD, the power detection signal VDDI_RDYB, and the delay signal 335 to generate the wake-up completion signal WAKEUP_DONE_SD based on the OR operation.

[0069] Advantageously, when the memory cell 125 and the output driver 280 have transitioned from a sleep state to an operating state, the wake-up detection circuit 185 can accurately generate a wake-up completion signal WAKEUP_DONE. In one aspect, the internal supply voltage VDDI provided to one or more circuits of the output driver 280 can be changed in response to a sleep control signal SLP. For example, when the sleep control signal SLP has a high voltage (e.g., 1V) that puts the output driver 280 into a sleep state, the internal supply voltage VDDI can be set to a first voltage (e.g., 0V). When the sleep control signal SLP has a low voltage (e.g., 0V) that puts the output driver 280 into an operating state, the internal supply voltage VDDI can be set to a second voltage (e.g., 1V). Due to capacitive load, changes in the internal supply voltage VDDI may be delayed relative to changes in the sleep control signal SLP or the control signal SLPQ_RIGHT. By enabling the wake-up detection circuit 185 to generate a wake-up completion signal WAKEUP_DONE based on the delay signal 335 and the power supply detection signal VDDI_RDYB, the wake-up completion signal WAKEUP_DONE can be accurately generated when the internal supply voltage VDDI reaches a sufficiently high voltage to enable the output driver 280 to operate. Therefore, premature operations such as reading data stored in the memory cell 125 can be avoided before the memory cell 125 and the output driver 280 have sufficiently transitioned from the sleep state to the operating state, allowing the memory device 100 to operate reliably with reduced power consumption.

[0070] Figure 6 A schematic diagram of a power supply detection circuit 520 according to some embodiments is illustrated. In some embodiments, the power supply detection circuit 520 includes transistors M1…M6. Transistors M1…M3 are implemented as P-type transistors, and transistors M4…M6 are implemented as N-type transistors. These components can operate together to detect an internal supply voltage VDDI and generate a power supply detection signal VDDI_RDYB based on the internal supply voltage VDDI. For example, if the internal supply voltage VDDI is higher than a threshold voltage (e.g., 0.7–0.9V), the power supply detection circuit 520 can generate a power supply detection signal VDDI_RDYB with a low voltage (e.g., 0V) to indicate that the output driver 280 has sufficient power supply or internal supply voltage VDDI to operate. For example, if the internal supply voltage VDDI is lower than a threshold voltage (e.g., 0.7–0.9V), the power supply detection circuit 520 can generate a power supply detection signal VDDI_RDYB with a high voltage (e.g., 1V) to indicate that the output driver 280 does not have sufficient power supply or internal supply voltage VDDI to operate. In some embodiments, the power detection circuit 520 includes a ratio Figure 6 Show more, fewer, or different components.

[0071] In one configuration, transistor M1 includes a source electrode coupled to a power rail to receive a supply voltage VDD and a gate electrode coupled to an input of power detection circuit 520. In another configuration, the drain electrode of transistor M1 is coupled to the source electrodes of transistors M2 and M3. In one configuration, transistor M2 includes a gate electrode coupled to an input of power detection circuit 520 and a drain electrode coupled to an output of power detection circuit 520. In one configuration, transistor M3 includes a gate electrode coupled to an output of power detection circuit 520 and a drain electrode coupled to a ground rail to receive a ground voltage VSS.

[0072] In one configuration, transistor M4 includes a source electrode coupled to the ground rail to receive the ground voltage VSS, and a gate electrode coupled to the input of the power supply detection circuit 520. In another configuration, the drain electrode of transistor M4 is coupled to the source electrodes of transistors M5 and M6. In yet another configuration, transistor M5 includes a gate electrode coupled to the input of the power supply detection circuit 520 and a drain electrode coupled to the output of the power supply detection circuit 520. In yet another configuration, transistor M6 includes a gate electrode coupled to the output of the power supply detection circuit 520 and a drain electrode coupled to the power rail to receive the supply voltage VDD.

[0073] In this configuration, transistors M1…M6 can be arranged as Schmitt triggers and generate a power supply detection signal VDDI_RDYB based on the internal supply voltage VDDI. For example, if the internal supply voltage VDDI is higher than a threshold voltage (e.g., 0.7–0.9V), transistors M4 and M5 can be enabled, and transistors M1 and M2 can be disabled to pull down the power supply detection circuit 520. By pulling down the voltage at the output of the power supply detection circuit 520, the power supply detection signal VDDI_RDYB at the output of the power supply detection circuit 520 can have a low voltage (e.g., 0V) to indicate that the output driver 280 has sufficient power or internal supply voltage VDDI for operation. For example, if the internal supply voltage VDDI is lower than a threshold voltage (e.g., 0.7–0.9V), transistors M4 and M5 can be disabled, and transistors M1 and M2 can be enabled, pulling up the voltage at the output of the power supply detection circuit 520. By adjusting the voltage at the output of the power supply detection circuit 520, the power supply detection signal VDDI_RDYB at the output of the power supply detection circuit 520 can have a high voltage (e.g., 1V) to indicate that the output driver 280 does not have sufficient power or internal supply voltage VDDI to operate.

[0074] Figure 7This is a timing diagram 700 illustrating the wake-up sequence of a memory device 100 according to some embodiments. In one aspect, the signals SLP, SLPQ_RIGHT, WAKE_DONE, and SLPQ_TRKR are similar to Figure 4 The signal described in [the document]. Therefore, for the sake of brevity, detailed descriptions of its repeated parts are omitted here.

[0075] During time period T0, delay circuit 295 generates a delay signal SLPQ_RIGHT with a low voltage (e.g., 0V) in response to a sleep control signal SLP. In response to the low-voltage delay signal SLPQ_RIGHT, power switch SW can be enabled. By enabling power switch SW, the internal supply voltage VDDI can have a high voltage (e.g., 1V) to enable latch circuit 350 of output driver 280. During time period T0, power detection circuit 520 can detect that the supply voltage VDDI is higher than a threshold voltage and generate a power detection signal VDDI_RDYB with a low voltage (e.g., 0V) to indicate that output driver 280 has sufficient power or internal supply voltage VDDI for operation. During time period T0, in response to a delayed sleep tracking signal SLPQ_TRKR (or SLPQ_TRK_RIGHT) with a low voltage (e.g., 0V) and a power detection signal VDDI_RDYB with a low voltage (e.g., 0V), the wake-up detection circuit 185 may generate a wake-up completion signal WAKEUP_DONE with a low voltage (e.g., 0V) to indicate that the memory device 100 is operating in the operating state.

[0076] During time period T1, delay circuit 295 generates a delay signal SLPQ_RIGHT with a high voltage (e.g., 1V) in response to a sleep control signal SLP with a high voltage (e.g., 1V). In response to SLPQ_RIGHT with a high voltage (e.g., 1V), power switch SW can be disabled. By disabling power switch SW, the internal supply voltage VDDI can be reduced to a low voltage (e.g., 0V) to disable latching circuit 350 of output driver 280. Due to the capacitive load of output driver 280, internal supply voltage VDDI may not change or decrease immediately. During time period T1, power detection circuit 520 can detect that the supply voltage VDDI is still above a threshold voltage and generate or maintain a power detection signal VDDI_RDYB with a low voltage (e.g., 0V) to indicate that output driver 280 has sufficient power or internal supply voltage VDDI for operation. During time period T1, in response to a delayed sleep tracking signal SLPQ_TRKR (or SLPQ_TRK_RIGHT) with a high voltage (e.g., 1V), the wake-up detection circuit 185 can generate a wake-up completion signal WAKEUP_DONE with a high voltage (e.g., 1V) to indicate that the memory device 100 is operating in a sleep state.

[0077] During time period T2, the sleep control signal SLP has a low voltage (e.g., 0V) to initiate the wake-up sequence. The sleep control signal SLP with a low voltage (e.g., 0V) allows memory cell 125 to operate in an operational state. During time period T2, after a certain delay (e.g., a delay associated with delay circuit 295) following the transition from the sleep control signal to the low voltage, delay circuit 295 generates a delayed signal SLPQ_RIGHT with a low voltage (e.g., 0V). During time period T2, when SLPQ_RIGHT has a low voltage (e.g., 0V), power switch SW is enabled. By enabling power switch SW, the internal supply voltage VDDI can be increased to a high voltage (e.g., 1V) to enable latch circuit 350 of output driver 280. However, due to the capacitive load of output driver 280, the internal supply voltage VDDI may not change immediately. Therefore, power detection circuit 520 can maintain the power detection signal VDDI_RDYB at a high voltage (e.g., 1V) because the internal supply voltage VDDI may still be below a threshold voltage. During time period T2, after a certain delay (e.g., the delay associated with delay circuits 290B, 292), the delayed sleep tracking signal SLPQ_TRKR (or SLPQ_TRK_RIGHT), which is delayed from or following the sleep tracking signal SLP_TRK, can transition from a high voltage (e.g., 1V) to a low voltage (e.g., 0V). During time period T2, in response to: i) the delayed sleep tracking signal SLPQ_TRKR (or SLPQ_TRK_RIGHT) having a high voltage (e.g., 1V) during the first portion of time period T2 before transitioning to a low voltage (e.g., 0V), and ii) the power detection signal VDDI_RDYB having a high voltage (e.g., 1V) during the second portion of time period T2, the wake-up detection circuit 185 can generate or maintain a wake-up completion signal WAKEUP_DONE with a high voltage (e.g., 1V) to indicate that the memory device 100 is still operating in a sleep state or the wake-up procedure has not yet been completed.

[0078] During time period T3, the power supply detection circuit 520 can detect that the supply voltage VDDI is greater than the threshold voltage and generate a power supply detection signal VDDI_RDYB with a low voltage (e.g., 0V) to indicate that the output driver 280 has sufficient power or internal supply voltage VDDI for operation. During time period T3, the wake-up detection circuit 185, in response to the delayed sleep tracking signal SLPQ_TRKR (or SLPQ_TRK_RIGHT) with a low voltage (e.g., 0V) and the power supply detection signal VDDI_RDYB with a low voltage (e.g., 0V), can generate a wake-up completion signal WAKEUP_DONE with a low voltage (e.g., 0V) to indicate that the wake-up sequence has been completed and the memory device 100 is operating in an operational state.

[0079] Advantageously, when the memory cell 125 and the output driver 280 have transitioned from a sleep state to an operating state, the wake-up detection circuit 185 can accurately generate a wake-up completion signal WAKEUP_DONE. In one aspect, the internal supply voltage VDDI provided to one or more circuits of the output driver 280 can be changed in response to a sleep control signal SLP. For example, when the sleep control signal SLP has a second voltage (e.g., 1V) that puts the output driver 280 into a sleep state, the internal supply voltage VDDI can be set to a first voltage (e.g., 0V), and when the sleep control signal SLP has a first voltage (e.g., 0V) that puts the output driver 280 into an operating state, the internal supply voltage VDDI can be set to a second voltage (e.g., 1V). Due to capacitive load, changes in the internal supply voltage VDDI may be delayed relative to changes in the sleep control signal SLP or the control signal SLPQ_RIGHT. By having the wake-up detection circuit 185 generate a wake-up completion signal WAKEUP_DONE based on the delay signal 335 and the power supply detection signal VDDI_RDYB, the wake-up completion signal WAKEUP_DONE can be accurately generated when the internal supply voltage VDDI reaches a sufficiently high voltage to operate the output driver 280. Therefore, premature operations such as reading data stored in the memory cell 125 can be avoided before the memory cell 125 and the output driver 280 have sufficiently transitioned from the sleep state to the operating state, allowing the memory device 100 to operate reliably with low power consumption.

[0080] Figure 8 The illustrations depict some embodiments. Figure 1 A schematic diagram of portion 298C of the memory controller 105. In one aspect, portion 298C of the memory controller 105 is similar to... Figure 3 The memory controller 105 in part 298A includes delay circuits 830, 840, and 890, which respectively replace delay circuits 330, 292, and 290B. Therefore, for the sake of brevity, detailed descriptions of their repeated portions are omitted here. Each of the delay circuits 830, 840, and 890 can be as follows... Figures 9A to 9D The example shown.

[0081] Figures 9A to 9D Schematic diagrams of delay circuits 900A…900D according to some embodiments are shown. Each of the delay circuits 900A…900D can be implemented as one or more delay circuits disclosed herein. In some embodiments, memory device 100 can be implemented with… Figures 9A to 9D Different delay circuits are shown. In some embodiments, Figure 9AThe delay circuit 900A in the middle includes and Figure 6 The power detection circuit 520 shown is a first delay circuit 910 similar to a Schmitt trigger, and the second delay circuit 920 is implemented as an inverter circuit. In some embodiments, Figure 9B The delay circuit 900B may include a first delay circuit 930 implemented as an inverter circuit and a second delay circuit 920 implemented as an inverter circuit. In some embodiments, Figure 9C The delay circuit 900C may include a first delay circuit 910, a second delay circuit 920, and a resistive element 925 (e.g., a metal rail or a high-resistivity material) located between the first delay circuit 910 and the second delay circuit 920. In one aspect, the resistive element 925 can be selected or adjusted to obtain a target delay. In some embodiments, Figure 9D The delay circuit 900D may include an even number of inverters 950 cascaded together. In one aspect, multiple inverters 950 can be selected or adjusted to obtain a target delay.

[0082] Figure 10 The illustrations depict some embodiments. Figure 2 A schematic diagram of portion 298D of the memory controller 105. In one aspect, portion 298D of the memory controller 105 is similar to... Figure 3 The memory controller 105 is part 298B. This excludes the memory controller 105 including a delay circuit 1010 between the power detection circuit 520 and the wake-up detection circuit 185. Therefore, for brevity, a detailed description of its repeated parts is omitted here. The delay circuit 1010 can be as follows... Figures 9A to 9D The embodiment shown. In some embodiments, the delay circuit 1010 may be implemented as a variable delay circuit. By using the output of the delay power supply detection circuit 520, premature generation of the wake-up completion signal WAKEUP_DONE (e.g., WAKEUP_DONE_SD, WAKEUP_DONE_DSLP) can be avoided before the memory cell 125 and the output driver 280 have sufficiently transitioned to the operating state.

[0083] Figure 11 A flowchart illustrating a method 1100 for performing a wake-up sequence by a memory device according to some embodiments is shown. In some embodiments, method 1100 is performed by a controller (e.g., memory controller 105 or main controller 110). In some embodiments, method 1100 is performed by other entities. In some embodiments, method 1100 includes... Figure 11 Show more, fewer, or different steps.

[0084] In one method, 1110, the controller generates a sleep control signal (e.g., a sleep control signal SLP) to transition a memory cell (e.g., memory cell 125) from a sleep state to an operational state, thereby initiating a wake-up sequence. For example, memory array 120 includes buffer circuits 245A…245C for propagating the sleep control signal SLP. The buffer circuits 245A…245C can be cascaded to propagate the sleep control signal SLP for different memory cells 125.

[0085] In one method, 1120, the controller generates an output signal (e.g., output signal Q) with a predetermined voltage (e.g., 0V) in response to a sleep tracking signal, indicating that the memory cell has not yet transitioned to an operational state, regardless of the data stored in memory cell 125. In another method, the controller's output driver (e.g., output circuit 380) receives the sleep tracking signal (e.g., SLP_TRK). The sleep tracking signal can be delayed from the sleep control signal SLP. For example, the sleep tracking signal can be the last delayed signal from the last buffer circuit of buffer circuits 245A…245C. Thus, the sleep tracking signal can indicate that the last memory cell in the set of memory cells has transitioned from a sleep state to an operational state. Until the sleep tracking signal indicating that the memory cell has transitioned to an operational state, the controller's output driver (e.g., output circuit 380) can generate and maintain the output signal with the predetermined state.

[0086] In one method, 1130, the controller detects that the memory cell has transitioned from a sleep state to an operating state. In another method, after a certain delay from a sleep control signal, a sleep tracking signal may indicate that the memory cell has completed a wake-up sequence and transitioned from a sleep state to an operating state.

[0087] In one method, 1140, after a memory cell has transitioned from a sleep state to an operating state, the controller generates an output signal to indicate the data stored in the memory cell. For example, in response to a sleep tracking signal indicating that the memory cell has transitioned to an operating state, the controller's output driver (e.g., output circuitry 380) may receive a signal indicating the data stored in the memory cell, for example, from a sense amplifier or a latch (e.g., 350) coupled to the sense amplifier, and generate an output signal indicating the data.

[0088] Advantageously, the memory device can reduce power consumption when transitioning from a sleep state to an operating state. In one aspect, by having the output driver generate an output signal with a predetermined voltage in response to a sleep control signal, the output driver can be made to consume power when the memory cells have not sufficiently transitioned from a sleep state to an operating state. By having the output driver generate an output signal with a predetermined voltage in response to a sleep tracking signal, the power consumption of the output driver can be reduced or eliminated when the memory cells have not sufficiently transitioned from a sleep state to an operating state.

[0089] Now for reference Figure 12 This diagram illustrates an example block diagram of a computing system 1200 according to some embodiments of the present disclosure. The computing system 1200 can be used by a circuit or layout designer of integrated circuit designs. As used herein, "circuit" is an interconnection of electrical components, such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured to perform desired functions. The computing system 1200 includes a master device 1205 associated with a memory device 1210. The master device 1205 can be configured to receive input from one or more input devices 1215 and provide output to one or more output devices 1220. The master device 1205 can be configured to communicate with the memory device 1210, the input device 1215, and the output device 1220 via appropriate interfaces 1225A, 1225B, and 1225C, respectively. The computing system 1200 can be implemented in a variety of computing devices, such as computers (e.g., desktops, laptops, servers, data centers, etc.), tablets, personal digital assistants, mobile devices, other handheld or portable devices, or any other device suitable for performing schematic design and / or layout design using the main device 1205.

[0090] Input device 1215 may include any of a variety of input technologies, such as a keyboard, stylus, touchscreen, mouse, trackball, keypad, microphone, voice recognition, motion recognition, remote control, input port, one or more buttons, dials, joystick, and any other input peripheral associated with master device 1205 that allows users (e.g., circuit designers or layout designers) to input information (e.g., data) from external sources into master device 1205 to send instructions to master device. Similarly, output device 1220 may include a variety of output technologies, such as external memory, printer, speaker, display, microphone, LED, headphones, video equipment, and any other output peripheral configured to receive information (e.g., data) from master device 1205. "Data" input to and / or output from master device 1205 may include any of a variety of text data, circuit data, signal data, semiconductor device data, graphic data, combinations thereof, or other types of analog and / or digital data suitable for processing using computing system 1200.

[0091] The host device 1205 includes or is associated with one or more processing units / processors, such as central processing unit (“CPU”) cores 1230A…1230N. CPU cores 1230A…1230N may be implemented as application-specific integrated circuits (“ASICs”), field-programmable gate arrays (“FPGAs”), or any other type of processing unit. Each of the CPU cores 1230A…1230N may be configured to execute instructions for running one or more applications of the host device 1205. In some embodiments, the instructions and data for running one or more applications may be stored in memory device 1210. The host device 1205 may also be configured to store the results of running one or more applications in memory device 1210. Therefore, the host device 1205 may be configured to request memory device 1210 to perform various operations. For example, the host device 1205 may request memory device 1210 to read data, write data, update or delete data, and / or perform management operations or other operations. One such application that the host device 1205 may be configured to run may be a standard unit application 1235. The standard cell application 1235 may be a standard cell used by a user of the main device 1205 to create or modify circuits, which is part of a computer-aided design or electronic design automation software suite. In some embodiments, instructions for executing or running the standard cell application 1235 may be stored in the memory device 1210. The standard cell application 1235 may be executed by one or more of the CPU cores 1230A…1230N using instructions associated with the standard cell application from the memory device 1210. In one example, the standard cell application 1235 allows a user to use pre-generated schematics and / or layout designs of the memory device 100 or a portion thereof to aid in integrated circuit design. After the layout design of the integrated circuit is completed, the manufacturing equipment can manufacture multiple integrated circuits, including, for example, the memory device 100 or any portion thereof, according to the layout design.

[0092] Still referencing Figure 12The memory device 1210 includes a memory controller 1240 configured to read data from or write data to the memory array 1245. The memory array 1245 may include various volatile and / or non-volatile memories. For example, in some embodiments, the memory array 1245 may include NAND flash memory cores. In other embodiments, the memory array 1245 may include NOR flash memory cores, static random access memory (SRAM) cores, dynamic random access memory (DRAM) cores, magnetoresistive random access memory (MRAM) cores, phase-change memory (PCM) cores, resistive random access memory (ReRAM) cores, 3DXPoint memory cores, ferroelectric random access memory (FeRAM) cores, and other types of memory cores suitable for a memory array. The memories within the memory array 1245 can be controlled individually and independently by the memory controller 1240. In other words, the memory controller 1240 can be configured to communicate individually and independently with each memory within the memory array 1245. By communicating with memory array 1245, memory controller 1240 can be configured to read data from or write data to memory array in response to instructions received from host device 1205. Although shown as part of memory device 1210, in some embodiments, memory controller 1240 may be part of host device 1205 or part of another component of computing system 1200 and associated with memory device 1210. Memory controller 1240 may be implemented as logic circuitry in software, hardware, firmware, or a combination thereof to perform the functions described herein. For example, in some embodiments, memory controller 1240 may be configured to retrieve instructions associated with standard cell application 1235 stored in memory array 1245 of memory device 1210 upon receiving a request from host device 1205.

[0093] It should be understood that Figure 12 Only some components of the computing system 1200 are shown and described herein. However, the computing system 1200 may include other components such as various batteries and power supplies, network interfaces, routers, switches, external storage systems, controllers, etc. Generally, the computing system 1200 may include any of a variety of hardware, software, and / or firmware components that are needed or considered desirable in performing the functions described herein. Similarly, the main device 1205, input device 1215, output device 1220, and memory device 1210, including memory controller 1240 and memory array 1245, may include other hardware, software, and / or firmware components that are needed or considered desirable in performing the functions described herein.

[0094] In one aspect of this disclosure, a memory device is disclosed. In some embodiments, the memory device includes memory cells for storing data. In some embodiments, the memory device includes an output driver coupled to the memory cells. In some embodiments, the output driver is configured to: generate an output signal indicating stored data in response to a sleep tracking signal indicating that the memory cells are in an operational state, and generate an output signal having a predetermined voltage independent of the stored data in response to a sleep tracking signal indicating that the memory cells are in a sleep state. In some embodiments, the sleep tracking signal is delayed from a sleep control signal that causes the memory cells to operate in a sleep or operational state.

[0095] In some embodiments, the output driver includes a NOR circuit, which includes a first input for receiving a signal indicating data stored in the memory cell and a second input for receiving a sleep tracking signal.

[0096] In some embodiments, the memory device further includes: a sleep control circuit for generating a sleep control signal to cause the memory cell to transition from a sleep state to an operating state at a first time, wherein a sleep tracking signal indicates that the memory cell transitions from the sleep state to the operating state at a second time after the first time, and wherein an output driver maintains an output signal at a predetermined voltage until the sleep tracking signal indicates that the memory cell has transitioned from the sleep state to the operating state at the second time.

[0097] In some embodiments, the memory device further includes: a delay circuit for delaying a sleep tracking signal; and a wake-up detection circuit coupled to the delay circuit, the wake-up detection circuit generating a wake-up completion signal based on the delayed sleep tracking signal, indicating whether the memory cell has completed transitioning from a sleep state to an operating state.

[0098] In some embodiments, the delay circuit includes one or more buffer circuits.

[0099] In some embodiments, the output driver includes a power switch for supplying a power supply voltage to one or more circuits in the output driver according to a sleep control signal.

[0100] In some embodiments, the memory device further includes a power supply detection circuit for generating a power supply detection signal indicating whether the supply voltage of the output driver has reached a threshold voltage.

[0101] In some embodiments, the wake-up detection circuit further generates a wake-up completion signal based on a power supply detection signal indicating that the supply voltage of the output driver has reached a threshold voltage.

[0102] In some embodiments, the wake-up detection circuit is an OR gate, which includes a first input for receiving a sleep tracking signal and a second input for receiving a power detection signal.

[0103] In another aspect of this disclosure, a memory device is disclosed. In some embodiments, the memory device includes memory cells for storing data. In some embodiments, the memory device includes a delay circuit configured to receive a sleep tracking signal indicating whether the memory cells are in a sleep state or an operational state, and to delay the sleep tracking signal to obtain a delayed sleep tracking signal. In some embodiments, the memory device includes a wake-up detection circuit coupled to the delay circuit. In some embodiments, the wake-up detection circuit is configured to generate a wake-up completion signal based on the delayed sleep tracking signal, indicating whether the transition of the memory cells from a sleep state to an operational state is complete.

[0104] In some embodiments, the memory device further includes an output driver coupled to the memory cell, the output driver generating an output signal indicating stored data based on a sleep tracking signal.

[0105] In some embodiments, the output driver includes a NOR circuit, which includes a first input for receiving a signal indicating stored data and a second input for receiving a sleep tracking signal.

[0106] In some embodiments, the output driver includes a power switch for supplying a power supply voltage to one or more circuits in the output driver according to a sleep control signal that causes a memory cell to transition from a sleep state to an operating state.

[0107] In some embodiments, the memory device further includes a power supply detection circuit for generating a power supply detection signal indicating whether the supply voltage of the output driver has reached a threshold voltage.

[0108] In some embodiments, the wake-up detection circuit further generates a wake-up completion signal based on a power supply detection signal indicating that the supply voltage of the output driver has reached a threshold voltage.

[0109] In some embodiments, the wake-up detection circuit is an OR gate, which includes a first input for receiving a sleep tracking signal and a second input for receiving a power detection signal.

[0110] In some embodiments, the delay circuit includes one or more buffer circuits.

[0111] In another aspect of this disclosure, a method of operating a memory device is disclosed. In some embodiments, the method includes generating a sleep control signal via a controller to transition a memory cell from a sleep state to an operating state at a first time. In some embodiments, the method includes detecting, via the controller, that the memory cell has transitioned from the sleep state to the operating state at a second time after the first time. In some embodiments, the method includes coupling an output driver to the memory cell via the controller to maintain an output signal with a predetermined voltage independent of the data stored in the memory cell until the second time. In some embodiments, the method includes generating, via the controller, an output driver after the second time to generate an output signal indicating the data stored in the memory cell.

[0112] In some embodiments, the method further includes: generating a sleep tracking signal by a controller indicating whether the memory cell is in a sleep state or an operating state; delaying the sleep tracking signal by the controller; and generating a wake-up completion signal by the controller based on the delayed sleep tracking signal, indicating whether the memory cell has completed transitioning from a sleep state to an operating state.

[0113] In some embodiments, the method further includes: generating a power detection signal by a controller indicating whether the supply voltage of the output driver has reached a threshold voltage; and wherein the controller further generates a wake-up completion signal based on the power detection signal.

[0114] The term "coupling" and its variations include joining two components directly or indirectly to each other. The term "electrical coupling" and its variations include connecting two components directly or indirectly to each other via a conductive material (e.g., a metal or copper trace). This connection can be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). This connection can be achieved by directly coupling two components to each other, coupling two components to each other using a single intermediate component, coupling two components to each other using any additional intermediate component, or coupling two components to each other using an intervening component integrally formed with one of the two components to form a single whole. If "coupling" or its variations are modified by an additional term (e.g., direct coupling), the general definition of "coupling" provided above is modified by the simple linguistic meaning of the additional term to have a narrower definition than the general definition of "coupling" provided above (e.g., "direct coupling" means connecting two components without any separate intermediate component). This coupling can be mechanical, electrical, or fluid.

[0115] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A memory device, comprising: Memory units for storing data; The controller is configured to generate a sleep control signal to cause the memory cell to transition from a sleep state to an operating state different from the sleep state at a first time, and to detect that the memory cell has transitioned from the sleep state to the operating state at a second time after the first time. as well as An output driver coupled to the memory cell, the output driver being used for: In response to a sleep tracking signal instructing the memory cell to transition to the operating state, an output signal indicating the stored data is generated, and In response to a sleep tracking signal indicating that the memory cell is in the sleep state, an output signal with a predetermined voltage is generated, independent of the stored data, wherein the output signal is maintained at the predetermined voltage until the second time. Wherein, the sleep tracking signal is a delay of the sleep control signal, and the sleep control signal causes the memory cell to operate in the sleep state or the operating state, and The controller causes the output driver to generate the output signal indicating the data stored by the memory cell after the second time.

2. The memory device according to claim 1, wherein, The output driver includes: The circuit includes a first input for receiving a signal indicating the data stored in the memory cell and a second input for receiving the sleep tracking signal.

3. The memory device according to claim 1, further comprising: A sleep control circuit is used to generate a sleep control signal, causing the memory cell to transition from the sleep state to the operating state at the first time point. Wherein, the sleep tracking signal indicates that the memory cell transitions from the sleep state to the operating state at a second time after the first time, and The output driver maintains the output signal at the predetermined voltage until the sleep tracking signal indicates that the memory cell has transitioned from the sleep state to the operating state at the second time.

4. The memory device according to claim 3, further comprising: Delay circuit, used to delay the sleep tracking signal; and A wake-up detection circuit, coupled to the delay circuit, generates a wake-up completion signal based on the delayed sleep tracking signal, indicating whether the memory cell has completed the transition from the sleep state to the operating state.

5. The memory device according to claim 4, wherein, The delay circuit includes one or more buffer circuits.

6. The memory device according to claim 4, wherein, The output driver includes: A power switch is used to provide a power supply voltage to one or more circuits in the output driver according to the sleep control signal.

7. The memory device according to claim 6, further comprising: A power supply detection circuit is used to generate a power supply detection signal indicating whether the supply voltage of the output driver has reached a threshold voltage.

8. The memory device according to claim 7, wherein, The wake-up detection circuit further generates the wake-up completion signal based on the power detection signal indicating that the supply voltage of the output driver has reached the threshold voltage.

9. The memory device according to claim 7, wherein, The wake-up detection circuit is an OR gate, and the OR gate includes: The first input to receive the sleep tracking signal, and The second input receives the power detection signal.

10. A memory device, comprising: Memory units for storing data; A controller is configured to generate a sleep control signal to cause the memory cell to transition from a sleep state to an operating state different from the sleep state at a first time, and the memory cell has transitioned from the sleep state to the operating state at a second time after the first time. Delay circuit, the delay circuit being used for: Receive a sleep tracking signal indicating whether the memory cell is in a sleep state or an operational state, and Delay the sleep tracking signal to obtain a delayed sleep tracking signal; and A wake-up detection circuit, coupled to the delay circuit, generates a wake-up completion signal based on the delayed sleep tracking signal, indicating whether the memory cell has completed the transition from the sleep state to the operating state; An output driver, coupled to the memory cell, is configured to generate an output signal with a predetermined voltage, independent of the stored data, in response to a sleep tracking signal indicating that the memory cell is in a sleep state, wherein the output signal maintains the predetermined voltage until the second time interval. The controller is also configured to cause the output driver to generate the output signal indicating the data stored by the memory unit after the second time.

11. The memory device according to claim 10, wherein, The output driver is also used to generate an output signal indicating the stored data based on the sleep tracking signal.

12. The memory device according to claim 11, wherein, The output driver includes: The circuit includes a first input for receiving a signal indicating the stored data and a second input for receiving the sleep tracking signal.

13. The memory device according to claim 11, wherein, The output driver includes: A power switch is used to provide a power supply voltage to one or more circuits in the output driver according to a sleep control signal that causes the memory cell to switch from the sleep state to the operating state.

14. The memory device of claim 13, further comprising: A power supply detection circuit is used to generate a power supply detection signal indicating whether the supply voltage of the output driver has reached a threshold voltage.

15. The memory device according to claim 14, wherein, The wake-up detection circuit further generates the wake-up completion signal based on the power detection signal indicating that the supply voltage of the output driver has reached the threshold voltage.

16. The memory device according to claim 14, wherein, The wake-up detection circuit is an OR gate, and the OR gate includes: The first input to receive the sleep tracking signal, and The second input receives the power detection signal.

17. The memory device according to claim 10, wherein, The delay circuit includes one or more buffer circuits.

18. A method of operating a memory device, comprising: The controller generates a sleep control signal to enable the memory cell to switch from a sleep state to an operating state different from the sleep state at the first moment. The controller detects that at a second time after the first time, the memory cell has transitioned from the sleep state to the operating state; The controller couples the output driver to the memory cell to maintain the output signal at a predetermined voltage until the second time, regardless of the data stored in the memory cell. as well as The controller causes the output driver to generate an output signal indicating the data stored in the memory cell after the second time.

19. The method of claim 18, further comprising: The controller generates a sleep tracking signal indicating whether the memory cell is in the sleep state or the operating state; The controller delays the sleep tracking signal; and Based on the delayed sleep tracking signal, the controller generates a wake-up completion signal indicating whether the memory cell has successfully transitioned from the sleep state to the operating state.

20. The method of claim 19, further comprising: The controller generates a power detection signal indicating whether the supply voltage of the output driver has reached a threshold voltage. and The controller further generates the wake-up completion signal based on the power detection signal.

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