Method of forming a semiconductor structure

Abstract

The application provides a semiconductor structure forming method, which comprises the following steps: providing a SiC substrate, and the SiC substrate is subjected to a first rapid thermal annealing treatment; forming a SiC epitaxial layer on the SiC substrate; performing a second rapid thermal annealing treatment on the SiC substrate and the SiC epitaxial layer, and when the first rapid thermal annealing treatment and the second rapid thermal annealing treatment are performed, the temperature of the SiC substrate and the SiC epitaxial layer is raised to a first temperature at a first time, and then the temperature of the SiC substrate and the SiC epitaxial layer is lowered to a second temperature; the operation of raising the temperature and then lowering the temperature of the SiC substrate and the SiC epitaxial layer is repeated for several times; forming a well region, a source region and a gate trench in the source region, the well region and the SiC epitaxial layer, and a third rapid thermal annealing is performed after the well region, the source region and the gate trench are formed. The semiconductor structure forming method provided by the application can improve the bipolar degradation problem of the SiC MOSFET.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, has been widely studied due to its wide bandgap, high critical breakdown field strength, high thermal conductivity, and high electron saturation drift velocity. It is expected to replace silicon (Si) devices and second-generation semiconductor devices in high-temperature, high-frequency, and high-power applications. Furthermore, since SiC is the only wide-bandgap semiconductor material that can be directly oxidized to silicon dioxide (SiO2), this will simplify the fabrication process of metal-oxide-semiconductor field-effect transistors (MOSFETs) using SiC. Therefore, SiC MOSFET devices have attracted considerable attention.

[0003] However, due to unresolved defects such as stacking faults in SiC epitaxial materials, the body diode is prone to bipolar degradation after long-term operation, which in turn degrades the electrical performance of the MOSFET, such as increased on-resistance and increased blocking leakage current. This poses a serious challenge to the performance and reliability of the entire power system. Summary of the Invention

[0004] The technical problem to be solved by this application is how to improve the bipolar degradation problem of SiC MOSFETs.

[0005] To address the aforementioned technical problems, this application provides a method for forming a semiconductor structure, comprising: providing a SiC substrate, wherein the SiC substrate undergoes a first rapid thermal annealing process; forming a SiC epitaxial layer on the SiC substrate; performing a second rapid thermal annealing process on the SiC substrate and the SiC epitaxial layer, wherein during the first and second rapid thermal annealing processes, the temperature is raised to a first temperature in a first instant, and then the temperature of the SiC substrate and the SiC epitaxial layer is cooled to a second temperature, and the operation of raising and lowering the temperature of the SiC substrate and the SiC epitaxial layer is repeated several times; forming a well region, a source region, and a gate trench located in the source region, the well region, and the SiC epitaxial layer; and performing a third rapid thermal annealing process after forming the well region, the source region, and the gate trench.

[0006] In some embodiments of this application, the SiC substrate and the SiC epitaxial layer are subjected to a heating and cooling operation at least five times.

[0007] In some embodiments of this application, during the third rapid thermal annealing process, the temperature is raised to the first temperature at the first time and then cooled to the second temperature.

[0008] In some embodiments of this application, the first time does not exceed 3 minutes, the first temperature is not less than 1600°C, and the second temperature does not exceed 800°C.

[0009] In some embodiments of this application, the first time is 1 min to 3 min, the first temperature is 1600℃ to 2000℃, and the second temperature is 500℃ to 800℃.

[0010] In some embodiments of this application, the first rapid thermal annealing process, the second rapid thermal annealing process, and the third rapid thermal annealing process are performed in any of the following atmospheres: Ar atmosphere, H2 atmosphere, SiH4 / Ar atmosphere, SiH4 / H2 atmosphere, Si2H6 / Ar atmosphere, Si2H6 / H2 atmosphere, Si3H8 / Ar atmosphere, or Si3H8 / H2 atmosphere.

[0011] In some embodiments of this application, the method of forming the well region, the source region, and the gate trench includes: forming the well region in the SiC epitaxial layer, wherein the well region further defines the width of the gate trench; forming the source region in the epitaxial layer in the well region and the well region; forming the gate trench in the source region, the well region, and the SiC epitaxial layer, and forming a gate structure in the gate trench.

[0012] In some embodiments of this application, after the source region is formed, heavy body regions are also formed on both sides of the source region.

[0013] In some embodiments of this application, the method of forming the well region, the source region, and the gate trench includes: forming the well region in the SiC epitaxial layer, wherein the well region further defines the width of the gate trench; forming the gate trench in the SiC epitaxial layer and the well region, and forming a gate structure in the gate trench; and forming a source region in the well region on both sides of the gate structure.

[0014] In some embodiments of this application, after the source region is formed, a heavy body region is also formed on the side of the source region away from the gate structure.

[0015] Compared with the prior art, the semiconductor structure formation method of this application has the following advantages:

[0016] Beneficial effects:

[0017] A first rapid thermal annealing process is performed on the SiC substrate. After forming a SiC epitaxial layer on the SiC substrate, a second rapid thermal annealing process is then performed on both the SiC substrate and the SiC epitaxial layer. This process is repeated multiple times, effectively converting most surface dislocations into through-screw dislocations, significantly improving device reliability and performance. A third rapid thermal annealing process is performed after forming the well region, source region, and gate trench. This process can largely recover lattice damage, further improving device reliability and performance.

[0018] During the first rapid thermal annealing process, the second rapid thermal annealing process, multiple repeated rapid thermal annealing operations, and the third rapid thermal annealing process, the temperature is raised to a first temperature in a first instant and then cooled to a second temperature, with the first time not exceeding 3 minutes, the first temperature not less than 1600℃, and the second temperature not exceeding 800℃. This enables the conversion of most substrate dislocations into through-screw dislocations with minimal lattice damage. Preferably, the first time is 1 to 3 minutes, the first temperature is 1600℃ to 2000℃, the second temperature is 500℃ to 800℃, and the operation of raising and lowering the temperature of the SiC substrate and the SiC epitaxial layer is repeated at least 5 times.

[0019] When performing the first, second, and third rapid thermal annealing processes, the processes are carried out in any of the following atmospheres: Ar, H2, SiH4 / Ar, SiH4 / H2, Si2H6 / Ar, Si2H6 / H2, Si3H8 / Ar, or Si3H8 / H2. This atmosphere enables the processed structure to have a relatively flat surface morphology, which is beneficial to improving the quality of the device structure and thus enhancing the device performance. Attached Figure Description

[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0021] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of this application;

[0022] Figures 2 to 10 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure formation method in the embodiments of this application. Detailed Implementation

[0023] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0024] This application provides a method for forming a semiconductor structure, which can be used to fabricate a SiC MOSFET, wherein the SiC MOSFET can be a trench double-diffused field-effect transistor (Trench MOSFET). (Reference) Figure 1 The method for forming the semiconductor structure includes the following steps:

[0025] S1: A SiC substrate is provided, and the SiC substrate undergoes a first rapid thermal annealing treatment;

[0026] S2: A SiC epitaxial layer is formed on the SiC substrate;

[0027] S3: Perform a second rapid thermal annealing process on the SiC substrate and the SiC epitaxial layer. When performing the first rapid thermal annealing process and the first rapid thermal annealing process, the temperature is raised to a first temperature in a first time, and then the temperature of the SiC substrate and the SiC epitaxial layer is cooled down to a second temperature. Repeat the operation of raising the temperature and then cooling down the SiC substrate and the SiC epitaxial layer several times.

[0028] S4: Form a well region, a source region, and a gate trench located in the source region, the well region, and the SiC epitaxial layer. After forming the well region, the source region, and the gate trench, a third rapid thermal annealing process is performed.

[0029] refer to Figure 2 A SiC substrate 100 is provided. The material of the SiC substrate 100 can be 4H-SiC, 6H-SiC, 3C-SiC, or 15R-SiC, etc. The SiC substrate 100 can be heavily doped, for example, the doping concentration can be 1E18cm⁻¹. -3 ~1E20cm -3 (i.e., 1×10) 18 cm -3 ~1×10 20 cm -3Furthermore, the SiC substrate 100 can be N-type doped or P-type doped, with the specific doping type depending on the device type (e.g., N-type MOSFET or P-type MOSFET). This application uses N-type doping as an example for illustration.

[0030] The SiC substrate 100 undergoes a first rapid thermal annealing process in a rapid heat treatment chamber. Compared to furnace tube annealing, rapid thermal annealing allows for thermal cycling within a short time, transforming base plane dislocations (BPDs) into threading screw dislocations (TSDs). During the first rapid thermal annealing process, the temperature is raised to a first temperature in a first time, and then the temperature of the SiC substrate 100 is cooled to a second temperature. In this embodiment, the first time does not exceed 3 minutes, the first temperature is not less than 1600°C, and the second temperature does not exceed 800°C. Preferably, the first time is 1 minute to 3 minutes, the first temperature is 1600°C to 2000°C, and the second temperature is 500°C to 800°C. For example, the first time can be 1 minute, 1.5 minutes, 2 minutes, 2.5 minutes, 3 minutes, or any time value between these intervals. The first temperature can be 1600℃, 1650℃, 1700℃, 1750℃, 1800℃, 1850℃, 1900℃, 1950℃, 2000℃, or any temperature value between these temperature nodes. The second temperature can be 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, or any temperature value between these temperature nodes. The atmosphere during the first rapid thermal annealing process affects the surface morphology of the structure being processed (such as the SiC substrate and the SiC epitaxial layer). The first rapid thermal annealing process is carried out in any of the following atmospheres: Ar atmosphere, H2 atmosphere, SiH4 / Ar atmosphere, SiH4 / H2 atmosphere, Si2H6 / Ar atmosphere, Si2H6 / H2 atmosphere, Si3H8 / Ar atmosphere, or Si3H8 / H2 atmosphere. When using this atmosphere, the SiC substrate and the SiC epitaxial layer have a relatively flat surface morphology, which is beneficial to improving the quality of the device structure formed on the SiC substrate and the SiC epitaxial layer, thereby improving the device performance.

[0031] In step S2, a SiC epitaxial layer 200 is formed on the SiC substrate 100. The SiC epitaxial layer 200 can be formed by an epitaxial growth process. The doping type of the SiC epitaxial layer 200 is the same as that of the SiC substrate 100, and the doping concentration of the SiC epitaxial layer 200 can be lower than that of the SiC substrate 100. For example, the doping concentration of the SiC epitaxial layer 200 can be 1E14cm⁻¹.-3 Up to 1E16cm -3 .

[0032] After forming the SiC epitaxial layer 200, step 3 is performed. A second rapid thermal annealing process is applied to the SiC substrate 100 and the SiC epitaxial layer 200. During this process, the SiC substrate 100 and the SiC epitaxial layer 200 are heated to a first temperature in a first instant, and then cooled to a second temperature. The first time does not exceed 3 minutes, the first temperature is not less than 1600°C, and the second temperature does not exceed 800°C. Preferably, the first time is 1 minute to 3 minutes, the first temperature is 1600°C to 2000°C, and the second temperature is 500°C to 800°C. For example, the first time can be 1 minute, 1.5 minutes, 2 minutes, 2.5 minutes, 3 minutes, or any time value between these intervals. The first temperature can be 1600℃, 1650℃, 1700℃, 1750℃, 1800℃, 1850℃, 1900℃, 1950℃, 2000℃, or any temperature value between these temperature nodes. The second temperature can be 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, or any temperature value between these temperature nodes. The second rapid thermal annealing treatment can be performed in any of the following atmospheres: Ar atmosphere, H2 atmosphere, SiH4 / Ar atmosphere, SiH4 / H2 atmosphere, Si2H6 / Ar atmosphere, Si2H6 / H2 atmosphere, Si3H8 / Ar atmosphere, or Si3H8 / H2 atmosphere. The operation of heating and then cooling the SiC substrate 100 and the SiC epitaxial layer 200 is repeated several times. In this embodiment, the SiC substrate 100 and the SiC epitaxial layer 200 are subjected to a heating-and-cooling operation at least five times. For example, the number of repetitions can be 5, 6, 7, 8, 9, 10, etc. The more repetitions, the higher the conversion rate from BPD to TSD.

[0033] Step S3 is performed to form a well region, a source region, and a gate trench located in the source region, the well region, and the SiC epitaxial layer. In this embodiment, the method for forming the well region, the source region, and the gate trench may include:

[0034] Step S31: The well region is formed in the SiC epitaxial layer, and the well region extends from the surface of the SiC epitaxial layer into the SiC epitaxial layer;

[0035] Step S32: The source region is formed in the well region, and the source region extends from the surface of the well region into the well region;

[0036] Step S33: Form the gate trench in the source region, the well region, and the SiC epitaxial layer, and form a gate structure in the gate trench.

[0037] Continue to refer to Figure 2 A well region 300 is formed in the SiC epitaxial layer 200. The well region 300 extends from the surface of the SiC epitaxial layer 200 into the SiC epitaxial layer 200, and the well region 300 has a doping type opposite to that of the SiC substrate 100 and the SiC epitaxial layer 200. The process for forming the well region 300 can be an ion implantation process, with the ion implantation temperature being 500℃~600℃ and the doping concentration being, for example, 3E17cm⁻¹. -3 ~1E21cm -3 In this embodiment, the well region 300 can define the width of the gate trench. In other embodiments, the well region 300 does not reserve the position of the gate trench. After ion implantation forms the well region 300, a third rapid thermal annealing process is performed. During the third rapid thermal annealing process, the temperature is raised to the first temperature in the first time interval and then cooled to the second temperature. The first time interval does not exceed 3 minutes, the first temperature is not less than 1600°C, and the second temperature does not exceed 800°C. Preferably, the first time interval is 1 minute to 3 minutes, the first temperature is 1600°C to 2000°C, and the second temperature is 500°C to 800°C. For example, the first time interval can be 1 minute, 1.5 minutes, 2 minutes, 2.5 minutes, 3 minutes, or any time value between these intervals. The first temperature can be 1600℃, 1650℃, 1700℃, 1750℃, 1800℃, 1850℃, 1900℃, 1950℃, 2000℃, or any temperature value between these temperature nodes. The second temperature can be 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, or any temperature value between these temperature nodes. The third rapid thermal annealing treatment can be performed in any of the following atmospheres: Ar atmosphere, H2 atmosphere, SiH4 / Ar atmosphere, SiH4 / H2 atmosphere, Si2H6 / Ar atmosphere, Si2H6 / H2 atmosphere, Si3H8 / Ar atmosphere, or Si3H8 / H2 atmosphere. The third rapid thermal annealing treatment can effectively restore lattice damage.

[0038] refer to Figure 3 Source regions 400 are formed in the well regions 300 and in the epitaxial layers 200 between the well regions 300. The formation of the source regions 400 can be an ion implantation process, and the ion implantation temperature can be 500℃~600℃. The type of implanted ions is opposite to the type of doped ions in the well regions 300, and the ion implantation concentration is 3E16cm⁻¹.-3 ~2E17cm -3 After the source region 400 is formed, the third rapid thermal annealing process is also performed. During the third rapid thermal annealing process, the temperature is raised to the first temperature within the first time interval, and then lowered to the second temperature. The first time interval does not exceed 3 minutes, the first temperature is not less than 1600℃, and the second temperature does not exceed 800℃. Preferably, the first time interval is 1 minute to 3 minutes, the first temperature is 1600℃ to 2000℃, and the second temperature is 500℃ to 800℃. For example, the first time interval can be 1 minute, 1.5 minutes, 2 minutes, 2.5 minutes, 3 minutes, or any time value between these intervals. The first temperature can be 1600℃, 1650℃, 1700℃, 1750℃, 1800℃, 1850℃, 1900℃, 1950℃, 2000℃, or any temperature value between these intervals. The second temperature can be 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, or any temperature value between these temperature nodes. The third rapid thermal annealing treatment can be performed in any of the following atmospheres: Ar atmosphere, H2 atmosphere, SiH4 / Ar atmosphere, SiH4 / H2 atmosphere, Si2H6 / Ar atmosphere, Si2H6 / H2 atmosphere, Si3H8 / Ar atmosphere, or Si3H8 / H2 atmosphere. The third rapid thermal annealing treatment can restore lattice damage.

[0039] After forming the source region 400, a heavy body region 500 can be formed in the well regions 300 on both sides of the source region 400 using an ion implantation process. The doping type of the heavy body region 500 is the same as that of the well region 300, and the doping concentration of the heavy body region 500 is greater than that of the well region 300. The heavy body region 500 can function as an ohmic contact. After forming the heavy body region 500, the third rapid thermal annealing treatment can also be performed to eliminate lattice damage. Specifically, the temperature is raised to the first temperature in the first time interval and then cooled to the second temperature. The first time interval does not exceed 3 minutes, the first temperature is not less than 1600°C, and the second temperature does not exceed 800°C. Preferably, the first time interval is 1 minute to 3 minutes, the first temperature is 1600°C to 2000°C, and the second temperature is 500°C to 800°C. For example, the first time interval can be 1 minute, 1.5 minutes, 2 minutes, 2.5 minutes, 3 minutes, or any time value between these intervals. The first temperature can be 1600℃, 1650℃, 1700℃, 1750℃, 1800℃, 1850℃, 1900℃, 1950℃, 2000℃, or any temperature value between these temperature nodes. The second temperature can be 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, or any temperature value between these temperature nodes. The atmosphere for the third rapid thermal annealing treatment can be Ar, H2, SiH4 / Ar, SiH4 / H2, Si2H6 / Ar, Si2H6 / H2, Si3H8 / Ar, or Si3H8 / H2.

[0040] refer to Figure 4A gate trench 600 is formed in the source region 400, the well region 300, and the SiC epitaxial layer 200. The process for forming the gate trench 600 is a conventional etching process. After forming the gate trench 600, a third rapid thermal annealing process is performed to eliminate lattice damage. During the third rapid thermal annealing process, the temperature is raised to the first temperature in the first time interval and then cooled to the second temperature. The first time interval does not exceed 3 minutes, the first temperature is not less than 1600°C, and the second temperature does not exceed 800°C. Preferably, the first time interval is 1 minute to 3 minutes, the first temperature is 1600°C to 2000°C, and the second temperature is 500°C to 800°C. For example, the first time interval can be 1 minute, 1.5 minutes, 2 minutes, 2.5 minutes, 3 minutes, or any time value between these intervals. The first temperature can be 1600℃, 1650℃, 1700℃, 1750℃, 1800℃, 1850℃, 1900℃, 1950℃, 2000℃, or any temperature value between these temperature nodes. The second temperature can be 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, or any temperature value between these temperature nodes. The third rapid thermal annealing treatment can be performed in any of the following atmospheres: Ar atmosphere, H2 atmosphere, SiH4 / Ar atmosphere, SiH4 / H2 atmosphere, Si2H6 / Ar atmosphere, Si2H6 / H2 atmosphere, Si3H8 / Ar atmosphere, or Si3H8 / H2 atmosphere.

[0041] refer to Figure 5 A gate structure is formed in the gate trench 600, comprising a gate dielectric layer 710 located on the sidewalls and bottom of the gate trench 600 and a gate layer 720 located on the surface of the gate dielectric layer 710. The gate dielectric layer 710 may be a single-layer or multi-layer structure. The material of the gate dielectric layer 710 may include SiO2 or a high-K material with a dielectric constant greater than 3.9, such as Al2O3. The gate dielectric layer 710 may be formed by deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). The material of the gate layer 720 may include polysilicon, and the gate layer 720 may be formed by deposition processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0042] In some other embodiments of this application, the formation order of the well region, the source region, and the gate trench is slightly different. (See reference...) Figure 6 The well region 300 is formed in the SiC epitaxial layer 200, and the well region 300 also defines the width of the gate trench. (Reference) Figure 7The gate trench 600 is formed in the SiC epitaxial layer 200 and the well region 300. (Reference) Figure 8 A gate dielectric layer 710 is formed on the sidewalls and bottom of the gate trench 600, and a gate layer 720 filling the gate trench 600 is formed on the surface of the gate dielectric layer 710. (Reference) Figure 9 Source regions 400 are formed in the well regions 300 on both sides of the gate structure, and then a heavy body region 500 is formed on the side of the source regions 400 away from the gate structure.

[0043] refer to Figure 10 In subsequent processes, an insulating layer 730 can be formed on the gate structure, a source electrode 800 can be formed on the source region 400, the heavy body region 500 and the insulating layer 730, and a drain electrode 900 can be formed on the other surface of the SiC substrate 100.

[0044] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0045] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0046] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0047] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0048] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A SiC substrate is provided, and the SiC substrate undergoes a first rapid thermal annealing process. During the first rapid thermal annealing process, the temperature is raised to a first temperature in a first time, and then the temperature of the SiC substrate is cooled to a second temperature to transform the base surface dislocations of the SiC substrate into through-screw dislocations. A SiC epitaxial layer is formed on the SiC substrate; The SiC substrate and the SiC epitaxial layer are subjected to a second rapid thermal annealing process. During the second rapid thermal annealing process, the temperature is raised to a first temperature in a first time, and then the temperature of the SiC substrate and the SiC epitaxial layer is cooled to a second temperature. The operation of raising the temperature and then cooling the SiC substrate and the SiC epitaxial layer is repeated several times to improve the conversion rate of the base surface dislocations of the SiC substrate and the SiC epitaxial layer into through-screw dislocations. A well region, a source region, and a gate trench located in the source region, the well region, and the SiC epitaxial layer are formed. A third rapid thermal annealing process is performed after the formation of the well region, the source region, and the gate trench.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Repeat the process of heating and cooling the SiC substrate and the SiC epitaxial layer at least 5 times.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, During the third rapid thermal annealing process, the temperature is raised to the first temperature at the first time and then lowered to the second temperature.

4. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The first time does not exceed 3 minutes, the first temperature is not less than 1600℃, and the second temperature does not exceed 800℃.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The first time is 1 min to 3 min, the first temperature is 1600℃ to 2000℃, and the second temperature is 500℃ to 800℃.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The first rapid thermal annealing treatment, the second rapid thermal annealing treatment, and the third rapid thermal annealing treatment are carried out in any of the following atmospheres: Ar atmosphere, H2 atmosphere, SiH4 / Ar atmosphere, SiH4 / H2 atmosphere, Si2H6 / Ar atmosphere, Si2H6 / H2 atmosphere, Si3H8 / Ar atmosphere, or Si3H8 / H2 atmosphere.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the well region, the source region, and the gate trench includes: The well region is formed in the SiC epitaxial layer, and the well region also defines the width of the gate trench; The source region is formed in the well region and in the epitaxial layer between the well regions; The gate trench is formed in the source region, the well region, and the SiC epitaxial layer, and a gate structure is formed in the gate trench.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, After the source region is formed, heavy body regions are also formed on both sides of the source region.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the well region, the source region, and the gate trench includes: The well region is formed in the SiC epitaxial layer, and the well region also defines the width of the gate trench; The gate trench is formed in the SiC epitaxial layer and the well region, and a gate structure is formed in the gate trench; Source regions are formed in the well regions on both sides of the gate structure.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, After the source region is formed, a heavy body region is also formed on the side of the source region away from the gate structure.

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