Dual-gate large-resistance integrated device, preparation method and radio frequency front end

Abstract

The application discloses a double-gate large-resistance integrated device, a preparation method and a radio frequency front end. The device comprises, from bottom to top, a substrate layer, a buffer layer, a channel layer and a barrier layer, wherein the barrier layer is provided with a passivation layer; the passivation layer is provided with two grooves etched to the upper surface of the barrier layer, T-shaped radio frequency gates used as power amplifiers and T-shaped direct current gates used as switches are respectively formed in the two grooves, the gate pins of the T-shaped radio frequency gates and the T-shaped direct current gates are inserted into the grooves, and the gate caps are covered on the gate pins and the passivation layer on the two sides of the grooves; the direct current gates are connected with gate resistors with a resistance greater than 10kΩ; the source and the drain are respectively arranged on the channel layer and at the two ends of the barrier layer; different voltages are applied to the T-shaped direct current gates, the opening degree of the two-dimensional electron gas channel can be controlled, and the gain adjustment of the power amplifier device can be realized. The radio frequency front end chip area can be greatly reduced, the breakdown voltage can be improved, the insertion loss can be reduced, and the isolation stability can be improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and particularly relates to a double-gate large-resistance integrated device, a preparation method and a radio frequency front end. BACKGROUND

[0002] As a component for receiving and transmitting electromagnetic wave signals, an antenna is a core accessory of some terminal devices such as mobile phones. As a new generation of communication technology, 5G brings many innovations in technology and standards with the increase in frequency bands, which also leads to the difficulty in the design and manufacture of antennas, prompting the development of antennas in the direction of high complexity and integration. With the increase in the complexity and area of the radio frequency front-end switch circuit, the isolation and insertion loss will deteriorate to a certain extent.

[0003] Massive MIMO will use a large number of radio frequency switches. Radio frequency switches play a role in controlling the switching of microwave signal channels in the circuit, and their role is particularly important in the radio frequency transceiver front end. The structure of the radio frequency transceiver front end is basically connected by radio frequency switches. The isolation, insertion loss and linearity of the radio frequency switch determine the effect of the radio frequency receiving signal. Generally speaking, improving the performance of the radio frequency switch can be approached from two aspects. On the one hand, the topology of the radio frequency switch circuit can be changed. In 2019, Sinan Osmanoglu et al. of the Department of Electrical and Electronic Engineering of Bilkent University in Turkey designed, analyzed and measured the performance of three different topologies of single-pole double-throw radio frequency switches based on high-power, low-loss and high-isolation GaN high electron mobility transistors. The advantages and disadvantages of the three structures are introduced respectively. On the other hand, the performance can be optimized by changing the device structure of the radio frequency switch. In 2014, NGES reported the development of a new transistor structure based on a gallium nitride superlattice channel with a 3D gate, called superlattice castellated field effect transistor (SLCFET). By combining excellent radio frequency switch performance with many ideal aspects of field effect transistor-based switches, products with excellent broadband loss and isolation performance, high reliability, fast switching speed and low power consumption are obtained. In the direction of double-gate structure, Yangling et al. of the Microelectronics College of Xi'an University of Electronic Science and Technology studied the subthreshold characteristics of gate-embedded high electron mobility transistors using a double-gate architecture in 2017, and applied them to obtain a lower subthreshold swing. In 2021, Lin Daijie et al. of Taiwan proposed a double-gate transistor structure to suppress the increase in dynamic on-resistance. Under appropriate fixed voltage, the auxiliary gate can induce additional electrons to compensate for the loss of channel carriers during the switching of the main gate, thereby reducing the dynamic on-resistance.

[0004] The prior art only focuses on the switching device part, regardless of optimizing the device structure or the circuit topology, and rarely considers the power amplifier device to achieve simultaneous optimization. The prior art adopts traditional device interconnection, which has large area, slow switching speed and large loss. Even if a double-gate structure is adopted, it is not applied to the transmission mode of the radio frequency front end, and the direct current gate resistor is small and easy to break down. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a double-gate large-resistance integrated device, a preparation method and a radio frequency front end.

[0006] A double-gate large-resistance integrated device, from bottom to top, comprises a substrate layer, a buffer layer, a channel layer and a barrier layer, wherein,

[0007] A passivation layer is arranged on the barrier layer;

[0008] Two grooves etched to the upper surface of the barrier layer are arranged on the passivation layer, a T-shaped radio frequency gate used as a power amplifier and a T-shaped direct current gate used as a switch are respectively formed in the two grooves, the gate pins of the T-shaped radio frequency gate and the T-shaped direct current gate are inserted into the grooves, and the gate caps are arranged on the gate pins and the passivation layer on both sides of the grooves;

[0009] A source and a drain are respectively arranged at both ends of the channel layer and the barrier layer;

[0010] The double-gate integrated device is connected with a gate resistor with a resistance greater than 10kΩ through the direct current gate;

[0011] A source and a drain are respectively arranged at both ends of the channel layer and the barrier layer;

[0012] Different voltages are applied to the T-shaped direct current gate to control the opening degree of the two-dimensional electron gas channel to realize the gain adjustment of the power amplifier device.

[0013] In an embodiment of the application, the gate resistor is a metal resistor, and the metal resistor is formed by depositing metal on a first preset resistance pattern area on the passivation layer; the first preset resistance pattern area is arranged on the passivation layer on the upper surface of the wafer and outside the device where the source and the drain are located.

[0014] In an embodiment of the application, the metal resistor is a NiCr alloy thin film resistor.

[0015] In one embodiment of the present application, the gate resistor is a gate resistor effect area, and the gate resistor effect area is a part of the wafer included in a second preset resistance pattern area formed by implanting ions into the wafer outside the second preset resistance pattern area on the surface of the barrier layer of the wafer and outside the device where the source and the drain are located.

[0016] In one embodiment of the present application, the T-shaped DC gate and the gate resistor are interconnected through interconnection metal.

[0017] In one embodiment of the present application, the material of the passivation layer is SiN, and the thickness is 120 nm.

[0018] In one embodiment of the present application, the materials of the T-shaped RF gate and the T-shaped DC gate are both Ni / Au, wherein the thickness of Ni is 45 nm, and the thickness of Au is 400 nm.

[0019] A preparation method of a double-gate large-resistor integrated device, comprising:

[0020] Obtaining a wafer, the wafer comprising, from bottom to top, a substrate layer, a buffer layer, a channel layer, and a barrier layer;

[0021] Preparing a source and a drain in a source pattern area and a drain pattern area on the barrier layer;

[0022] Growth of a passivation layer on the barrier layer and the source and the drain;

[0023] Etching the passivation layer covering the source and the drain to expose the source and the drain;

[0024] Etching two grooves of different depths on the passivation layer to the upper surface of the barrier layer, and performing gate metal evaporation in the two grooves respectively to form a T-shaped RF gate used as a power amplifier and a T-shaped DC gate used as a switch, the gate legs of the T-shaped RF gate and the T-shaped DC gate are inserted into the grooves, and the gate caps are covered on the gate legs and the passivation layer on both sides of the grooves; the T-shaped DC gate is used to control the opening degree of the two-dimensional electron gas channel when different voltages are applied thereto, so as to realize the gain adjustment of the power amplifier device;

[0025] Depositing metal on a first preset resistance pattern area on the passivation layer to form a gate resistor, and the resistance of the gate resistor is greater than 10 kΩ; the first preset resistance pattern area is arranged on the passivation layer on the upper surface of the wafer and outside the device where the source and the drain are located;

[0026] Depositing interconnection metal between the T-shaped DC gate and the gate resistor to realize the interconnection of the DC gate and the gate resistor.

[0027] A preparation method of a double-gate large-resistance integrated device, comprising:

[0028] A wafer is obtained, which comprises, from bottom to top, a substrate layer, a buffer layer, a channel layer and a barrier layer;

[0029] A source and a drain are prepared in source and drain pattern areas on the barrier layer;

[0030] Ions are implanted in the wafer outside a second preset resistance pattern area on the surface of the barrier layer and outside the device where the source and the drain are located, and the wafer part contained in the second preset resistance pattern area forms a gate resistance effect area;

[0031] A passivation layer is grown on the barrier layer and the source and the drain;

[0032] The passivation layer covering the source and the drain is etched to expose the source and the drain;

[0033] Two grooves with different depths to the upper surface of the barrier layer are etched on the passivation layer, and gate metal evaporation is performed in the two grooves respectively to form a T-shaped radio frequency gate used as a power amplifier and a T-shaped direct current gate used as a switch, the gate legs of the T-shaped radio frequency gate and the T-shaped direct current gate are inserted into the grooves, and the gate caps are covered on the gate legs and the passivation layer on both sides of the grooves; and the T-shaped direct current gate is connected with the gate resistance effect area; the T-shaped direct current gate is used to control the opening degree of the two-dimensional electron gas channel when different voltages are applied thereto, so as to realize the gain adjustment of the power amplifier device.

[0034] A radio frequency front end, comprising the double-gate large-resistance integrated device of any one of the above or the double-gate large-resistance integrated device prepared by the preparation method of any one of the above.

[0035] Compared with the prior art, the double-gate large-resistance integrated device of the embodiment of the present application has the following beneficial effects:

[0036] The double-gate large-resistance integrated device of the embodiment of the present application sets two grooves on the passivation layer, and forms a T-shaped radio frequency gate used as a power amplifier and a T-shaped direct current gate used as a switch in the grooves, which is equivalent to integrating the power amplifier and the radio frequency switch on one device through the double-gate structure, so that the number of radio frequency front end devices can be greatly reduced, and the chip area can be greatly reduced; and the T-shaped direct current connection large resistance of more than 10kΩ can improve the breakdown voltage, so that the working range of the device is wider, the insertion loss is reduced, and the isolation stability is improved. In addition, by applying different voltages to the direct current gate, the opening degree of the two-dimensional electron gas channel will be different, so that the gain of the power amplifier device can be conveniently adjusted. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1is a structure schematic diagram of a double-gate large-resistance integrated device provided by an embodiment of the present application;

[0038] Figure 2 is a top view of a double-gate large-resistance integrated device provided by an embodiment of the present application;

[0039] Figure 3 is a structure schematic diagram of another double-gate large-resistance integrated device provided by an embodiment of the present application;

[0040] Figure 4 is a top view of another double-gate large-resistance integrated device provided by an embodiment of the present application;

[0041] Figure 5 is a flowchart of a preparation method of a double-gate large-resistance integrated device provided by an embodiment of the present application;

[0042] Figure 6 is a flowchart of another preparation method of a double-gate large-resistance integrated device provided by an embodiment of the present application;

[0043] Figure 7 is a structure schematic diagram of a radio frequency front end provided by an embodiment of the present application;

[0044] Figure 8 is a structure schematic diagram of a traditional radio frequency front end;

[0045] Figure 9 is a design layout of a radio frequency front end device provided by an embodiment of the present application.

[0046] Reference signs: 1-substrate layer; 2-buffer layer; 3-channel layer; 4-potential barrier layer; 5-passivation layer; 6-source electrode; 7-drain electrode; 8-T-shaped radio frequency gate; 9-T-shaped direct current gate; 10-metal resistance; 11-first preset resistance pattern area; 12-gate resistance effect area; 13-second preset resistance pattern area. DETAILED DESCRIPTION

[0047] The present application will be further described in detail below with specific embodiments, but the embodiments of the present application are not limited thereto.

[0048] Please refer to Figure 1 , Figure 1It is a structure schematic diagram of a double-gate large-resistance integrated device provided by the embodiment of the present application, and the double-gate large-resistance integrated device comprises, from bottom to top, a substrate layer 1, a buffer layer 2, a channel layer 3 and a barrier layer 4. It should be noted that the substrate layer 1, the buffer layer 2, the channel layer 3 and the barrier layer 4 can be directly purchased wafers, that is, the scheme of the present application is directly processed on any wafer; or the substrate layer 1, the buffer layer 2, the channel layer 3 and the barrier layer 4 can be prepared according to the wafer preparation process. The material of the substrate layer 1 is preferably SiC, the material of the buffer layer 2 is preferably GaN, the material of the channel layer 3 is preferably GaN, and the material of the barrier layer 4 is preferably AlGaN.

[0049] The barrier layer 4 of the embodiment of the present application is provided with a passivation layer 5, and the material of the passivation layer 5 is preferably SiN and the thickness is 120 nm. The channel layer 3 of the embodiment of the present application is provided with a source electrode 6 and a drain electrode 7 at both ends of the barrier layer 4.

[0050] The passivation layer 5 is provided with two grooves etched to the upper surface of the barrier layer 4, and a T-shaped radio frequency gate 8 (power amplifier) used as a power amplifier and a T-shaped direct current gate 9 (radio frequency switch) used as a switch are respectively formed in the two grooves, and the gate pins of the T-shaped radio frequency gate 8 and the T-shaped direct current gate 9 are inserted into the grooves, and the gate caps are covered on the gate pins and the passivation layer 5 on both sides of the grooves. The direct current gate is connected with a gate resistor with a resistance greater than 10kΩ, and the large resistance connected with the direct current gate can increase the breakdown voltage, reduce the insertion loss and improve the isolation. The materials of the T-shaped radio frequency gate 8 and the T-shaped direct current gate 9 are preferably both Ni / Au, wherein the thickness of Ni is 45 nm and the thickness of Au is 400 nm.

[0051] Different voltages are applied to the T-shaped direct current gate 9 to control the opening degree of the two-dimensional electron gas channel to realize the gain adjustment of the power amplifier device. Since the two-dimensional electron gas is generated between the barrier layer 4 and the channel layer 3 due to polarization, the voltage applied to the direct current gate changes the polarization strength, and in addition, the voltage also affects the heterojunction between the two layers, so that the thickness of the depletion region changes. When the voltage applied to the direct current gate is less than the threshold voltage, the opening and closing effect is achieved, and when the voltage applied to the direct current gate is greater than the threshold voltage, the two-dimensional electron gas channel is opened, and the opening degree and the gain are different with different voltages. Therefore, by controlling the different voltages applied to the T-shaped direct current gate 9, the opening degree of the two-dimensional electron gas channel can be controlled to realize the gain adjustment of the power amplifier device.

[0052] The double-gate large-resistance integrated device of the embodiment of the present application is provided with two grooves on the passivation layer 5, and a T-shaped radio frequency gate 8 used as a power amplifier and a T-shaped direct current gate 9 used as a switch are formed in the grooves, which is equivalent to integrating the power amplifier and the radio frequency switch on one device through a double-gate structure, so that the number of radio frequency front-end devices can be greatly reduced, and the chip area can be greatly reduced; the T-shaped direct current gate 9 is connected with a large resistance of more than 10 kΩ, so that the breakdown voltage can be improved, the working range of the device is wider, the insertion loss is reduced, and the isolation stability is improved. In addition, by applying different voltages to the direct current gate, the opening degree of the two-dimensional electron gas channel will be different, so that the gain of the power amplifier device can be conveniently adjusted.

[0053] The large resistance connected with the T-shaped direct current gate 9 in the double-gate large-resistance integrated device provided by the embodiment of the present application can be realized in two ways. One structure is shown in Figure 1 , in which the gate resistance is a metal resistance 10 formed by depositing metal on a first preset resistance pattern area 11 on the passivation layer 5; the first preset resistance pattern area 11 is arranged on the passivation layer 5 on the upper surface of the wafer and outside the device in which the source 6 and the drain 7 are located. The metal resistance 10 is preferably a NiCr alloy thin film resistance; the T-shaped direct current gate 9 and the gate resistance are interconnected through interconnection metal. The structure diagram of the first preset resistance pattern area 11 and the gate resistance is shown in Figure 2 .

[0054] Please refer to Figure 3 and Figure 4 , Figure 3 is another structure diagram of a double-gate large-resistance integrated device provided by the embodiment of the present application, Figure 4 is a top view of another double-gate large-resistance integrated device provided by the embodiment of the present application; the difference between the device and Figure 1 is that the gate resistance is not a metal resistance 10 formed by depositing metal on the first preset resistance pattern area 11, but a gate resistance effect area 12, which is a wafer part contained in a second preset resistance pattern area formed by implanting ions on the wafer outside the second preset resistance pattern area on the surface of the barrier layer 4 and outside the device in which the source 6 and the drain 7 are located. In this structure, the implanted ions can be argon ions, which diffuse to the layers below the wafer, and the diffusion depth is at least the sum of the thicknesses of the barrier layer 4 and the channel layer 3, and the two-dimensional electron gas in the passive area outside the device is blocked. The gate resistance effect area 12 has two-dimensional electron gas, which can play a voltage control role on the direct current gate, and the resistance is much larger than 10 KΩ, which can also be used as an implementation way of the gate large resistance, and plays a role of high isolation.

[0055] Please refer to Figure 5 , Figure 5is a flowchart of a preparation method of a double-gate large-resistance integrated device provided by an embodiment of the present application, and the method comprises the following steps:

[0056] S101, a wafer is acquired, and the wafer comprises, from bottom to top, a substrate layer 1, a buffer layer 2, a channel layer 3 and a barrier layer 4.

[0057] The wafer in this step can be a wafer directly purchased on the market, that is, the scheme of the present application is directly processed on any wafer; or the substrate layer 1, the buffer layer 2, the channel layer 3 and the barrier layer 4 can be sequentially and respectively prepared according to the preparation process of the wafer; the material of the substrate layer 1 is preferably SiC, the material of the buffer layer 2 is preferably GaN, the material of the channel layer 3 is preferably GaN, and the material of the barrier layer 4 is preferably AlGaN.

[0058] S102, a source electrode 6 and a drain electrode 7 are prepared in a source pattern area and a drain pattern area on the barrier layer 4.

[0059] This step can specifically comprise the following steps.

[0060] The source pattern area and the drain pattern area are etched on the barrier layer 4 by using a photolithography process to prepare source and drain ohmic metals, and the photolithography process uses SF6 photoresist first and then EPI621 photoresist; then ohmic metal evaporation is performed in the source pattern area and the drain pattern area, the metal is Ti / Al / Ni / Au, and the thickness is 20 / 160 / 55 / 45 nm; finally, ohmic contact annealing is performed to obtain the source electrode 6 and the drain electrode 7.

[0061] S103, a passivation layer 5 is grown on the barrier layer 4 and the source electrode 6 and the drain electrode 7.

[0062] This step can specifically comprise the following steps.

[0063] PECVD technology is used to grow the SiN passivation layer 5 on the barrier layer 4 and the source electrode 6 and the drain electrode 7, and the thickness is 120 nm.

[0064] S104, the passivation layer 5 covering the source electrode 6 and the drain electrode 7 is etched away to expose the source electrode 6 and the drain electrode 7.

[0065] This step can specifically comprise the following steps.

[0066] After the passivation, aperture photolithography is performed on the surface of the SiN passivation layer 5, and EPI621 photoresist is used. Then, aperture F-based etching is performed by using an ICP etching device, and the etching depth is until the upper surface of the source electrode 6 and the drain electrode 7, so as to expose the source and drain ohmic metals covered by the SiN.

[0067] S105, etching two grooves of different depths on the passivation layer 5 to the upper surface of the barrier layer 4, and performing gate metal evaporation in the two grooves respectively to form a T-shaped radio frequency gate 8 used as a power amplifier and a T-shaped direct current gate 9 used as a switch, the gate legs of the T-shaped radio frequency gate 8 and the T-shaped direct current gate 9 are inserted into the grooves, and the gate cap is covered on the gate legs and the passivation layer 5 on both sides of the grooves; the T-shaped direct current gate 9 is used to control the opening degree of the two-dimensional electron gas channel when different voltages are applied thereto, so as to realize the gain adjustment of the power amplifier device.

[0068] In this step, the following steps can be specifically included:

[0069] In this step, the following steps can be specifically included:

[0070] S106, depositing metal on the first preset resistance pattern area 11 on the passivation layer 5 to form a gate resistance, and the resistance value of the gate resistance is greater than 10kΩ.

[0071] In this step, the following steps can be specifically included:

[0072] In this step, the following steps can be specifically included:

[0073] S107, depositing interconnection metal between the T-shaped direct current gate 9 and the gate resistance to realize the interconnection of the direct current gate and the gate resistance.

[0074] The preparation method of the double-gate large-resistance integrated device provided by the embodiment of the application can set two grooves on the passivation layer 5, and form a T-shaped radio frequency gate 8 used as a power amplifier and a T-shaped direct current gate 9 used as a switch in the grooves, which is equivalent to integrating the power amplifier and the radio frequency switch through a double-gate structure on one device, so that the number of radio frequency front-end devices can be greatly reduced, and the chip area can be greatly reduced; and the T-shaped direct current gate 9 is connected with a large resistance greater than 10kΩ, which can improve the breakdown voltage, make the working range of the device wider, reduce the insertion loss, and improve the isolation stability. In addition, by applying different voltages to the direct current gate, the opening degree of the two-dimensional electron gas channel will be different, so that the gain of the power amplifier device can be conveniently adjusted.

[0075] Please refer toFigure 6 , Figure 6 is another flow diagram of a preparation method of a double-gate large-resistance integrated device provided by an embodiment of the present application, and the method comprises the following steps:

[0076] S201, a wafer is obtained, and the wafer comprises, from bottom to top, a substrate layer 1, a buffer layer 2, a channel layer 3 and a barrier layer 4.

[0077] The wafer in this step can be directly purchased, that is, the scheme of the present application is directly processed on any wafer; or the substrate layer 1, the buffer layer 2, the channel layer 3 and the barrier layer 4 can be sequentially and respectively prepared according to the preparation process of the wafer; the material of the substrate layer 1 is preferably SiC, the material of the buffer layer 2 is preferably GaN, the material of the channel layer 3 is preferably GaN, and the material of the barrier layer 4 is preferably AlGaN.

[0078] S202, a source 6 and a drain 7 are prepared in the source pattern area and the drain pattern area on the barrier layer 4.

[0079] This step can specifically comprise:

[0080] The source pattern area and the drain pattern area are etched on the barrier layer 4 by using a photoetching process to prepare the source and drain ohmic metal, the photoetching process uses SF6 photoresist first and then EPI621 photoresist; then ohmic metal evaporation is performed in the source pattern area and the drain pattern area, the metal is Ti / Al / Ni / Au, and the thickness is 20 / 160 / 55 / 45 nm; finally, ohmic contact annealing is performed to obtain the source 6 and the drain 7.

[0081] S203, ions are implanted in the wafer outside the second preset resistance pattern area 13 on the surface of the barrier layer 4 and outside the device where the source 6 and the drain 7 are located, and the wafer part contained below the second preset resistance pattern area forms a gate resistance effect area.

[0082] This step can specifically comprise:

[0083] The layout pattern of the gate large-resistance mask plate is used to photoetch the second preset resistance pattern area 13 on the surface of the barrier layer 4 using AZ6130 photoresist; then argon ions are implanted into the GaN channel layer 3 below the wafer part contained below the second preset resistance pattern area 13 and outside the device where the source 6 and the drain 7 are located, so that the two-dimensional electron gas in the passive area outside the device is interrupted, the wafer part contained below the second preset resistance pattern area 13 has two-dimensional electron gas, forming a gate resistance effect area 12, which can play a voltage control role on the direct current gate. Since the resistance of the gate resistance effect area 12 is much larger than 10KΩ, it can also be used as an implementation mode of the gate large resistance, playing a role of high isolation degree.

[0084] S204, growing a passivation layer 5 on the barrier layer 4 and the source 6 and the drain 7.

[0085] This step can specifically include:

[0086] PECVD technology is used to grow the SiN passivation layer 5 on the barrier layer 4 and the source 6 and the drain 7, with a thickness of 120 nm.

[0087] S205, etching away the passivation layer 5 covering the source 6 and the drain 7 to expose the source 6 and the drain 7.

[0088] This step can specifically include:

[0089] After passivation, aperture photolithography is performed on the surface of the SiN passivation layer 5, using EPI621 photoresist. Then, aperture F-based etching is performed using an ICP etching device, with an etching depth reaching the upper surface of the source 6 and the drain 7, with the purpose of exposing the SiN-covered source and drain ohmic metal.

[0090] S206, etching two grooves on the passivation layer 5 to the upper surface of the barrier layer 4, and performing gate metal evaporation in the two grooves respectively to form a T-shaped radio frequency gate 8 used as a power amplifier and a T-shaped direct current gate 9 used as a switch, with the gate legs of the T-shaped radio frequency gate 8 and the T-shaped direct current gate 9 inserted into the grooves, and the gate caps covering the gate legs and the passivation layer 5 on both sides of the grooves; and the T-shaped direct current gate 9 is connected with the gate resistance effect area 12; the T-shaped direct current gate 9 is used to control the opening degree of the two-dimensional electron gas channel when different voltages are applied to it, to realize the gain adjustment of the power amplifier device.

[0091] This step can specifically include:

[0092] Single-layer photoresist photolithography is performed on the surface of the passivation layer 5, using EPI621 photoresist to etch two grooves; F-based etching is performed using an ICP etching device, etching to the upper surface of the barrier layer 4, and etching away the excess passivation layer 5, and performing gate metal evaporation in the two grooves formed respectively to form a T-shaped radio frequency gate 8 used as a power amplifier and a T-shaped direct current gate 9 used as a switch; and the T-shaped direct current gate 9 is connected with the gate resistance effect area 12.

[0093] The preparation method of the double-gate large-resistance integrated device of the embodiment of the application is characterized in that: ions are injected into the wafer outside the second preset resistance pattern area 13 on the surface of the barrier layer 4 and the device where the source electrode 6 and the drain electrode 7 are located, the wafer part contained in the second preset resistance pattern area forms a gate resistance effect area with large resistance, two grooves are arranged on the passivation layer 5, and a T-shaped radio frequency gate 8 used as a power amplifier and a T-shaped direct current gate 9 used as a switch are respectively formed in the grooves, which is equivalent to integrating the power amplifier and the radio frequency switch on one device through the double-gate structure, so that the number of radio frequency front-end devices can be greatly reduced, and the chip area can be greatly reduced; the T-shaped direct current gate 9 is connected with the gate resistance effect area 12, so that the breakdown voltage can be improved, the working range of the device can be widened, the insertion loss can be reduced, and the isolation stability can be improved. In addition, by applying different voltages to the direct current gate, the opening degree of the two-dimensional electron gas channel can be different, so that the gain of the power amplifier device can be conveniently adjusted.

[0094] Please refer to Figure 7 , Figure 7 is a structure schematic diagram of a radio frequency front-end provided by the embodiment of the application, the radio frequency front-end comprises the double-gate large-resistance integrated device of any one of the above embodiments, and the double-gate large-resistance integrated device prepared by the preparation method of any one of the above embodiments. As a comparison, please refer to Figure 8 , Figure 8 is a structure schematic diagram of a traditional radio frequency front-end. Compared with the traditional radio frequency front-end, the radio frequency switch and the power amplifier are integrated on one device through the double-gate structure in the application, and the direct current gate is connected with the gate resistance greater than 10kΩ, when the direct current gate is floating, the state of the device of the application is equivalent to that of the power amplifier; when the transmitting end is in the blocking state, a voltage Vg2 with a large negative value is applied to the direct current gate, so that the carriers are depleted and the channel is pinched off, and the signal in the antenna cannot pass through the power amplifier, thereby playing a closing function; when the transmitting end is in the conducting state, the device of the application works as the radio frequency switch and also works as the power amplifier. The voltage Vg1 is applied to the radio frequency gate of the device of the application, and is used to input the radio frequency signal, and the positive voltage Vg2 is applied to the direct current gate, and is used to control the channel. The size of the positive voltage Vg2 of the direct current gate is changed, so as to control the opening degree of the channel, change the amplification degree, and make the signal gain different, and the working principle is as shown in Figure 7 . After the signal is amplified by the integrated device, the signal can be directly conducted to the antenna for transmission. Figure 9 is a design layout of a radio frequency front-end device provided by the embodiment of the application, and can be used as a specific application reference of the double-gate large-resistance integrated device provided by the embodiment of the application.

[0095] The radio frequency front end of the application, by optimizing the transmitting end in the radio frequency front end, integrates the radio frequency switch and the power amplifier on one device through the double-gate structure, changes the connection mode of the power amplifier and the antenna through the independent radio frequency switch in the traditional mode, and is applied to the massive antenna technology (Massive MIMO). When applied to the massive antenna technology (Massive MIMO), under the condition of ensuring good switch characteristics and power amplifier characteristics, due to the very large number of channels of the massive antenna, the integrated device can greatly reduce the number of radio frequency front end devices, and the chip area is greatly reduced. In addition, only the voltage bias of the direct current gate needs to be adjusted to change the gain of the power amplifier part, which is ingenious, convenient and simple. In addition, unlike the effect of other double-gate structures, the introduction of the gate large resistance further optimizes the double-gate structure. In the application aspect of the radio frequency front end, the signal entering the radio frequency gate is very small in the possibility of leakage from the direct current control gate, so the insertion loss and isolation of the integrated device are obviously improved, which is not possessed by other double-gate structure technologies.

[0096] The above is a further detailed description of the application in combination with specific preferred embodiments, and the specific implementation of the application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the application belongs, some simple deductions or substitutions can be made without departing from the concept of the application, and all of them should be regarded as falling within the protection scope of the application.

Claims

1. A dual-gate large-resistance integrated device, characterized in that, From bottom to top, successively include: substrate layer, buffer layer, channel layer and barrier layer, wherein, The barrier layer is provided with a passivation layer; The passivation layer is provided with two grooves etched to the upper surface of the barrier layer, two T-shaped radio frequency gates used as power amplifiers and T-shaped direct current gates used as switches are respectively formed in the two grooves, and the gate pins of the T-shaped radio frequency gates and the T-shaped direct current gates are inserted into the grooves, and the gate caps are covered on the gate pins and the passivation layer on both sides of the grooves; The direct current gate is connected with a gate resistor with a resistance greater than 10kΩ; The source and the drain are respectively arranged at both ends of the channel layer and the barrier layer; Different voltages are applied to the T-shaped direct current gate to control the opening degree of the two-dimensional electron gas channel to realize the gain adjustment of the power amplifier device; The gate resistor is a metal resistor formed by depositing metal on a first preset resistance pattern area on the passivation layer; the first preset resistance pattern area is arranged on the passivation layer on the upper surface of the wafer and outside the device where the source and the drain are located; The metal resistor is a NiCr alloy thin film resistor; The T-shaped direct current gate and the gate resistor are interconnected through interconnection metal.

2. A double-gate large resistance integrated device, characterized by, From bottom to top, successively include: substrate layer, buffer layer, channel layer and barrier layer, wherein, The barrier layer is provided with a passivation layer; The passivation layer is provided with two grooves etched to the upper surface of the barrier layer, two T-shaped radio frequency gates used as power amplifiers and T-shaped direct current gates used as switches are respectively formed in the two grooves, and the gate pins of the T-shaped radio frequency gates and the T-shaped direct current gates are inserted into the grooves, and the gate caps are covered on the gate pins and the passivation layer on both sides of the grooves; The direct current gate is connected with a gate resistor with a resistance greater than 10kΩ; The source and the drain are respectively arranged at both ends of the channel layer and the barrier layer; Different voltages are applied to the T-shaped direct current gate to control the opening degree of the two-dimensional electron gas channel to realize the gain adjustment of the power amplifier device; The gate resistor is a gate resistor effect area, which is a part of the wafer contained in a second preset resistance pattern area formed by implanting ions on the wafer outside the second preset resistance pattern area on the surface of the barrier layer of the wafer and outside the device where the source and the drain are located.

3. The dual-gate high-resistance integrated device according to claim 1 or 2, wherein The material of the passivation layer is SiN, and the thickness is 120nm.

4. The integrated double-gate high-resistance device according to claim 1 or 2, wherein The materials of the T-shaped radio frequency gate and the T-shaped direct current gate are both Ni / Au, wherein the thickness of Ni is 45nm, and the thickness of Au is 400nm.

5. A method of manufacturing a double-gate large resistance integrated device according to claim 1, wherein It includes: Obtain a wafer, the wafer successively includes from bottom to top: substrate layer, buffer layer, channel layer and barrier layer; Prepare a source and a drain on a source pattern area and a drain pattern area on the barrier layer; Grow a passivation layer on the barrier layer and the source and the drain; Etch away the passivation layer covering the source and the drain to expose the source and the drain; etching two grooves of different depths on the passivation layer to the surface of the barrier layer, and performing gate metal evaporation in the two grooves respectively to form a T-shaped radio frequency gate used as a power amplifier and a T-shaped direct current gate used as a switch, the gate legs of the T-shaped radio frequency gate and the T-shaped direct current gate are inserted into the grooves, and the gate caps are covered on the gate legs and the passivation layer on both sides of the grooves; the T-shaped direct current gate is used to control the opening degree of the two-dimensional electron gas channel when different voltages are applied thereto, so as to realize the gain adjustment of the power amplifier device; depositing metal on the first preset resistance pattern area on the passivation layer to form a gate resistance, and the resistance value of the gate resistance is greater than 10 kΩ; the first preset resistance pattern area is arranged on the passivation layer on the upper surface of the wafer and outside the device where the source and the drain are located; depositing interconnection metal between the T-shaped direct current gate and the gate resistance to realize the interconnection of the T-shaped direct current gate and the gate resistance; the gate resistance is a metal resistance, and the metal resistance is formed by depositing metal on the first preset resistance pattern area on the passivation layer; the first preset resistance pattern area is arranged on the passivation layer on the upper surface of the wafer and outside the device where the source and the drain are located; the metal resistance is a NiCr alloy thin film resistance.

6. A method of manufacturing a double-gate large resistance integrated device as claimed in claim 2, characterized by, comprising: obtaining a wafer, the wafer sequentially comprising, from bottom to top: a substrate layer, a buffer layer, a channel layer, and a barrier layer; preparing a source and a drain on a source pattern area and a drain pattern area on the barrier layer; implanting ions on the wafer outside a second preset resistance pattern area on the surface of the barrier layer and outside the device where the source and the drain are located, and the part of the wafer contained in the second preset resistance pattern area forms a gate resistance effect area; growing a passivation layer on the barrier layer and on the source and the drain; etching away the passivation layer covering the source and the drain to expose the source and the drain; etching two grooves of different depths on the passivation layer to the surface of the barrier layer, and performing gate metal evaporation in the two grooves respectively to form a T-shaped radio frequency gate used as a power amplifier and a T-shaped direct current gate used as a switch, the gate legs of the T-shaped radio frequency gate and the T-shaped direct current gate are inserted into the grooves, and the gate caps are covered on the gate legs and the passivation layer on both sides of the grooves; and the T-shaped direct current gate is connected with the gate resistance effect area; the T-shaped direct current gate is used to control the opening degree of the two-dimensional electron gas channel when different voltages are applied thereto, so as to realize the gain adjustment of the power amplifier device; the gate resistance is a gate resistance effect area, and the gate resistance effect area is the part of the wafer contained in the second preset resistance pattern area formed by implanting ions on the wafer outside a second preset resistance pattern area on the surface of the barrier layer and outside the device where the source and the drain are located.

7. A radio frequency front end, comprising: comprising: the double-gate large-resistance integrated device of any one of claims 1-4, or the double-gate large-resistance integrated device prepared by the preparation method of claim 5 or claim 6.

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