An eleven-level inverter circuit

Abstract

The present invention discloses an eleven-level inverter circuit, comprising an energy storage capacitor bank and a power supply. When the midpoint potential is unbalanced and the midpoint potential is higher than 0.5Vdc, the inverter circuit outputs from a 0 level to a +1 level, controls the midpoint potential, the energy storage capacitor bank, and the power supply to be turned on, and discharges the midpoint potential to the power supply via the energy storage capacitor, thereby releasing the unbalanced potential and causing the midpoint potential to decrease. When the midpoint potential is lower than 0.5Vdc, the inverter circuit outputs from a 0 level to a -1 level, controls the power supply energy storage capacitor bank and the midpoint potential to be turned on, causes the power supply to charge the midpoint potential via the energy storage capacitor bank, and causes the midpoint potential to increase. The present invention has the advantage of achieving a balanced midpoint potential.

Description

Technical Field

[0001] The present invention relates to the technical field of inverters, and more particularly to an eleven-level inverter circuit. Background Art

[0002] With the use of fossil fuels and the intensification of global warming, the development of new energy sources, primarily photovoltaics and nuclear power, is accelerating. In photovoltaic power generation, solar panels convert sunlight into direct current (DC), which is then inverted and fed into the national grid. With rising energy demand, solar power has greater potential for growth in terms of installed capacity and size. Traditional inverter topologies are becoming less suitable for large-capacity solar power plants. For example, in the widely used two-level H-bridge topology, each switch operates at a DC voltage. Switches with higher voltage tolerances are less costly and efficient than those with lower voltage tolerances. The two-level H-bridge requires a higher switching frequency or a filter with a lower cutoff frequency to effectively meet harmonic requirements. The equivalent switching frequency of a multilevel inverter is n-1 times the switching frequency. This means that for the same switching frequency, the equivalent switching frequency of a multilevel inverter is higher than that of a two-level inverter. Furthermore, the voltages operated by the switches in a multilevel inverter are lower than those in a two-level inverter, resulting in higher efficiency.

[0003] Traditional multi-level inverters, such as three-level inverter circuits, have a maximum inverter voltage of half the maximum DC voltage, lack a boost function, and require midpoint potential balancing, requiring a larger step-up transformer for grid connection. Chinese Patent Publication No. CN 203734562U discloses an eleven-level single-phase inverter that can output nine different voltage combinations. It offers advantages such as a reduced number of power switches, reduced control switch stress, reduced power loss, higher efficiency, and more stable operation. While it has a boost function and eliminates the need for a step-up transformer, it lacks midpoint potential balancing.

[0004] Taking the more commonly used three-level inverter as an example, the three-level inverter does not have the midpoint potential balance function. When the midpoint potential is unbalanced, the zero level output of the circuit will have a certain drift. If the algorithm is not corrected, the midpoint potential will continue to fluctuate and eventually tend to the power supply voltage. As a result, the inverter cannot output zero level, and the output voltage harmonics increase. Furthermore, the capacitor is subjected to the power supply voltage, which can easily damage the DC capacitor and cause the inverter to malfunction. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that the existing multi-level inverter circuit does not have the balancing function of the midpoint potential, which causes the inverter circuit to be unable to emit 0 level, increases the output voltage harmonics, easily damages the DC capacitor, and causes the inverter to fail to work normally.

[0006] The present invention solves the above-mentioned technical problems through the following technical means: an eleven-level inverter circuit includes an energy storage capacitor group and a power supply. When the midpoint potential is unbalanced and the midpoint potential is higher than 0.5Vdc, the inverter circuit outputs from the 0 level to the +1 level, controls the midpoint potential, the energy storage capacitor group and the power supply to be turned on, and the midpoint potential is discharged to the power supply through the energy storage capacitor, thereby releasing the unbalanced potential and lowering the midpoint potential; when the midpoint potential is lower than 0.5Vdc, the inverter circuit outputs from the 0 level to the -1 level, controls the power supply energy storage capacitor group and the midpoint potential to be turned on, and the power supply is charged to the midpoint potential through the energy storage capacitor group, and the midpoint potential is increased.

[0007] Beneficial effect: When the midpoint potential is unbalanced in the present invention, the switch tube is adjusted when the inverter circuit outputs ±1 level. By controlling the charging and discharging of the energy storage capacitor group, it is discharged when the midpoint potential is high, thereby releasing energy, and charged when the midpoint potential is low, thereby replenishing energy, realizing the balance function of the midpoint potential, avoiding the inverter circuit from being unable to emit 0 level, avoiding damage to the DC capacitor, and enabling the inverter to work normally.

[0008] Furthermore, the energy storage capacitor group includes a polarized capacitor C5, and the inverter circuit further includes a switch tube Q9, a switch tube Q10, a switch tube Q6, a switch tube Q7, a switch tube Q14, a switch tube Q15, a switch tube Q17, a switch tube Q18, a polarized capacitor C1, and a polarized capacitor C2. The source of the switch tube Q7 is connected to the drain of the switch tube Q18, and the connection point serves as the midpoint potential. The drain of the switch tube Q7 is connected to the source of the switch tube Q6. The drain of the switch tube Q6 is connected to the drain of the switch tube Q10 and the positive electrode of the polarized capacitor C5, respectively. The source of the switch Q10 is connected to the drain of the switch Q9. The source of the switch Q9 is grounded and connected to the negative electrode of the polarity capacitor C1. The positive electrode of the polarity capacitor C1 is connected to the positive electrode of the power supply. The source of the switch Q18 is connected to the drain of the switch Q17. The source of the switch Q17 is respectively connected to the source of the switch Q15 and the negative electrode of the polarity capacitor C5. The drain of the switch Q15 is connected to the source of the switch Q14. The drain of the switch Q14 is grounded and connected to the positive electrode of the polarity capacitor C2. The negative electrode of the polarity capacitor C2 is connected to the negative electrode of the power supply.

[0009] Furthermore, the energy storage capacitor group includes a polar capacitor C3, and the inverter circuit also includes a switch tube Q1, a switch tube Q2, a switch tube Q13, a switch tube Q3, a switch tube Q11, a switch tube Q12, a switch tube Q4, a switch tube Q8, and a switch tube Q5. The drain of the switch tube Q5 is connected to the drain of the switch tube Q7, the source of the switch tube Q5 is connected to the drain of the switch tube Q4 and the source of the switch tube Q8, the drain of the switch tube Q8 is connected to the drain of the switch tube Q6, and the source of the switch tube Q4 is connected to the drain of the switch tube Q6. It is connected to the source of the switching tube Q3, the drain of the switching tube Q3, the positive electrode of the polarity capacitor C3, the drain of the switching tube Q2 and the drain of the switching tube Q11, the source of the switching tube Q2, the source of the switching tube Q1 and the drain of the switching tube Q13, the source of the switching tube Q13 is connected to the negative electrode of the polarity capacitor C1, the drain of the switching tube Q1 is connected to the positive electrode of the polarity capacitor C1, the positive electrode of the polarity capacitor C3 is connected to the source of the switching tube Q12, and the drain of the switching tube Q12 is connected to the source of the switching tube Q2.

[0010] Furthermore, the energy storage capacitor group includes a polarized capacitor C4, and the inverter circuit further includes a switch tube Q26, a switch tube Q24, a switch tube Q25, a switch tube Q21, a switch tube Q23, a switch tube Q22, a switch tube Q20, a switch tube Q16, and a switch tube Q19. The source of the switch tube Q19 is connected to the source of the switch tube Q18, the drain of the switch tube Q19 is connected to the source of the switch tube Q20 and the drain of the switch tube Q16, respectively, the source of the switch tube Q16 is connected to the source of the switch tube Q17, and the drain of the switch tube Q20 is connected to the drain of the switch tube Q21. The source of the switch tube Q21, the negative electrode of the polarity capacitor C4, the source of the switch tube Q24, and the source of the switch tube Q23 are connected. The drain of the switch tube Q24, the drain of the switch tube Q26, and the source of the switch tube Q25 are connected. The drain of the switch tube Q25 is connected to the positive electrode of the polarity capacitor C2. The source of the switch tube Q26 is connected to the negative electrode of the polarity capacitor C2. The positive electrode of the polarity capacitor C4 is connected to the drain of the switch tube Q22 and the source of the switch tube Q11. The source of the switch tube Q22 is connected to the drain of the switch tube Q24. The drain of the switch tube Q23 is connected to the negative electrode of the polarity capacitor C3.

[0011] Furthermore, the switch tubes Q9, Q10, Q6, and Q7 are turned on, and the remaining switch tubes are turned off. At this time, the circuit outputs a 0 level.

[0012] Furthermore, the switch tubes Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, and the other switch tubes are turned off, and the circuit outputs a +1 level. At this time, the polarity capacitor C5 is charged; the switch tubes Q14, Q15, Q6, and Q7 are turned on, and the other switch tubes are turned off, and the circuit outputs a +2 level.

[0013] The switching tubes Q13, Q12, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, and the other switching tubes are turned off. The polarity capacitor C3 charges the polarity capacitor C5. At this time, the output is a +2 level voltage. When Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, and Q26 are turned on, and the other switching tubes are turned off, the output is a +3 level voltage, and the polarity capacitor C3 is charged.

[0014] Furthermore, the switches Q1, Q2, Q12, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, and the other switches are turned off. The circuit outputs a +3 level voltage and charges the polarity capacitor C5. When Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, and Q26 are turned on, and the other switches are turned off, the circuit outputs a +4 level voltage, charges the polarity capacitor C3, and discharges the polarity capacitor C5.

[0015] The switching tubes Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, and the other switching tubes are turned off. The circuit outputs a +4 level and charges the polarity capacitor C5. When outputting a +5 level, in the first stage, the switching tubes Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, Q26, and Q11 are turned on, and the other switching tubes are turned off. The polarity capacitor C3 is charged, and the polarity capacitor C4 is charged. In the second stage, the switching tubes Q14, Q15, Q6, Q7, Q1, Q2Q23, Q22, and Q26 are turned on, and the other switching tubes are turned off. The polarity capacitor C3 is charged again. At this time, the circuit outputs a +5 level.

[0016] Furthermore, the switch tubes Q26, Q24, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on, and the other switch tubes are turned off. At this time, the circuit outputs a -1 level, and the polarity capacitor C5 is charged; the switch tubes Q9, Q10, Q17, and Q18 are turned on, and the other switch tubes are turned off, and the polarity capacitor C5 is discharged. At this time, the circuit output voltage is a -2 level;

[0017] The switching tubes Q25, Q22, Q21, Q20, Q16, Q17, Q19, Q18, Q1, Q2, Q3, Q4, and Q8 are turned on, and the other switching tubes are turned off. At this time, the circuit outputs a -2 level, and the polarity capacitor C5 is charged; the switching tubes Q9, Q10, Q17, Q18, Q1, Q2, Q11, Q24, and Q26 are turned on, and the other switching tubes are turned off. The polarity capacitor C5 is discharged, and the circuit output voltage is a -3 level.

[0018] Furthermore, the switching tubes Q26, Q22, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on, and the other switching tubes are turned off. At this time, the circuit outputs a -3 level, and the polarity capacitor C5 is charged; the switching tubes Q9, Q10, Q17, Q18, Q1, Q2, Q11, Q24, and Q26 are turned on, and the other switching tubes are turned off, and the polarity capacitor C5 is discharged. At this time, the circuit outputs a voltage of -4 level;

[0019] The switching tubes Q26, Q22, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on, and the other switching tubes are turned off. At this time, the circuit outputs a -4 level, and the polarity capacitor C5 is charged. When the -5 level is output, in the first stage, the switching tubes Q9, Q10, Q17, Q18, Q1, Q2, Q23, Q24, Q26, and Q11 are turned on, and the other switching tubes are turned off, and the polarity capacitors C3 and C4 are charged. In the second stage, the switching tubes Q9, Q10, Q17, Q18, Q26, Q24, Q11, Q12, and Q1 are turned on, and the other switching tubes are turned off. At this time, the polarity capacitor C4 is charged again, and the circuit output is a -5 level.

[0020] Furthermore, when the midpoint potential is unbalanced, the switch tube adjusts when outputting ±1 level. When the midpoint potential is higher than 0.5Vdc and the circuit outputs from 0 level to +1 level, the switch tubes Q14, Q15, Q17, Q18, Q13, Q2, Q23, Q24, and Q26 are turned on, and the other switch tubes are cut off. At this time, the circuit output is 0 level, the switch tubes Q13, Q12, Q3, Q4, Q5, Q6, Q7, and Q8 are turned on, and the other switches are cut off. The switch is turned off, and the circuit output is +1 level. The charge is released through the path of charging the polar capacitor C3 through the midpoint potential, and the midpoint potential drops. When the midpoint potential is lower than 0.5Vdc, the circuit changes from 0 to -1 level, the switch tubes Q9, Q10, Q6, Q7, Q1, Q2, Q11, Q24, and Q25 are turned on, and the other switch tubes are turned off. At this time, the circuit output is 0 level, and the power supply is charged to the midpoint potential through the polar capacitor C4, and the midpoint potential rises.

[0021] The advantages of the present invention are:

[0022] (1) In the present invention, when the midpoint potential is unbalanced, the switch tube is adjusted when the inverter circuit outputs ±1 level. By controlling the charging and discharging of the energy storage capacitor group, the capacitor group is discharged when the midpoint potential is high, thereby releasing energy, and charged when the midpoint potential is low, thereby replenishing energy, thereby achieving the balance function of the midpoint potential, avoiding the inverter circuit from being unable to emit 0 level, avoiding damage to the DC capacitor, and enabling the inverter to work normally.

[0023] (2) In the present invention, when the polar capacitors C3 and C4 deviate from the midpoint potential by a certain value, the corresponding unbalanced charge is Qc. When the midpoint potential imbalance is detected, the midpoint potential balance wave is generated to achieve regulation.

[0024] (3) In the present invention, when polar capacitors C3 and C4 are charging, polar capacitor C5 is discharging. When polar capacitors C3 and C4 are discharging, one end of polar capacitor C5 is connected to the DC power supply through the conduction of the switch tube for charging, so that the circuit always operates in a continuous state. Assuming that the power supply voltage is Vdc, polar capacitors C3 and C4 are charged and connected in series with the power supply. According to the superposition theorem, the output voltage is the sum of Vdc and the capacitor voltage.

[0025] (4) The present invention has a multi-level switching function through the switching of the switch tube, and can switch from a low level to a high level at the same time, thereby having a boost function. Assuming that the power supply voltage is Vdc, the polar capacitor voltages C3 and C4 are charged through the switching of the switch tube. After the conversion of the switch tube, the power supply is connected in series with the capacitor. According to the superposition theorem in the circuit, the output voltage is Vdc + capacitor voltage. In a relatively short period of time, the polar capacitor will discharge, and the output voltage will remain approximately unchanged.

[0026] (5) The inverter circuit of the present invention can change back and forth from a low level to a higher level, such as from 0 to ±1 level, and from ±1 level to 0 level, so that the working mode is flexible and suitable for various application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is the overall working flow diagram of the circuit;

[0028] Figure 2 This is an original circuit diagram of an eleven-level inverter circuit disclosed in an embodiment of the present invention;

[0029] Figure 3 This is the path diagram of the circuit's 0-level output;

[0030] Figure 4 Output experimental waveform for the circuit at level 0;

[0031] Figure 5 It is the path diagram of the circuit from 0 level to +1 level output;

[0032] Figure 6 Output experimental waveform for the circuit +1 level;

[0033] Figure 7 This is the path diagram from the +1 level to the +2 level output of the circuit;

[0034] Figure 8 Output experimental waveform for the circuit +2 level;

[0035] Figure 9 This is the path diagram for the circuit's +2 level to +3 level output;

[0036] Figure 10 Output experimental waveform for the circuit +3 level;

[0037] Figure 11 This is the path diagram for the circuit's +3 level to +4 level output;

[0038] Figure 12 Output experimental waveform for the circuit +4 level;

[0039] Figure 13 This is the path diagram for the circuit's +4 level to +5 level output;

[0040] Figure 14 Output experimental waveform for the circuit +5 level;

[0041] Figure 15 It is the path diagram of the circuit from 0 level to -1 level output;

[0042] Figure 16 Output experimental waveform for circuit-1 level;

[0043] Figure 17 It is the path diagram from the -1 level to the -2 level output of the circuit;

[0044] Figure 18 Output experimental waveform for circuit-2 level;

[0045] Figure 19 This is the path diagram for the circuit's -2 level to -3 level output;

[0046] Figure 20 Output experimental waveform for circuit-3 level;

[0047] Figure 21 This is the path diagram for the circuit's -3 level to -4 level output;

[0048] Figure 22 Output experimental waveform for circuit-4 level;

[0049] Figure 23 This is the path diagram for the circuit's -4 level to -5 level output;

[0050] Figure 24 Output experimental waveform for circuit -5 level;

[0051] Figure 25 Schematic diagram of the process of adjusting the positive imbalance of the potential at the midpoint of the circuit;

[0052] Figure 26 It is a schematic diagram of the process of regulating the negative imbalance of the circuit midpoint potential;

[0053] Figure 27 It is the overall working waveform of the circuit. DETAILED DESCRIPTION

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0055] like Figure 1 and Figure 2 As shown, the present invention provides an eleven-level inverter circuit, including an energy storage capacitor group and a power supply, wherein the energy storage capacitor group includes a polar capacitor C5, and the inverter circuit further includes a switch tube Q9, a switch tube Q10, a switch tube Q6, a switch tube Q7, a switch tube Q14, a switch tube Q15, a switch tube Q17, a switch tube Q18, a polar capacitor C1, and a polar capacitor C2. The source of the switch tube Q7 is connected to the drain of the switch tube Q18, and the connection point serves as a midpoint potential. The drain of the switch tube Q7 is connected to the source of the switch tube Q6, and the drain of the switch tube Q6 is connected to the drain of the switch tube Q10 and the drain of the switch tube Q18. The positive electrode of the polarity capacitor C5 is connected, the source of the switch tube Q10 is connected to the drain of the switch tube Q9, the source of the switch tube Q9 is grounded and connected to the negative electrode of the polarity capacitor C1, and the positive electrode of the polarity capacitor C1 is connected to the positive electrode of the power supply; the source of the switch tube Q18 is connected to the drain of the switch tube Q17, the source of the switch tube Q17 is respectively connected to the source of the switch tube Q15 and the negative electrode of the polarity capacitor C5, the drain of the switch tube Q15 is connected to the source of the switch tube Q14, the drain of the switch tube Q14 is grounded and connected to the positive electrode of the polarity capacitor C2, and the negative electrode of the polarity capacitor C2 is connected to the negative electrode of the power supply.

[0056] The energy storage capacitor group further includes a polar capacitor C3, and the inverter circuit further includes a switch tube Q1, a switch tube Q2, a switch tube Q13, a switch tube Q3, a switch tube Q11, a switch tube Q12, a switch tube Q4, a switch tube Q8, and a switch tube Q5. The drain of the switch tube Q5 is connected to the drain of the switch tube Q7, the source of the switch tube Q5 is connected to the drain of the switch tube Q4 and the source of the switch tube Q8, the drain of the switch tube Q8 is connected to the drain of the switch tube Q6, the source of the switch tube Q4 is connected to the drain of the switch tube Q7, and the drain of the switch tube Q7 is connected to the drain of the switch tube Q7. The source of the switch tube Q3 is connected, the drain of the switch tube Q3, the positive electrode of the polarity capacitor C3, the drain of the switch tube Q2 and the drain of the switch tube Q11 are connected, the source of the switch tube Q2, the source of the switch tube Q1 and the drain of the switch tube Q13 are connected, the source of the switch tube Q13 is connected to the negative electrode of the polarity capacitor C1, the drain of the switch tube Q1 is connected to the positive electrode of the polarity capacitor C1, the positive electrode of the polarity capacitor C3 is connected to the source of the switch tube Q12, and the drain of the switch tube Q12 is connected to the source of the switch tube Q2.

[0057] The energy storage capacitor group further includes a polar capacitor C4, and the inverter circuit further includes a switch tube Q26, a switch tube Q24, a switch tube Q25, a switch tube Q21, a switch tube Q23, a switch tube Q22, a switch tube Q20, a switch tube Q16, and a switch tube Q19. The source of the switch tube Q19 is connected to the source of the switch tube Q18, the drain of the switch tube Q19 is connected to the source of the switch tube Q20 and the drain of the switch tube Q16, the source of the switch tube Q16 is connected to the source of the switch tube Q17, the drain of the switch tube Q20 is connected to the drain of the switch tube Q21, and the switch The source of the transistor Q21, the negative electrode of the polarity capacitor C4, the source of the switch transistor Q24, and the source of the switch transistor Q23 are connected. The drain of the switch transistor Q24, the drain of the switch transistor Q26, and the source of the switch transistor Q25 are connected. The drain of the switch transistor Q25 is connected to the positive electrode of the polarity capacitor C2. The source of the switch transistor Q26 is connected to the negative electrode of the polarity capacitor C2. The positive electrode of the polarity capacitor C4 is connected to the drain of the switch transistor Q22 and the source of the switch transistor Q11. The source of the switch transistor Q22 is connected to the drain of the switch transistor Q24. The drain of the switch transistor Q23 is connected to the negative electrode of the polarity capacitor C3.

[0058] In this embodiment, C3 and C4 are charging capacitors, and C5 is a buffer capacitor. Capacitors with low ESR are selected, such as solid capacitors and hybrid capacitors, which have a lower charging speed, lower power loss, and longer working time.

[0059] The present invention has the following relationship between the on and off state of the switch tubes at each level in the circuit:

[0060] like Figure 3 and Figure 4As shown, for level 0: switches Q9, Q10, Q6, and Q7 are turned on, while the remaining switches are turned off. At this point, the circuit outputs level 0. It should be noted that level 0 represents 0 times the reference level. In this embodiment, the reference level is 0.5 Vdc. Level +1 represents +0.5 Vdc, level +2 represents +1 Vdc, and level +3 represents +1.5 Vdc. The same applies to other levels and is not detailed here.

[0061] like Figure 5 and Figure 6 As shown, for the 0 level to +1 level, the switch tubes Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 are turned on, and the other switch tubes are turned off.

[0062] like Figure 7 (a) Figure 7 (b) and Figure 8 As shown, for the transition from +1 to +2, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, while the remaining switches are turned off. The circuit outputs a +1 level, charging capacitor C5 to a voltage equal to the +2 level. When the output reaches a +2 level, Q14, Q15, Q6, and Q7 are turned on, while the remaining switches are turned off, resulting in a +2 level output.

[0063] like Figure 9 (a) Figure 9 (b) and Figure 10 As shown, for the +2 to +3 voltage transition: switches Q13, Q12, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, while the remaining switches are turned off. Capacitor C3 charges capacitor C5, resulting in a +2 voltage output. When Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, and Q26 are turned on, the output voltage reaches a +3 voltage level, and capacitor C3 charges. The circuit outputs a +3 voltage level.

[0064] like Figure 11 and Figure 12 As shown, for the +3 level to +4 level transition: when switches Q1, Q2, Q12, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, the circuit outputs a +3 level voltage and charges capacitor C5, bringing it to a +4 level. When Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, and Q26 are turned on, a +4 level voltage is output, capacitor C3 charges, and capacitor C5 discharges. The circuit outputs a +4 level.

[0065] like Figure 13 (a) Figure 13 (b) and Figure 14As shown, for the transition from +4 to +5 levels: switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, the circuit outputs a +4 level and charges capacitor C5, bringing it to a +5 level. When outputting a +5 level, in the first stage, switches Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, Q26, and Q11 are turned on, charging capacitors C3 and C4. In the second stage, switches Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q22, and Q26 are turned on, charging capacitor C3 a second time, bringing the capacitor voltage to a +3 level. At this point, the circuit outputs a +5 level.

[0066] like Figure 15 and Figure 16 As shown, for the 0 level to -1 level: the switch tubes Q6, Q7, Q9, Q10, Q14, Q15, Q17, and Q18 are turned on, and the circuit output is 0 level. The switch tubes Q26, Q24, Q21, Q20, Q16, Q17, Q18, and Q19 are turned on, and the circuit output is -1 level.

[0067] like Figure 17 (a) Figure 17 (b) and Figure 18 As shown, for the -1 level to -2 level: switches Q26, Q24, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on. At this time, the circuit outputs a -1 level, and capacitor C5 is charged, causing its voltage to reach a +2 level. Switches Q9, Q10, Q17, and Q18 are turned on, causing capacitor C5 to discharge. At this time, the circuit outputs a -2 level.

[0068] like Figure 19 (a) Figure 19 (b) and Figure 20 As shown, for the -2 level to -3 level: switches Q25, Q22, Q21, Q20, Q16, Q17, Q19, Q18, Q1, Q2, Q3, Q4, and Q8 are turned on. At this time, the circuit outputs a -2 level, and capacitor C5 is charged, causing its voltage to reach the +3 level. Switches Q9, Q10, Q17, Q18, Q1, Q2, Q11, Q24, and Q26 are turned on, causing capacitor C5 to discharge. At this time, the circuit outputs a -3 level.

[0069] like Figure 21 and Figure 22As shown, for the -3 level to -4 level: switches Q26, Q22, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on. At this time, the circuit outputs a -3 level, and capacitor C5 is charged, causing its voltage to reach a +4 level. Switches Q9, Q10, Q17, Q18, Q1, Q2, Q11, Q24, and Q26 are turned on, causing capacitor C5 to discharge. At this time, the circuit outputs a -4 level.

[0070] like Figure 23 (a) Figure 23 (b) and Figure 24 As shown, for the transition from -4 to -5 levels: switches Q26, Q22, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on. At this point, the circuit outputs a -4 level, charging capacitor C5 to a +5 level voltage. For a -5 level output, in the first stage, switches Q9, Q10, Q17, Q18, Q1, Q2, Q23, Q24, Q26, and Q11 are turned on, charging capacitors C3 and C4. In the second stage, switches Q9, Q10, Q17, Q18, Q26, Q24, Q11, Q12, and Q1 are turned on, charging capacitor C4 a second time to a +3 level voltage. At this point, the circuit outputs a -5 level.

[0071] The inverter circuit of the present invention has a midpoint potential adjustment function. When the midpoint potential is unbalanced, the switching tube adjusts the output to ±1 level. When the midpoint potential is higher than 0.5Vdc, when the output is from 0 level to +1 level, the switching tubes Q14, Q15, Q17, Q18, Q13, Q2, Q23, Q24, and Q26 are turned on, and the circuit output is at 0 level. The switching tubes Q13, Q12, Q3, Q4, Q5, Q6, Q7, and Q8 are turned on, and the circuit output is at +1 level, and the midpoint potential decreases. When the midpoint potential is lower than 0.5Vdc, when the output is from 0 to -1 level, the switching tubes Q9, Q10, Q6, Q7, Q1, Q2, Q11, Q24, and Q25 are turned on, and the circuit output is at 0 level. The power supply charges the midpoint potential through C4, and the midpoint potential increases. When the switches Q25, Q22, Q21, Q20, Q16, Q17, Q18, and Q19 are turned on, the circuit outputs a -1 level, and the current is released by the unbalanced charge at the midpoint potential. Figure 25 (a) and Figure 25 (b) is a schematic diagram of the circuit midpoint potential forward imbalance adjustment process. Figure 26 (a) and Figure 26 (b) is a schematic diagram of the negative imbalance adjustment process of the circuit midpoint potential.

[0072] Under high-level output conditions, the equivalent voltage withstand values ​​of the switches differ, resulting in a lower voltage withstand. When the DC power supply voltage is Vdc, the circuit outputs a +5V level (2.5Vdc). At this point, switches Q14, Q15, Q6, Q7, Q1, Q2, Q11, Q23, Q24, and Q26 are conducting, and the maximum voltage withstand of the switches in the circuit is 1.25Vdc. When the circuit outputs a -5V level, switches Q1, Q2, Q11, Q26, Q24, Q23, Q9, Q10, Q17, and Q18 are conducting, and the maximum voltage withstand of the switches in the circuit is 1.25Vdc.

[0073] like Figure 27 is the overall working waveform of the inverter circuit. It can be seen from the figure that the present invention can achieve multi-level output.

[0074] Through the above technical solution, in the present invention, when the midpoint potential is unbalanced, the switch tube is adjusted when the inverter circuit outputs the ±1 level, and the charging and discharging of the energy storage capacitor group is controlled so that the midpoint potential is discharged when it is high, thereby releasing energy, and the midpoint potential is charged when it is low, thereby replenishing energy, thereby achieving the balance function of the midpoint potential and making up for the shortcomings of the existing technology.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An eleven-level inverter circuit, characterized in that: It includes a storage capacitor bank and a power supply. When the midpoint potential is unbalanced and higher than 0.5Vdc, the inverter circuit outputs from 0 level to +1 level, controls the midpoint potential, the storage capacitor bank and the power supply to be turned on, and the midpoint potential is discharged to the power supply through the storage capacitor, thereby releasing the unbalanced potential and causing the midpoint potential to drop. When the midpoint potential is lower than 0.5Vdc, the inverter circuit outputs from 0 level to -1 level, controlling the power supply energy storage capacitor group and the midpoint potential to be turned on, the power supply is charged to the midpoint potential through the energy storage capacitor group, and the midpoint potential rises; The energy storage capacitor group includes a polar capacitor C5, and the inverter circuit also includes a switch tube Q9, a switch tube Q10, a switch tube Q6, a switch tube Q7, a switch tube Q14, a switch tube Q15, a switch tube Q17, a switch tube Q18, a polar capacitor C1 and a polar capacitor C2. The source of the switch tube Q7 is connected to the drain of the switch tube Q18, and the connection point serves as the midpoint potential. The drain of the switch tube Q7 is connected to the source of the switch tube Q6. The drain of the switch tube Q6 is connected to the drain of the switch tube Q10 and the positive electrode of the polar capacitor C5 respectively. The source of Q10 is connected to the drain of the switching tube Q9, the source of the switching tube Q9 is grounded and connected to the negative electrode of the polarity capacitor C1, and the positive electrode of the polarity capacitor C1 is connected to the positive electrode of the power supply; the source of the switching tube Q18 is connected to the drain of the switching tube Q17, the source of the switching tube Q17 is connected to the source of the switching tube Q15 and the negative electrode of the polarity capacitor C5 respectively, the drain of the switching tube Q15 is connected to the source of the switching tube Q14, the drain of the switching tube Q14 is grounded and connected to the positive electrode of the polarity capacitor C2, and the negative electrode of the polarity capacitor C2 is connected to the negative electrode of the power supply; The energy storage capacitor group includes a polar capacitor C3, and the inverter circuit also includes a switch tube Q1, a switch tube Q2, a switch tube Q13, a switch tube Q3, a switch tube Q11, a switch tube Q12, a switch tube Q4, a switch tube Q8, and a switch tube Q5. The drain of the switch tube Q5 is connected to the drain of the switch tube Q7, the source of the switch tube Q5 is connected to the drain of the switch tube Q4 and the source of the switch tube Q8, the drain of the switch tube Q8 is connected to the drain of the switch tube Q6, and the source of the switch tube Q4 is connected to the drain of the switch tube Q7. The source of the switching tube Q3 is connected, the drain of the switching tube Q3, the positive electrode of the polarity capacitor C3, the drain of the switching tube Q2 and the drain of the switching tube Q11 are connected, the source of the switching tube Q2, the source of the switching tube Q1 and the drain of the switching tube Q13 are connected, the source of the switching tube Q13 is connected to the negative electrode of the polarity capacitor C1, the drain of the switching tube Q1 is connected to the positive electrode of the polarity capacitor C1, the positive electrode of the polarity capacitor C3 is connected to the source of the switching tube Q12, and the drain of the switching tube Q12 is connected to the source of the switching tube Q2; The energy storage capacitor group includes a polar capacitor C4, and the inverter circuit also includes a switch tube Q26, a switch tube Q24, a switch tube Q25, a switch tube Q21, a switch tube Q23, a switch tube Q22, a switch tube Q20, a switch tube Q16, and a switch tube Q19. The source of the switch tube Q19 is connected to the source of the switch tube Q18, the drain of the switch tube Q19 is connected to the source of the switch tube Q20 and the drain of the switch tube Q16, the source of the switch tube Q16 is connected to the source of the switch tube Q17, the drain of the switch tube Q20 is connected to the drain of the switch tube Q21, and the switch The source of the transistor Q21, the negative electrode of the polarity capacitor C4, the source of the switch transistor Q24, and the source of the switch transistor Q23 are connected. The drain of the switch transistor Q24, the drain of the switch transistor Q26, and the source of the switch transistor Q25 are connected. The drain of the switch transistor Q25 is connected to the positive electrode of the polarity capacitor C2. The source of the switch transistor Q26 is connected to the negative electrode of the polarity capacitor C2. The positive electrode of the polarity capacitor C4 is connected to the drain of the switch transistor Q22 and the source of the switch transistor Q11. The source of the switch transistor Q22 is connected to the drain of the switch transistor Q24. The drain of the switch transistor Q23 is connected to the negative electrode of the polarity capacitor C3.

2. The eleven-level inverter circuit according to claim 1, characterized in that: The switch tubes Q9, Q10, Q6 and Q7 are turned on, and the remaining switch tubes are turned off. At this time, the circuit outputs a 0 level.

3. The eleven-level inverter circuit according to claim 1, characterized in that: The switch tubes Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, and the other switch tubes are turned off, and the circuit outputs a +1 level. At this time, the polarity capacitor C5 is charged; the switch tubes Q14, Q15, Q6, and Q7 are turned on, and the other switch tubes are turned off, and the circuit outputs a +2 level; The switching tubes Q13, Q12, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, and the other switching tubes are turned off. The polarity capacitor C3 charges the polarity capacitor C5. At this time, the output is a +2 level voltage. When Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, and Q26 are turned on, and the other switching tubes are turned off, the output is a +3 level voltage, and the polarity capacitor C3 is charged.

4. The eleven-level inverter circuit according to claim 1, characterized in that: The switching tubes Q1, Q2, Q12, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, and the other switching tubes are turned off. The circuit outputs a +3 level voltage and charges the polarity capacitor C5. When Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, and Q26 are turned on and the other switching tubes are turned off, a +4 level voltage is output, the polarity capacitor C3 is charged, and the polarity capacitor C5 is discharged. The switching tubes Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q16, Q20, Q21, Q24, and Q26 are turned on, and the other switching tubes are turned off. The circuit outputs a +4 level and charges the polarity capacitor C5. When outputting a +5 level, in the first stage, the switching tubes Q14, Q15, Q6, Q7, Q1, Q2, Q23, Q24, Q26, and Q11 are turned on, and the other switching tubes are turned off. The polarity capacitor C3 is charged, and the polarity capacitor C4 is charged. In the second stage, the switching tubes Q14, Q15, Q6, Q7, Q1, Q2Q23, Q22, and Q26 are turned on, and the other switching tubes are turned off. The polarity capacitor C3 is charged again. At this time, the circuit outputs a +5 level.

5. The eleven-level inverter circuit according to claim 1, characterized in that: The switch tubes Q26, Q24, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on, and the other switch tubes are turned off. At this time, the circuit outputs a -1 level, and the polarity capacitor C5 is charged; the switch tubes Q9, Q10, Q17, and Q18 are turned on, and the other switch tubes are turned off, and the polarity capacitor C5 is discharged. At this time, the circuit output voltage is a -2 level; Switching tubes Q25, Q22, Q21, Q20, Q16, Q17, Q19, Q18, Q1, Q2, Q3, Q4, and Q8 are turned on, and the other switching tubes are turned off. At this time, the circuit outputs a -2 level, and the polarity capacitor C5 is charged; switching tubes Q9, Q10, Q17, Q18, Q1, Q2, Q11, Q24, and Q26 are turned on, and the other switching tubes are turned off, and the polarity capacitor C5 is discharged. At this time, the circuit outputs a -3 level.

6. The eleven-level inverter circuit according to claim 1, characterized in that: The switching tubes Q26, Q22, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on, and the other switching tubes are turned off. At this time, the circuit outputs a -3 level, and the polarity capacitor C5 is charged; the switching tubes Q9, Q10, Q17, Q18, Q1, Q2, Q11, Q24, and Q26 are turned on, and the other switching tubes are turned off. The polarity capacitor C5 is discharged, and the circuit output voltage is a -4 level; The switch tubes Q26, Q22, Q21, Q20, Q16, Q17, Q18, Q19, Q1, Q2, Q3, Q4, and Q8 are turned on, and the other switch tubes are turned off. At this time, the circuit outputs a -4 level, and the polarity capacitor C5 is charged. When the output is a -5 level, in the first stage, the switch tubes Q9, Q10, Q17, Q18, Q1, Q2, Q23, Q24, Q26, and Q11 are turned on, and the other switch tubes are turned off, and the polarity capacitors C3 and C4 are charged. In the second stage, the switch tubes Q9, Q10, Q17, Q18, Q26, Q24, Q11, Q12, and Q1 are turned on, and the other switch tubes are turned off. At this time, the polarity capacitor C4 is charged again, and the circuit output is a -5 level.

7. The eleven-level inverter circuit according to claim 1, characterized in that: When the midpoint potential is unbalanced, the switching tubes adjust when outputting ±1 levels. When the midpoint potential is higher than 0.5Vdc and the circuit outputs from 0 level to +1 level, the switching tubes Q14, Q15, Q17, Q18, Q13, Q2, Q23, Q24, and Q26 are turned on, and the other switching tubes are turned off. At this time, the circuit output is 0 level, the switching tubes Q13, Q12, Q3, Q4, Q5, Q6, Q7, and Q8 are turned on, and the other switching tubes are turned off. At this time, the circuit output is +1 level, and the charge is released through the path of charging the polar capacitor C3 through the midpoint potential, and the midpoint potential drops. When the midpoint potential is lower than 0.5Vdc and the circuit outputs from 0 level to -1 level, the switching tubes Q9, Q10, Q6, Q7, Q1, Q2, Q11, Q24, and Q25 are turned on, and the other switching tubes are turned off. At this time, the circuit output is 0 level, the power supply is charged to the midpoint potential through the polar capacitor C4, and the midpoint potential rises.

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