Circuit board wiring structure improvement method and circuit board wiring improvement structure

Abstract

The present application provides a circuit board line structure improvement method and a circuit board line improvement structure. The circuit board line structure improvement method comprises the following steps: providing a multi-layer circuit board comprising inner layer lines and surface lines, forming an opening to expose part of the inner layer lines, forming a first conductive line in the opening, on the surface of the inner layer lines and the surface lines, forming a first line layer in the opening, removing the first line layer, the first conductive line and the surface line on the surface of the multi-layer circuit board, and removing part of the first line layer in the opening, forming an adhesive layer in the opening and on the surface of the multi-layer circuit board, forming a second conductive line on the adhesive layer and on the surface of the first line layer in the opening, forming a photoresist layer on the second conductive line on the surface of the multi-layer circuit board, forming a second line layer on the surface of the multi-layer circuit board and in the opening to improve the uniformity of the second line layer, and removing the photoresist layer and part of the second conductive line.

Description

TECHNICAL FIELD

[0001] The present invention relates to an improved method and structure, and more particularly, to an improved method for circuit board line structure and an improved circuit board line structure. BACKGROUND

[0002] Referring to Figures 3A-3G , which is a flow chart of a manufacturing method of a known circuit board line structure. As shown in Figure 3A , in step S31, a multi-layer circuit board 31 is provided, the multi-layer circuit board 31 includes inner layer lines 311 and surface lines 312. As shown in Figure 3B , in step S32, at least one opening 313 is formed in the multi-layer circuit board 31, the at least one opening 311 exposes part of the inner layer lines 311, in this step, the opening 311 is formed using a technique such as laser drilling. As shown in Figure 3C , in step S33, after removing the residue G formed in the opening 311 using laser drilling in step 32, a conductive line 32 is formed in the at least one opening 313 and on the surface lines 312. As shown in Figure 3D , in step S34, a photoresist layer P is formed on the conductive line 32 on the surface of the multi-layer circuit board 31. As shown in Figure 3E , in step S35, a line layer 33 is formed on the surface lines 312 on the surface of the multi-layer circuit board 31 and in the at least one opening 313. As shown in Figure 3F , in step S36, the photoresist layer P is removed. As shown in Figure 3G , in step S37, the conductive line 32 and the surface lines 312 on the surface of the multi-layer circuit board 31 disposed on the position of the photoresist layer P are removed, thereby completing the known circuit board line structure 3.

[0003] As mentioned above, in the above-mentioned circuit board line structure 3, since the surface line formed thereby is formed on the surface of the multi-layer circuit board 31, and in the step of forming the final circuit board line structure 3, the surface line is formed under the line layer 33 to become the bottom copper layer (bottom copper). Further, since the multi-layer circuit board 31 provided in step S31 is formed by pressing the pre-laminated multi-layer board, the surface line 312 has a certain thickness, about 3 μm. However, in the case of the thickness being too thick, for the current modified semi-additive process (mSAP) in the subsequent etching step, the etching bias will reach about 7 μm, that is, in step S37, the lateral double-side length of the removed bottom copper will reach about 7 μm, which will seriously affect the ability of the circuit board to make fine lines. In other words, since the surface line 312 has a thickness of about 3 μm, and in the case of the longitudinal thickness being too thick, the subsequent etching step must increase the etching time, thus increasing the lateral etching length.

[0004] Referring to Figure 3H , which is a partial enlarged schematic view of a known circuit board line structure. In step S35, since the line layer 33 is formed on the surface of the multi-layer circuit board 31 and in at least one opening 313 by using the method of electroless copper plating, the electroless copper plating method cannot effectively control the height of the line layer 33 formed thereby on the surface of the circuit board line structure 3, causing the problem of poor line uniformity. In the current requirement standard of the circuit board line structure 3, the line surface height difference R2 in the line layer 33 should be less than 2 μm in height, but the circuit board line structure 3 formed by the known method has a line surface height difference R2 in the line layer 33 greater than 2 μm in height.

[0005] In addition, the above-mentioned description is for a single line in the line layer 33, however, for the line layer 33 of the circuit board line structure 3, the line layer 33 contains a plurality of lines. When the uniformity of a single line is poor, it further affects the uniformity of the circuit board line structure 3 on the entire surface. In the current requirement standard of the circuit board line structure 3, the range between each line in the line layer 33 should be less than 3.5 μm, but the circuit board line structure 3 formed by the known method has a range between each line in the line layer 33 greater than 10 μm in width.

[0006] Furthermore, in the step of forming the opening in step S32, since the technology of forming the opening 313 easily forms a residual glue G on the surface of the opening 313, the surface of the opening 313 cannot be flat, so that the circuit layer 33 formed in the opening 313 by the way of electroless copper plating in step S35 cannot be flatly and stably arranged in the opening 313, the binding force of the circuit layer 33 on the surface of the low roughness material is reduced, and further the binding force between the circuit layer 33 and the surface (the bottom material) of the multilayer circuit board 31 and the inner edge (the surface) of the opening 313 is affected.

[0007] Therefore, how to provide a circuit board circuit structure improvement method and structure has become a research topic in urgent need at present. SUMMARY

[0008] In view of the above problems, the present application provides a circuit board circuit structure improvement method, comprising the following steps: providing a multilayer circuit board, the multilayer circuit board comprising an inner layer circuit. Forming at least one opening in the multilayer circuit board to expose part of the inner layer circuit. Forming at least one opening on the surface of the multilayer circuit board; forming a first circuit layer in the at least one opening. Forming a second circuit layer on the first circuit layer in the at least one opening and on the surface of the multilayer circuit board, wherein the second circuit layer comprises a plurality of circuits, the height difference between the plurality of circuits on the surface of the at least one opening is less than a first predetermined value, and the circuit distribution range between the plurality of circuits on the surface of the multilayer circuit board is less than a second predetermined value.

[0009] As described above, the circuit board circuit structure improvement method and the improved circuit board circuit structure of the present application use a two-stage circuit hole filling process, including the first stage of using chemical copper prepared by a chemical solution with good hole filling ability to fill the opening, and the second stage of using chemical copper prepared by a chemical solution with good uniformity to be arranged on the first circuit layer in the opening to make up the height of the circuit, so that the height difference between each circuit formed by the circuit layer is less than a first predetermined value, and the circuit distribution range between each circuit of the second circuit layer on the surface of the multilayer circuit board is less than a second predetermined value, thereby improving the uniformity of the circuit. In addition, in the steps of the circuit board circuit structure improvement method, the surface copper thickness of the circuit board circuit structure formed can meet the requirement of being less than or equal to a third predetermined value, which can further improve the development ability of the circuit board circuit structure on fine circuits. Furthermore, by arranging an adhesive layer on the bottom material and the opening, the circuit board circuit structure can improve the binding force and adhesion between the circuit layer and the bottom material and the opening, and further improve the application of the circuit board circuit structure on the 5G products with low roughness material surface in the future. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figures 1A-1K The flow chart of the steps of the circuit board circuit structure improvement method of the present application;

[0011] Figure 1L Partial enlarged view of the circuit board line improvement structure of the present application;

[0012] Figure 2 Cross-sectional view of the circuit board line improvement structure of the present application;

[0013] Figures 3A-3G Flow chart of the manufacturing method of the known circuit board line structure; and

[0014] Figure 3H Partial enlarged view of the known circuit board line structure.

[0015] [Symbol explanation]

[0016] 1: Circuit board line improvement structure

[0017] 11: Multilayer circuit board

[0018] 111: Inner layer line

[0019] 112: Surface line

[0020] 113: Opening

[0021] 12: First conductive line

[0022] 13: First line layer

[0023] 14: Adhesion layer

[0024] 15: Second conductive line

[0025] 16: Second line layer

[0026] 3: Circuit board line structure

[0027] 31: Multilayer circuit board

[0028] 311: Inner layer line

[0029] 312: Surface line

[0030] 313: Opening

[0031] 32: Conductive line

[0032] 33: Line layer

[0033] P: Photoresist layer

[0034] G: Residual glue

[0035] R1: First preset value

[0036] R2: Line surface height difference DETAILED DESCRIPTION

[0037] Please refer toFigures 1A-1K which is a flow chart of the steps of the method for improving the circuit board line structure of the present application. As shown in FIG. 1, in step Sll, a multi-layer circuit board 11 is provided, which includes inner layer lines 111 and surface lines 112. As shown in FIG. 2, in step S12, at least one opening 113 is formed in the multi-layer circuit board 11 to expose part of the inner layer lines 111. As shown in FIG. 3, in step S13, a first conductive line 12 is formed in the at least one opening 113, on the inner layer lines 111 and on the surface lines 112. As shown in FIG. 4, in step S14, a first line layer 13 is formed in the at least one opening 113, so that the first line layer 13 fills the at least one opening 113, and in an embodiment of the present application, the first line layer 13 is disposed on the first conductive line 12 with the thinnest thickness. As shown in FIG. 5, in step S15, the first conductive line 12, the surface lines 112 and the first line layer 13 on the multi-layer circuit board 11 are removed, and part of the first line layer 13 in the at least one opening 113 is removed. As shown in FIG. 6, in step S16, an adhesive layer 14 is formed in the at least one opening 113 and on the multi-layer circuit board 11. As shown in FIG. 7, in step S17, a second conductive line 15 is formed on the adhesive layer 14 and on the first line layer 13 in the at least one opening 113. As shown in FIG. 8, in step S18, a photoresist layer P is formed on the second conductive line 15 on the surface of the multi-layer circuit board 11. As shown in FIG. 9, in step S19, a second line layer 16 is formed in the at least one opening 113 and on the surface of the multi-layer circuit board 11 through the photoresist layer P, so that the surface height difference between each line of the second line layer 16 protruding from the surface of the opening 113 is less than a first preset value, and the line distribution range of each line of the second line layer 16 on the surface of the multi-layer circuit board 11 is less than a second preset value. As shown in FIG. 10, in step S20, the photoresist layer P is removed. As shown in FIG. 11, in step S21, the second conductive line 15 on the multi-layer circuit board 11 disposed at the position of the photoresist layer P is removed, and thus the circuit board line structure 1 is completed. Figure 1A Figure 1B Figure 1C Figure 1D Figure 1E Figure 1F Figure 1G Figure 1H Figure 1I Figure 1J Figure 1K

[0038] In step S12, the method for forming the opening 113 includes laser drilling. In addition, after laser drilling, the residual glue G inside the opening 113 is removed to make the surface inside the opening 113 flat.

[0039] ​​​​​​​​​​​In step S16, the adhesive layer 14 is formed to contact the surface of the first circuit layer 13 in the opening 113. By providing the adhesive layer 14, the bonding force between the second circuit layer 16 and the surface of the bottom multilayer circuit board 11 (the bottom material) and the inner edge (the surface) of the opening 113 can be further improved. In the embodiment of the present application, the pull force test shows that the pull force of the structure without the adhesive layer 14 is 0.03 (kgf / cm), and the pull force of the structure with the adhesive layer 14 is further improved to 0.2-0.3 (kgf / cm).

[0040] In steps S13 and S17, the method for forming the first conductive circuit 12 and the second conductive circuit 15 includes electroplating (copper) with a thickness less than or equal to 0.85 μm, i.e., the surface copper thickness on the surface of the circuit board circuit structure 1 can reach the requirement of less than or equal to 0.85 μm.

[0041] In step S21, the method for removing the second conductive circuit 15 includes etching. In addition to etching and removing the second conductive circuit 15 in the longitudinal direction, the second conductive circuit 15 is also etched in the lateral direction. In an embodiment of the present application, the length of the second conductive circuit 15 etched in the lateral direction (etching bias) is less than 2 μm. Further, since the thickness of the second conductive circuit 15 is less than or equal to 0.85 μm, the length of the second conductive circuit 15 etched in the lateral direction is less than 2 μm in the case of a smaller and thinner thickness in the longitudinal direction.

[0042] In step S14, the method for forming the first circuit layer 13 uses a chemical copper prepared by a chemical solution with good horizontal pulse electroplating hole filling capability to fill the opening.

[0043] In step S17, the method for forming the second conductive circuit 16 uses a chemical copper prepared by a chemical solution with good uniformity to be disposed on the first circuit layer 13 in the opening 113 to compensate the height of the circuit in the opening 113.

[0044] Please refer to Figure 1L , which is a partial enlarged view of the improved circuit board circuit structure of the present application. By the above method, the surface height difference between the circuits formed by the second circuit layer 16 can reach the first preset value R1 of less than 2 μm, and the circuit distribution full range of the circuits of the second circuit layer 16 on the surface of the multilayer circuit board 11 can reach the second preset value of less than 3.5 μm.

[0045] Please refer to Figure 2Fig. 1 is a cross-sectional view of a circuit board line structure according to an embodiment of the present application. The circuit board line structure 1 comprises a multi-layer circuit board 11, a first conductive line 12, a first line layer 13, an adhesive layer 14, a second conductive line 15, and a second line layer 16. The multi-layer circuit board 11 comprises an inner layer line 111 and at least one opening 113 exposing the inner layer line 111. The first conductive line 12 is disposed in the at least one opening 113 and on the inner layer line 111. The first line layer 13 is disposed on the first conductive line 12 in the at least one opening 113, and the height of the first line layer 13 is lower than the depth of the at least one opening 113. The adhesive layer 14 is disposed on the first conductive line 12 in the at least one opening 113 and on the surface of the multi-layer circuit board 11. The second conductive line 15 is disposed on the adhesive layer 14 and on the first line layer 13 in the at least one opening 113. The second line layer 16 is disposed on the second conductive line 15 in the at least one opening 113 and on the second conductive line 15 of the multi-layer circuit board 11, wherein the second line layer 16 comprises a plurality of lines, the surface height difference between each of the lines is less than a first predetermined value, and the line distribution range of each of the lines on the surface of the multi-layer circuit board 11 is less than a second predetermined value.

[0046] In an embodiment of the present application, the thickness of the first conductive line 12 and the second conductive line 15 is less than or equal to 0.85 μm, i.e., the surface copper thickness of the circuit board line structure 1 can reach the requirement of less than or equal to 0.85 μm.

[0047] In an embodiment of the present application, the surface height difference between each of the lines formed by the second line layer 16 reaches the first predetermined value of less than 2 μm, and the line distribution range of each of the lines of the second line layer 16 on the surface of the multi-layer circuit board 11 reaches the second predetermined value of less than 3.5 μm.

[0048] In summary, the circuit board line structure improvement method and the circuit board line improvement structure use two-stage line hole filling processes, including the first stage using chemical copper with good hole filling ability to fill the opening, and the second stage using chemical copper with good uniformity to set on the first line layer in the opening, to make up the height of the line in the opening, so as to achieve the first preset value that the surface height difference between each line formed by the line layer is less than 2μm, and the second preset value that the line distribution full range of each line of the second line layer on the surface of the multi-layer circuit board is less than 3.5μm, thereby improving the uniformity of the line, improving the density of the circuit board structure, and making the line layer have high reliability. In addition, in the steps of the circuit board line structure improvement method, the surface copper thickness of the circuit board line improvement structure can reach the requirement of less than or equal to 0.85μm, which can further improve the development ability of the circuit board line improvement structure on the fine line. Furthermore, the circuit board line improvement structure sets the adhesive layer on the bottom material and the opening, which can improve the bonding force and adhesion between the line layer and the bottom material and the opening, further improve the application of the circuit board line improvement structure on the 5G product with low roughness material surface in the future, and can greatly improve the transmission rate of the 5G product.

Claims

1. A method of modifying a circuit board layout, comprising: The method comprises the following steps: providing a multilayer circuit board, the multilayer circuit board comprising an inner layer circuit; forming at least one opening on a surface of the multilayer circuit board; wherein part of the inner layer circuit is exposed to the at least one opening; forming a first circuit layer in the at least one opening; and forming a second circuit layer on the first circuit layer in the at least one opening and on the surface of the multilayer circuit board; wherein the second circuit layer comprises a plurality of circuits, a surface height difference between the plurality of circuits protruding from a surface of the at least one opening is less than a first preset value, and a circuit distribution range between the plurality of circuits on the surface of the multilayer circuit board is less than a second preset value; wherein the step of forming the first circuit layer comprises: forming a first conductive circuit in the at least one opening and on a surface of the inner layer circuit; wherein the first circuit layer is filled in the at least one opening: wherein the step of forming the second circuit layer comprises: removing the first conductive circuit on the surface of the multilayer circuit board, and removing part of the first circuit layer in the at least one opening; forming an adhesive layer in the at least one opening and on the surface of the multilayer circuit board; forming a second conductive circuit on the adhesive layer and on the first circuit layer in the at least one opening; forming a photoresist layer on the second conductive circuit on the surface of the multilayer circuit board; forming the second circuit layer on the second conductive circuit in the at least one opening and on the second conductive circuit on the surface of the multilayer circuit board through the photoresist layer; removing the photoresist layer; and removing the second conductive circuit on the surface of the multilayer circuit board that is not covered by the second circuit layer.

2. The circuit board wiring structure modification method according to claim 1, wherein A thickness of the second conductive circuit formed on the surface of the multilayer circuit board is less than or equal to 0.85 µm.

3. The circuit board wiring structure modification method according to Claim 1, wherein The second conductive circuit is removed by etching, and a length of the second conductive circuit etched transversely is less than 2 µm.

4. The circuit board wiring structure modification method according to Claim 1, wherein The first preset value is 2 µm.

5. The circuit board wiring structure modification method according to Claim 1, wherein The second preset value is 3.5 µm.

6. A circuit board wiring improvement structure characterized by comprising: The circuit board circuit structure improvement structure is processed by the circuit board circuit structure improvement method of any one of claims 1-5, comprising: a multilayer circuit board comprising an inner layer circuit and at least one opening, part of the inner layer circuit being exposed to the at least one opening; a first circuit layer disposed in the at least one opening, and a height of the first circuit layer being lower than a depth of the at least one opening; and a second circuit layer disposed on the first circuit layer in the at least one opening and on a surface of the multilayer circuit board; wherein the second circuit layer comprises a plurality of circuits, a surface height difference between the plurality of circuits protruding from a surface of the at least one opening is less than a first preset value, and a circuit distribution range between the plurality of circuits on the surface of the multilayer circuit board is less than a second preset value.

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