Semiconductor structure and method of making the same, memory

Abstract

The embodiment of the present application relates to the field of semiconductor, and provides a semiconductor structure, a manufacturing method thereof, and a memory, the semiconductor structure at least can include: a plurality of aligned transistors, the transistors share the same source plate, the channel of the transistor is located on the source plate, and the channel length direction of the transistor is perpendicular to the surface of the source plate, wherein the material of the channel includes single-crystal semiconductor;A plurality of drain contacts are electrically connected with the drain of the transistor, and an even number of the transistors share the same drain contact;A plurality of magnetic tunnel junctions are located on the drain contact, and the magnetic tunnel junction is electrically connected with the drain contact one by one.The embodiment of the present application is beneficial to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductors, and in particular to a semiconductor structure, a manufacturing method thereof, and a memory. Background Art

[0002] Semiconductor memory, including dynamic random access memory (DRAM) and magnetic random access memory (MRAM), is required for data storage in most electronic devices. Data storage requires a certain drive current. However, as semiconductor devices become increasingly miniaturized, the interconnection resistance between adjacent conductors increases as the contact area decreases. This reduces the drive current while maintaining the same drive voltage, making it impossible to maintain the original drive capability. Furthermore, increasing the voltage supplied by the voltage source to maintain the original drive current increases the power consumption of the semiconductor device. Summary of the Invention

[0003] The embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, and a memory, which are at least beneficial to improving the electrical performance of the semiconductor structure and the memory.

[0004] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a semiconductor structure, which may at least include: a plurality of aligned transistors, the transistors sharing the same source plate, the channels of the transistors located on the source plate, the channel length direction of the transistors being perpendicular to the surface of the source plate, wherein the material of the channel includes a single crystal semiconductor; a plurality of drain contacts electrically connected to the drains of the transistors, an even number of the transistors sharing the same drain contact; a plurality of magnetic tunnel junctions located on the drain contacts, the magnetic tunnel junctions being electrically connected to the drain contacts one-to-one.

[0005] According to some embodiments of the present application, another aspect of the present application further provides a memory, which may include at least any one of the semiconductor structures described above.

[0006] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a method for manufacturing a semiconductor structure, which may at least include: providing a plurality of aligned transistors, the transistors sharing the same source plate, the channels of the transistors being located on the source plate, the channel length direction of the transistor being perpendicular to the surface of the source plate, wherein the material of the channel includes a single crystal semiconductor; forming a plurality of drain contacts electrically connected to the drains of the transistors, an even number of the transistors sharing the same drain contact; forming a plurality of magnetic tunnel junctions located on the drain contacts, the magnetic tunnel junctions being electrically connected to the drain contacts one-to-one.

[0007] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0008] The above technical solution provides a new semiconductor structure, which uses a single crystal semiconductor as the channel material of the transistor. Since the single crystal semiconductor has a high carrier mobility, the transistor device prepared based on the single crystal semiconductor has a high switching performance; in addition, when the drain contact is connected to an even number of transistors at the same time, the shape of the drain contact can be a regular rectangle, and the centers of the multiple drain contacts in the same row are on the same straight line. This is beneficial for the situation where the center of the magnetic tunnel junction coincides with the center projection of the drain contact, and the bit line effectively and uniformly contacts each magnetic tunnel junction in its extension direction, thereby ensuring that the semiconductor structure has stable signal transmission performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0010] Figures 1 to 6 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present application.

[0011] Figures 7 to 12 This is a schematic structural diagram corresponding to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0013] Figures 1 to 6 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present application.

[0014] refer to Figures 1 to 3 The semiconductor structure includes: a plurality of aligned transistors, the transistors share a common drain contact 20, the channel 13 of the transistor is located on the source plate 12, the length direction of the channel of the transistor is perpendicular to the surface of the source plate 12, wherein the material of the channel 13 includes a single crystal semiconductor; a plurality of drain contacts 20, connected to the drain 19 of the transistor, an even number of transistors share the same drain contact 20; a plurality of magnetic tunnel junctions 22, located on the drain contact 20, the magnetic tunnel junctions 22 being electrically connected to the drain contact 20 in a one-to-one correspondence.

[0015] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0016] The semiconductor structure includes a substrate 11 and a source plate 12 located on the substrate 11. The substrate 11 can be composed of an insulating material to serve as an isolation function. The substrate 11 can also be a silicon wafer to facilitate the growth of single crystal materials. The source plate 12 can be independent of the transistor, serving as a source contact and providing a source signal for the transistor, or serving as the source of the transistor to receive a source signal. In any case, the material of the source plate 12 is a conductive material, such as at least one of doped silicon, indium tin oxide (ITO), metal molybdenum, metal aluminum, metal titanium or metal copper.

[0017] In some embodiments, the channel 13 of the transistor is in direct contact with the source plate 12, and the channel 13 and the source plate 12 are connected as one. That is, the source plate 12 serves as the source of the transistor, and multiple aligned transistors share the same source plate 12 and the same source signal. This helps reduce process complexity and eliminates the need to use masking and etching processes to prepare multiple discrete sources. The source plate 12 and the channel 13 can be composed of the same single crystal semiconductor. This helps reduce the contact resistance between the source plate 12 and the channel 13, ensuring that each transistor has a large drive current at a preset drive voltage. At the same time, the single crystal semiconductor includes single crystal silicon or single crystal germanium, and the source plate 12 includes doped single crystal silicon or doped single crystal germanium.

[0018] In some embodiments, the semiconductor structure includes a substrate 11, a source plate 12, a first isolation layer 15, a word line 16 and a second isolation layer 17 stacked in sequence. The first isolation layer 15 is arranged between the word line 16 and the source plate 12 to isolate the source plate 12 and the word line 16; the second isolation layer 17 is arranged between adjacent word lines 16 and covers the top surface of the word line 16, mainly used to isolate adjacent word lines 16, and isolate the word line 16 and other stacked film layers located on the second isolation layer 17, and the other stacked film layers include but are not limited to the drain contact 20.

[0019] It can be understood that the material of the first isolation layer 15 and the material of the second isolation layer 17 can be the same or different; at the same time, the second isolation layer 17 can be composed of a first part and a second part, the first part is arranged between adjacent word lines 16, and the second part is arranged between the word lines 16 and other stacked film layers. The material of the first part and the material of the second part can be the same or different. For example, the dielectric constant of the material of the first part is smaller than the dielectric constant of the material of the second part. The first part is mainly used to suppress signal crosstalk between adjacent word lines 16, and the second part is used to suppress signal crosstalk between adjacent transistors and short circuit of the film layers on both sides.

[0020] Furthermore, the gate dielectric layer 14 and the channel 13 sequentially penetrate the second isolation layer 17, the word line 16, and the first isolation layer 15. The bottoms of the gate dielectric layer 14 and the channel 13 are in direct contact with the surface of the source plate 12, and the gate dielectric layer 14 covers the entire sidewall surface of the channel 13. In a direction perpendicular to the surface of the source plate 12, the length of the gate dielectric layer 14 and the channel 13 is equal to the sum of the lengths of the first isolation layer 15, the word line 16, and the second isolation layer 17, and the length of the gate dielectric layer 14 is equal to the length of the channel 13. In other embodiments, the gate dielectric layer 14 is located only between the channel 13 and the word line 16, and the gate dielectric layer 14 only covers a portion of the sidewall of the channel 13. In a direction perpendicular to the surface of the source plate 12, the length of the gate dielectric layer 14 is equal to the length of the word line 16.

[0021] In some embodiments, the gate dielectric layer 14 is made of a high-k material. For example, the gate dielectric layer 14 includes at least one of HfO2, ZrO2, or HfON. Using a high-k material for the gate dielectric layer 14 helps suppress gate leakage current caused by electron tunneling when the gate dielectric layer 14 is relatively thin.

[0022] refer to Figure 4 The semiconductor structure includes a plurality of word lines 16 arranged in sequence. The word lines 16 extend along a first direction D1 and are arranged along a second direction D2, which is perpendicular to the first direction D1. Each word line 16 is used to drive a transistor in the extending direction, and the word lines 16 surround the channel 13. It will be understood that because the word lines 16 surround the channel 13, the width d of each word line 16 in the second direction D2 is greater than the outer diameter of the gate dielectric layer 14.

[0023] In some embodiments, transistors are arranged in an aligned array. The transistor array can be considered to be composed of different rows extending along a first direction D1 and arranged along a second direction D2. Transistors in different rows are aligned in the first direction D1, and the spacing between adjacent rows in the second direction D2 is equal. The spacing between adjacent transistors in the same row can be equal to the spacing between adjacent rows in the second direction D2. Each word line 16 is used to drive all transistors in the same row of the transistor array.

[0024] In some embodiments, multiple transistors sharing a common drain contact 20 are located in at least two rows of a transistor array. Accordingly, the multiple transistors connected to the same drain contact 20 are driven by at least two word lines 16. The drain contacts 20 are arranged in a regular pattern, such as a rectangle or a square, and are arranged in a regular array. The geometric centers of the multiple drain contacts 20 in the same row are aligned on the same line. Thus, when the center of the magnetic tunnel junction coincides with the center projection of the drain contact, the bit line 23 can effectively and uniformly contact each magnetic tunnel junction 22 along its extension direction, ensuring signal transmission stability in the semiconductor structure. In other words, when the geometric centers of the multiple drain contacts 20 in the same row are aligned, the center of the magnetic tunnel junction 22 can coincide with the center projection of the corresponding drain contact 20 without changing the position of the bit line 23 and ensuring effective contact between the bit line 23 and the magnetic tunnel junction 22, thereby ensuring good signal transmission performance between the drain contact 20 and the magnetic tunnel junction 22.

[0025] For example, refer to Figure 5 , 2M transistors share the same drain contact 20, the 2M transistors are located in two adjacent rows of the transistor array, each row has corresponding M transistors, the drain contact 20 is rectangular, where M is an integer greater than or equal to 2, illustratively, when M is equal to 3, 6 transistors share the same drain contact 20; refer to Figure 6 , N 2 The four transistors share the same drain contact 20 , which is in a square shape, wherein N is an integer greater than or equal to 2. Exemplarily, N is equal to 2, and the four transistors share the same drain contact 20 .

[0026] It is understandable that multiple transistors sharing the same drain contact 20 can also be located in the same row of the transistor array; in addition, according to the above description, it can be known that KM transistors share the same drain contact 20, where K and M are both parameters greater than or equal to 2. When K is equal to 2, as shown in FIG. Figure 5 As shown, multiple transistors sharing the same drain contact 20 are located in two rows of the transistor array; when K is equal to 3, multiple transistors sharing the same drain contact 20 are located in three rows of the transistor array; when K is equal to M, refer to Figure 6 , the drain contact 20 is in a square shape.

[0027] In some embodiments, the drain 19 of the transistor is located between the channel 13 and the drain contact 20, and each transistor has a corresponding drain 19, that is, the drains 19 corresponding to different transistors are relatively independent; in other embodiments, the shape of the drain 19 is the same as the shape of the drain contact 20, that is, an even number of transistors share the same drain, and in the direction perpendicular to the surface of the source plate 12, the orthographic projection of the drain contact 20 coincides with the orthographic projection of the drain 19. By setting the shape of the drain 19 to be the same as the shape of the drain contact 20, it is beneficial to increase the contact area between the drain 19 and the drain contact 20 and reduce the contact resistance between the drain 19 and the drain contact 20, thereby ensuring that under a preset driving voltage, the magnetic tunnel junction 22 can receive a larger driving current.

[0028] In some embodiments, in a direction perpendicular to the surface of the source plate 12, the magnetic tunnel junction 22 includes a fixed layer 221, a tunnel junction 222, and a free layer 223 stacked in sequence, the fixed layer 221 covers the surface of the drain contact 20, the fixed layer 221 and the free layer 223 are formed of a ferromagnetic material having in-plane magnetic anisotropy or having perpendicular magnetic anisotropy, the magnetic orientation of the fixed layer 221 remains fixed, and when the magnetic orientations of the free layer 223 and the fixed layer 221 are antiparallel (AP) to each other, the first state (for example, The first state (e.g., logic "1") is stored when the magnetic orientations of the free layer 223 and the fixed layer 221 are parallel to each other (P), and the second state (e.g., logic "0") is stored. The magnetic orientation relationship between the free layer 223 and the fixed layer 221 can be determined by sensing the resistance when the current flows through the magnetic tunnel junction 22, thereby realizing data reading. Accordingly, the transistor can be turned on by activating the word line 16 to generate a write current (i.e., the above-mentioned drive current) flowing through the magnetic tunnel junction 22. The write current can adjust the magnetic orientation of the free layer 223 to realize data storage.

[0029] In some embodiments, the semiconductor structure further includes: a plurality of bit lines 23 arranged in sequence, wherein the arrangement direction of the bit lines 23 is perpendicular to the arrangement direction of the word lines 16, and the bit lines 23 connect all magnetic tunnel junctions 22 in their extension direction, and the bit lines 23 are located above the magnetic tunnel junctions 22. By arranging the bit lines 23 above the magnetic tunnel junctions 22, it is advantageous to avoid the cross-sectional dimensions of the bit lines 23 being restricted by other structures on the same plane, thereby ensuring that the bit lines 23 have a relatively wide dimension in their arrangement direction and a relatively large cross-sectional area in their extension direction, thereby ensuring that the bit lines 23 have a relatively low transmission resistance and a relatively good signal transmission performance.

[0030] In the embodiment of the present application, the semiconductor structure uses a single crystal semiconductor as the channel material of the transistor. Since the single crystal semiconductor has a high carrier mobility, the transistor device prepared based on the single crystal semiconductor has a high switching performance. In addition, when the drain contact is connected to an even number of transistors at the same time, the shape of the drain contact can be a regular rectangle, and the centers of the multiple drain contacts in the same row are on the same straight line. This is beneficial for the situation where the center of the magnetic tunnel junction coincides with the center projection of the drain contact, and the bit line effectively and uniformly contacts each magnetic tunnel junction in its extension direction, thereby ensuring that the semiconductor structure has stable signal transmission performance.

[0031] The present application also provides a memory device comprising any of the aforementioned semiconductor structures. A memory device fabricated based on the aforementioned semiconductor structure has low drive voltage requirements and low inherent losses, thereby reducing heat generation during operation of electronic devices, lowering cooling costs, and improving the competitiveness of electronic devices.

[0032] Figures 7 to 12 The present invention provides a schematic diagram of the structure of each step of the method for manufacturing a semiconductor structure. Figures 7 to 12 The method for manufacturing a semiconductor structure provided in an embodiment of the present application includes the following steps:

[0033] refer to Figure 7 , providing a substrate 11, a source plate 12 and an intrinsic layer 13a stacked in sequence.

[0034] The substrate 11 can be a supporting material for supporting the formation of subsequent film layers, or it can be the base of all the film layers that have been formed. The substrate 11 is only used as an illustration. If the substrate 11 only plays a supporting role, the substrate 11 can be removed after the target structure is formed, or the substrate 11 is not formed. The substrate 11 can also be a silicon wafer to facilitate the growth of single crystal materials; the source plate 12 can serve as the source of the subsequently formed transistor, or provide a source signal for the subsequently formed transistor. The material of the source plate 12 is a conductive material, such as at least one of doped silicon (single crystal silicon, polycrystalline silicon or microcrystalline silicon), indium tin oxide (ITO), metal molybdenum, metal aluminum, metal titanium or metal copper; the material of the intrinsic layer 13a includes a single crystal semiconductor, and the intrinsic layer 13a is used to prepare a transistor channel.

[0035] refer to Figure 8 , etch the intrinsic layer 13a (refer to Figure 7 ), forming a plurality of aligned channels 13.

[0036] In some embodiments, the channel 13 of the transistor is in direct contact with the source plate 12, and the source plate 12 serves as the source of the transistor. Multiple aligned transistors share the same source plate 12 and the same source signal. The source plate 12 and the channel 13 may include the same single crystal semiconductor to reduce the contact resistance between the source plate 12 and the channel 13.

[0037] In some embodiments, the single crystal semiconductor includes single crystal germanium or single crystal silicon, and the material of the intrinsic layer 13a is set to single crystal silicon or single crystal germanium, which is beneficial to improving the carrier transfer rate of the transistor device, thereby improving the switching performance of the transistor array; in addition, forming the channel first and then forming the isolation layer between adjacent transistors is beneficial to expanding the diffusion space of the deposited material, so that the deposited gate dielectric layer can be more evenly attached to the side wall of the channel, so as to ensure that the thickness of the gate dielectric layer of different transistors and different positions of the same transistor is similar, and ensure that the transistor has stable and reliable electrical performance.

[0038] refer to Figure 9 , forming a gate dielectric layer 14 surrounding the sidewalls of the channel 13.

[0039] In some embodiments, the gate dielectric layer 14 is made of a high-k material. For example, the gate dielectric layer 14 includes at least one of HfO2, ZrO2, or HfON. Using a high-k material for the gate dielectric layer 14 helps suppress gate leakage current caused by electron tunneling when the gate dielectric layer 14 is relatively thin.

[0040] refer to Figure 10 , forming a first isolation layer 15 , a plurality of word lines 16 arranged in sequence, and a second isolation layer 17 .

[0041] The first isolation layer 15 is located between the word line 16 and the source plate 12. The first isolation layer 15 is used to isolate the source plate 12 and the word line 16 and to suppress signal crosstalk between adjacent transistors. The word line 16 extends along the first direction D1 and is arranged along the second direction D2. Each word line 16 is used to connect and drive all transistors in the extension direction, wherein the word line 16 surrounds the channel of the driven transistor, and the width of the word line 16 in the second direction D2 is greater than the outer diameter of the gate dielectric layer 14. The second isolation layer 17 fills the space between adjacent word lines 16 and covers the word line 16. The top surface of the word line 16 is flush with the top surface of the second isolation layer 17. The portion of isolation material filled between adjacent word lines 16 and the portion of isolation material covering the top surface of the word line 16 can be different.

[0042] The materials of the first isolation layer 15 and the second isolation layer 17 are both low dielectric constant materials, and the low dielectric constant materials include but are not limited to silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.

[0043] refer to Figure 11 , forming a third isolation layer 18 and a drain 19 , wherein the drain 19 , the channel 13 , the source plate 12 , the gate dielectric layer 14 and a portion of the word line 16 constitute a transistor.

[0044] In some embodiments, an even number of channels 13 share the same drain 19, and multiple transistors sharing the same drain 19 share the same drain contact 20. In the direction perpendicular to the surface of the source plate 12, the drain 19 can have the same shape as the drain contact 20 formed subsequently. In addition, the drain 19 and the channel 13 can contain the same single crystal semiconductor, for example, the channel 13 is single crystal silicon and the drain 19 is doped single crystal silicon; in other embodiments, each transistor corresponds to a drain 19, and the drains 19 corresponding to different transistors are independent of each other. In addition, the material of the drain 19 can also be the same as the material of the source plate 12.

[0045] In some embodiments, the drain 19 and the channel 13 may comprise the same single crystal semiconductor, and the third isolation layer 18 may be formed before the drain 19. It is understood that because the drain 19 and the channel 13 comprise the same material, the etchant for the drain 19 has a faster etching rate for the channel 13. If a conductive layer is formed first and then the drain 19 is etched, the etching process may damage the channel 13, especially if the drain 19 does not completely cover the top surface of the channel 13. In addition, the material of the third isolation layer 18 may be the same as that of the first isolation layer 15 or the second isolation layer 17.

[0046] refer to Figure 12 , forming a drain contact 20 and a fourth isolation layer 21.

[0047] In some embodiments, the shape of the drain contact 20 is the same as the shape of the connected drain, and the contact resistance between the drain 19 and the subsequently formed magnetic tunnel junction 22 is greater than the contact resistance between the drain contact 20 and the magnetic tunnel junction 22. By setting the drain contact 20, it is beneficial to reduce the contact resistance between different conductors, thereby increasing the driving current of the magnetic tunnel junction 22 when the driving voltage is fixed; when the drains 19 of different transistors are relatively independent, setting the drain contact 20 is also beneficial to increase the contact area with the magnetic tunnel junction and support the magnetic tunnel junction, ensuring that magnetic tunnel junctions 22 of any size can be effectively connected to the corresponding transistor.

[0048] In some embodiments, the third isolation layer 18 and the fourth isolation layer 21 are two separate film layers, and the material of the fourth isolation layer 21 is the same as that of the third isolation layer 18; in another embodiment, the drain contact 20 is formed after the drain 19 is formed, and the isolation layers 18 and 21 are formed after the drain contact 20 is formed, and the isolation layers 18 and 19 are respectively filled between adjacent drains 19 and between adjacent drain contacts, that is, the isolation layer 18 filled between adjacent drains and the isolation layer 21 filled between adjacent drain contacts are an integrated structure.

[0049] refer to Figures 1 to 3 , forming a magnetic tunnel junction 22 and a bit line 23.

[0050] The magnetic tunnel junction 22 is located on the drain contact 20, and the magnetic tunnel junction 22 is electrically connected to the drain contact 20 one by one; the bit line 23 is located on the magnetic tunnel junction 22, and the extension direction of the bit line 23 is perpendicular to the extension direction of the word line 16. The arrangement direction of the bit line 23 is perpendicular to the arrangement direction of the word line 16, and each bit line 23 connects all the magnetic tunnel junctions 22 in the extension direction.

[0051] In the embodiment of the present application, the semiconductor structure uses a single crystal semiconductor as the channel material of the transistor. Since single crystal semiconductors have a high carrier mobility, transistor devices prepared based on single crystal semiconductors have high switching performance. In addition, when the drain contact is connected to an even number of transistors at the same time, the shape of the drain contact can be a regular rectangle, and the centers of multiple drain contacts in the same row are on the same straight line. This is beneficial for the situation where the center of the magnetic tunnel junction coincides with the center projection of the drain contact, and the bit line effectively and uniformly contacts each magnetic tunnel junction in its extension direction, thereby ensuring that the semiconductor structure has stable signal transmission performance.

[0052] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: A plurality of aligned transistors, the transistors sharing a common source plate, the channels of the transistors being located on the source plate, the channel lengths of the transistors being perpendicular to a surface of the source plate, wherein the channel material comprises a single crystal semiconductor; a plurality of drain contacts electrically connected to the drains of the transistors, wherein an even number of the transistors share the same drain contact; A plurality of magnetic tunnel junctions are located on the drain contacts, wherein the magnetic tunnel junctions are electrically connected to the drain contacts in a one-to-one correspondence; A plurality of word lines arranged in sequence are located above the source plate and drive the transistors in the extending direction of the word lines, wherein the plurality of transistors connected to the same drain contact are driven by at least two word lines.

2. The semiconductor structure according to claim 1, wherein: The channel of the transistor is in direct contact with the source plate, and the channel and the source plate are connected as one.

3. The semiconductor structure according to claim 1, wherein: The source plate includes the single crystal semiconductor.

4. The semiconductor structure according to claim 3, wherein: The single crystal semiconductor includes single crystal silicon or single crystal germanium.

5. The semiconductor structure according to claim 1, wherein: The word line surrounds the channel.

6. The semiconductor structure according to claim 5, wherein: Also includes: A plurality of bit lines are arranged in sequence, wherein the arrangement direction of the bit lines is perpendicular to the arrangement direction of the word lines, each of the bit lines connects all the magnetic tunnel junctions in an extension direction, and the bit lines are located on the magnetic tunnel junctions.

7. The semiconductor structure according to claim 5, wherein: Also includes: A gate dielectric layer is located between the channel and the word line and surrounds the channel, wherein a material of the gate dielectric layer includes at least one of HfO 2 , ZrO 2 or HfON.

8. The semiconductor structure according to claim 7, wherein: In a direction perpendicular to the surface of the source plate, the length of the gate dielectric layer is equal to the length of the channel, or the length of the gate dielectric layer is equal to the length of the word line.

9. The semiconductor structure according to claim 1, wherein: The drain contact is square or rectangular.

10. The semiconductor structure according to claim 9, wherein: N 2 The transistors share the same drain contact, and the drain contact is square; wherein N is an integer greater than or equal to 2.

11. The semiconductor structure according to claim 10, wherein: 2M transistors share the same drain contact, and the drain contact is rectangular; wherein M is an integer greater than or equal to 2.

12. A memory, characterized in that: A semiconductor structure comprising the semiconductor structure according to any one of claims 1 to 11.

13. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a plurality of aligned transistors, wherein the transistors share a common source plate, the channels of the transistors are located on the source plate, the length direction of the channels of the transistors is perpendicular to the surface of the source plate, wherein the material of the channels comprises a single crystal semiconductor; forming a plurality of drain contacts electrically connected to the drains of the transistors, wherein an even number of the transistors share the same drain contact; forming a plurality of magnetic tunnel junctions located on the drain contacts, wherein the magnetic tunnel junctions are electrically connected to the drain contacts in a one-to-one correspondence; A plurality of word lines arranged in sequence are formed above the source plate, and the word lines drive the transistors in the direction in which the word lines extend, wherein the plurality of transistors connected to the same drain contact are driven by at least two word lines.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: The process steps for forming the transistor include: forming the source plate and the intrinsic layer in a stacked arrangement; Etching the intrinsic layer to form a plurality of aligned channels; forming a gate dielectric layer surrounding the sidewalls of the channel; A first isolation layer is formed, where the first isolation layer is located between the word line and the source plate, and the word line surrounds the gate dielectric layer in a direction in which the word line extends.

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