A flexible antiferroelectric neuromorphic transistor and its preparation method

Abstract

The present invention discloses a flexible antiferroelectric neuromorphic transistor and a method for preparing the same. The flexible antiferroelectric neuromorphic transistor comprises: a flexible substrate; a gate electrode film formed on the flexible substrate; a transition layer made of a high-k dielectric material formed on the gate electrode film; an antiferroelectric functional film stack formed by overlapping multiple hafnium-based ferroelectric films and an antiferroelectric induction layer, formed on the transition layer; silicon nanowires, the surfaces of which are coated with a two-dimensional semiconductor film and a two-dimensional ferroelectric film, arranged in parallel and spaced apart from each other, formed on the antiferroelectric functional film stack; and source and drain electrodes formed on both sides of each nanowire.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a flexible antiferroelectric neuromorphic transistor and a preparation method thereof. Background Art

[0002] As a new type of production and processing technology for high-quality oxides, atomic layer deposition technology can achieve atomic-scale thickness controllability, self-limitation and excellent step coverage compared to physical vapor deposition, thermal evaporation and other process methods. It is very suitable for growing sub-nanometer-thick gate dielectric materials and provides a core functional layer for the miniaturization of integrated circuits.

[0003] At present, hafnium-based ferroelectric materials (HfZrOx, HfSiOx, HfAlOx, HfLaOx, etc.) based on atomic layer deposition have attracted widespread attention. Compared with traditional perovskite ferroelectric materials, they have advantages such as good CMOS process compatibility, environmental friendliness, and nanoscale thickness size (~10nm). However, hafnium-based ferroelectric materials often lead to poor durability and reduced reliability during the process of continuous polarization reversal, which is very unfavorable for the continuous use of memory. On the other hand, the inherent polarization reversal behavior of hafnium-based ferroelectric materials can ensure the non-volatile storage of devices, but it is difficult to apply to volatile neuromorphic transistors. Therefore, it is necessary to develop hafnium-based ferroelectric thin film materials with more stable performance and volatility to meet the growing demand for neuromorphic transistors.

[0004] Antiferroelectricity, a novel property of ferroelectric materials, stems primarily from the phenomenon of oppositely directed spontaneous polarizations between adjacent lattices. When a voltage is applied, when the applied electric field is greater than the reverse folding field, the material exhibits macroscopic ferroelectric properties. However, when the applied electric field is less than the reverse folding field, the macroscopic polarization decreases, returning to the antiferroelectric phase. This property of the material is well-suited for applications in volatile memory and neuromorphic applications, and the development of related antiferroelectric devices is of great value in the research of neuromorphic transistors. Summary of the Invention

[0005] The present invention discloses a flexible one-dimensional antiferroelectric neuromorphic transistor and a preparation method thereof. Low-temperature atomic layer deposition technology is used to grow a four-element doped antiferroelectric oxide on a flexible substrate. The antiferroelectricity is regulated by controlling the Zr element doping ratio. One-dimensional silicon nanowires wrapped with molybdenum sulfide are used as the channel material of the neuromorphic transistor to construct a volatile flexible one-dimensional antiferroelectric neuromorphic transistor.

[0006] The flexible antiferroelectric neuromorphic transistor includes: a flexible substrate; a gate electrode film formed on the flexible substrate; a transition layer, which is a high-k dielectric material, formed on the gate electrode film; an antiferroelectric functional film stack, which is composed of multiple hafnium-based ferroelectric films and an antiferroelectric induction layer overlapped, and is formed on the transition layer; silicon nanowires, whose surface is coated with a two-dimensional semiconductor film and a two-dimensional ferroelectric film, which are spaced apart and arranged in parallel, and are formed on the antiferroelectric functional film stack; and a source electrode and a drain electrode, which are formed on both sides of each of the nanowires.

[0007] In the flexible antiferroelectric neuromorphic transistor of the present invention, preferably, the gate electrode thin film is PEDOT:PSS.

[0008] In the flexible antiferroelectric neuromorphic transistor of the present invention, preferably, the hafnium-based ferroelectric thin film is HfLaOx or HfZrOx.

[0009] In the flexible antiferroelectric neuromorphic transistor of the present invention, preferably, the antiferroelectric induction layer is a ZrO2 thin film.

[0010] In the flexible antiferroelectric neuromorphic transistor of the present invention, preferably, the two-dimensional semiconductor film is MoS2, HfS2, PtS2, WS2, MoSe2, HfSe2, PtSe2, WSe2, MoTe2, HfTe2, PtTe2 or WTe2.

[0011] The method for preparing a flexible antiferroelectric neuromorphic transistor of the present invention comprises the following steps: forming a gate electrode film on a flexible substrate; forming a high-k dielectric material as a transition layer on the gate electrode film; sequentially forming a hafnium-based ferroelectric film and an antiferroelectric induction layer on the transition layer, repeating the process multiple times, and performing a rapid thermal annealing treatment in an inert gas atmosphere to achieve crystallization of the ferroelectric film and the antiferroelectric film to obtain an antiferroelectric functional film stack; forming silicon nanowires spaced apart and arranged in parallel on the antiferroelectric functional film stack, forming a two-dimensional semiconductor film and a two-dimensional ferroelectric film on the surfaces of the silicon nanowires; and forming a source electrode and a drain electrode on both sides of each of the nanowires.

[0012] In the method for preparing a flexible antiferroelectric neuromorphic transistor of the present invention, preferably, the hafnium-based ferroelectric thin film is HfLaOx or HfZrOx.

[0013] In the method for preparing a flexible antiferroelectric neuromorphic transistor of the present invention, preferably, the antiferroelectric induction layer is a ZrO2 thin film.

[0014] In the method for preparing a flexible antiferroelectric neuromorphic transistor of the present invention, preferably, the temperature of the rapid thermal annealing treatment is 400° C. to 700° C., and the time is 10s to 60s.

[0015] In the method for preparing the flexible antiferroelectric neuromorphic transistor of the present invention, preferably, the length of the silicon nanowire is 10 μm to 50 μm, and the diameter is 10 nm to 100 nm.

[0016] Beneficial effects:

[0017] 1) Breaking with the traditional non-volatile control method, the low-temperature atomic layer deposition technology is used to introduce a four-element doped antiferroelectric functional layer including zirconium as the core dielectric film. This not only improves the durability of the device, but also enables the device to achieve volatile neuromorphic control based on antiferroelectricity, which is more advantageous when simulating volatile neuronal functions.

[0018] (2) Designing an antiferroelectric transistor with a one-dimensional structure to realize neuromorphic computing, the heterogeneous integration of the two-dimensional InSe ferroelectric film on the one-dimensional MoS2 nanowire not only shrinks the dimension of the chip from the traditional three-dimensional to one-dimensional, but also has great advantages in terms of chip size reduction and high-density integration.

[0019] (3) A HfAlOx transition layer is introduced at the bottom of the multilayer ferroelectric film to improve the voltage resistance and bending fracture simulation capability of the transistor. The preparation of flexible one-dimensional antiferroelectric neuromorphic transistors lays the foundation for the development of wearable devices and broadens the application scenarios of neuromorphic wearable electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a flow chart of the method for preparing flexible antiferroelectric neuromorphic transistors.

[0021] Figures 2 to 8 Schematic diagram of the structures of each stage of the flexible antiferroelectric neuromorphic transistor preparation method. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0023] In the description of the present invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In addition, many specific details of the present invention are described below, such as device structure, materials, dimensions, processing techniques, and technologies, to facilitate a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without following these specific details. Unless otherwise noted below, various components of the device may be constructed from materials known to those skilled in the art, or materials with similar functions developed in the future may be used.

[0025] Figure 1 This is a flow chart of the method for preparing a flexible antiferroelectric neuromorphic transistor. Figure 1 As shown, the method for preparing a flexible antiferroelectric neuromorphic transistor includes the following steps:

[0026] Step S1, a gate electrode thin film PEDOT:PSS101 is prepared on the surface of a mica substrate 100 by solution spin coating or evaporation, and then annealed in a glove box filled with an inert gas such as nitrogen. The annealing temperature is 60-150°C, and the thickness is controlled to be 100-200nm. The obtained structure is as shown in FIG. Figure 2 shown.

[0027] Step S2, using atomic layer deposition to grow a three-element high-k dielectric film of HfAlOx, HfTiOx, HfSiOx, HfTaOx on the surface of the gate electrode film 101 as a transition layer 102, the resulting structure is as follows Figure 3 The growth chamber temperature is set to 20-100°C, and the film thickness is controlled to be 3-10 nm.

[0028] In step S3, a first HfLaOx thin film 103 is grown on the transition layer 102 by atomic layer deposition (ALD), with the growth chamber temperature set at 20-100°C and the film thickness controlled to be 3-5 nm. Next, a first ZrO2 thin film 104 is grown on the above structure by ALD, with the growth chamber temperature set at 20-100°C and the film thickness controlled to be 5-8 nm.

[0029] A second layer of HfLaOx 105 is grown on the structure using atomic layer deposition (ALD), covering the first ZrO2 film 104. The growth chamber temperature is set at 20°C to 100°C, and the film thickness is controlled to be 3-5 nm. Next, a second layer of ZrO2 film 106 is grown on the structure using ALD. The growth chamber temperature is set at 20°C to 100°C, and the film thickness is controlled to be 5-8 nm.

[0030] A third layer of HfLaOx 107 is grown on the structure using atomic layer deposition (ALD), covering the second ZrO2 film 106. The growth chamber temperature is set at 20-100°C, and the film thickness is controlled to be 3-5 nm. A third layer of ZrO2 film 108 is also grown on the structure using ALD. The growth chamber temperature is set at 20-100°C, and the film thickness is controlled to be 5-8 nm. This forms a four-element antiferroelectric functional layer with an overlapping structure of a three-element high-k hafnium-based ferroelectric film and an antiferroelectric inducing layer.

[0031] The film is then subjected to a rapid thermal annealing treatment at 400-700°C for 10-60s in an inert gas atmosphere such as nitrogen or argon to achieve crystallization of the three-element high-k hafnium-based ferroelectric film and the antiferroelectric induction layer, thereby obtaining a functional film stack with antiferroelectric properties on a macroscopic scale. The resulting structure is as follows: Figure 4 shown.

[0032] In this embodiment, HfLaOx is used as the ferroelectric layer, but the present invention is not limited to this. Alternatively, a three-element high-k hafnium-based ferroelectric thin film such as HfZrOx can be used. Furthermore, in this embodiment, a triple stacked structure of HfLaOx103 / ZrO2104 / HfLaOx105 / ZrO2106 / HfLaOx107 / ZrO2108 is formed, but the present invention is not limited to this. The number of stacked layers can be adjusted based on actual conditions.

[0033] Step S4, the silicon nanowires 201 prepared by low pressure chemical vapor deposition are transferred from the original substrate to the target substrate by ultrasound assistance using ethanol or isopropyl alcohol as a solvent, so that the silicon nanowires are spaced apart and arranged in parallel, and a silicon nanowire array is obtained on the surface of the antiferroelectric functional film stack, such as Figure 5 As shown. The silicon nanowires have a length of 10μm to 50μm and a diameter of 10nm to 100nm. Low-pressure chemical vapor deposition (LPCVD) is used to prepare silicon nanowires by growing a 1-3nm thick Au film on a 100nm thick silicon oxide substrate 200 in a silane atmosphere at a temperature of 300-600°C for 1-3 hours.

[0034] Step S5, using atomic layer deposition to grow a two-dimensional semiconductor film 202 such as MoS2, HfS2, PtS2, WS2, MoSe2, HfSe2, PtSe2, WSe2, MoTe2, HfTe2, PtTe2, or WTe2 on the surface of the silicon nanowire 201 as the inner layer material of the channel, Figure 6 The growth temperature is controlled at 400-600°C and the thickness is controlled at 1-10nm.

[0035] Afterwards, a two-dimensional ferroelectric thin film 203 of In2Se3 is transferred onto the surface of the target Si2O1 / MoS22O2 nanowire by mechanical exfoliation, with a thickness controlled at 1-10 nm, to form a heterostructure of Si / MoS2 / In2Se3, which is used as a channel material together. Figure 7 shown.

[0036] Step S6, using physical vapor deposition, electron beam evaporation, thermal evaporation, etc., Ti / Pt, Ti / Au, Ti / Pd, Ti / Al, Cr / Pt, Cr / Au, Cr / Pd, Cr / Al, etc. as the source electrode 109 and the drain electrode 110 on both sides of the Si nanowire 201 coated with MoS2202 / In2Se3203 to complete the preparation of the flexible antiferroelectric neuromorphic transistor, as shown in FIG. Figure 8 shown.

[0037] The present invention utilizes low-temperature atomic layer deposition (ALD) technology to introduce a ZrO2 stacking method to construct a Lego-like stacked antiferroelectric functional layer, which exhibits atomic-level thickness controllability and perfect step coverage, enabling controlled growth on a flexible substrate. By overlapping the growth of ZrO2 nanofilms and HfLaOx, the Zr doping ratio in the overall film is controlled to construct a four-element doped antiferroelectric functional layer. Furthermore, by utilizing the antiferroelectric layer as the dielectric layer and MoS2-coated silicon nanowires as the channel material, a volatile one-dimensional antiferroelectric neuromorphic transistor design is realized.

[0038] like Figure 8 As shown, the flexible antiferroelectric neuromorphic transistor includes: a flexible substrate 100; a gate electrode film 101, formed on the flexible substrate 100; a transition layer 102, which is a high-k dielectric material, formed on the gate electrode film 101; an antiferroelectric functional film stack HfLaOx103 / ZrO2104 / HfLaOx105 / ZrO2106 / HfLaOx107 / ZrO2108, which is composed of a triple hafnium-based ferroelectric film and an antiferroelectric inducing layer overlapped, formed on the transition layer 102; a silicon nanowire 201, whose surface is coated with a two-dimensional semiconductor film 202 and a two-dimensional ferroelectric film 203, which are spaced apart and arranged in parallel, and formed on the antiferroelectric functional film stack; a source electrode 109 and a drain electrode 110, formed on both sides of each nanowire.

[0039] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A flexible antiferroelectric neuromorphic transistor, characterized in that: include: Flexible substrate; a gate electrode film formed on the flexible substrate; a transition layer, which is a high-k dielectric material and is formed on the gate electrode film; an antiferroelectric functional thin film stack, formed by overlapping multiple hafnium-based ferroelectric thin films and antiferroelectric induction layers, and formed on the transition layer; a plurality of silicon nanowires, each of which is coated with a two-dimensional semiconductor film and a two-dimensional ferroelectric film, and the plurality of silicon nanowires are spaced apart and arranged in parallel, and are formed on the antiferroelectric functional film stack; A source electrode and a drain electrode are formed on both sides of each of the silicon nanowires. Wherein, the two-dimensional semiconductor film is MoS2, HfS2, PtS2, WS2, MoSe2, HfSe2, PtSe2, WSe2, MoTe2, HfTe2, PtTe2 or WTe2.

2. The flexible antiferroelectric neuromorphic transistor according to claim 1, characterized in that The gate electrode film is PEDOT:PSS.

3. The flexible antiferroelectric neuromorphic transistor according to claim 1, wherein: The hafnium-based ferroelectric thin film is HfLaOx or HfZrOx.

4. The flexible antiferroelectric neuromorphic transistor according to claim 1, wherein: The antiferroelectric induction layer is a ZrO2 thin film.

5. A method for preparing a flexible antiferroelectric neuromorphic transistor, characterized in that: The following steps are involved: forming a gate electrode thin film on a flexible substrate; forming a high-k dielectric material as a transition layer on the gate electrode film; forming a hafnium-based ferroelectric thin film and an antiferroelectric induction layer on the transition layer in sequence, repeating the process multiple times, and performing a rapid thermal annealing process in an inert gas atmosphere to achieve crystallization of the ferroelectric thin film and the antiferroelectric thin film, thereby obtaining an antiferroelectric functional thin film stack; forming a plurality of silicon nanowires spaced apart from each other and arranged in parallel on the antiferroelectric functional thin film stack, and forming a two-dimensional semiconductor film and a two-dimensional ferroelectric film on the surface of each of the silicon nanowires; forming a source electrode and a drain electrode on both sides of each of the silicon nanowires, Wherein, the two-dimensional semiconductor film is MoS2, HfS2, PtS2, WS2, MoSe2, HfSe2, PtSe2, WSe2, MoTe2, HfTe2, PtTe2 or WTe2, The temperature of the rapid thermal annealing treatment is 400° C. to 700° C., and the time is 10s to 60s.

6. The method for preparing a flexible antiferroelectric neuromorphic transistor according to claim 5, wherein: The hafnium-based ferroelectric thin film is HfLaOx or HfZrOx.

7. The method for preparing a flexible antiferroelectric neuromorphic transistor according to claim 5, wherein: The antiferroelectric induction layer is a ZrO2 thin film.

8. The method for preparing a flexible antiferroelectric neuromorphic transistor according to claim 5, wherein: The silicon nanowire has a length of 10 μm to 50 μm and a diameter of 10 nm to 100 nm.

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