Torque equalization fault response for electric vehicles

Abstract

The present disclosure relates to torque equalization fault response for electric vehicles. Various embodiments of the present invention include an exemplary controller, dual power inverter modules, and an electric vehicle. In an exemplary embodiment, the controller includes one or more processors associated with a first power inverter and a second power inverter for a drive unit. A computer readable medium for the one or more processors is each configured to store computer executable instructions configured to cause the one or more processors to apply a same fault action to the first power inverter and the second power inverter in response to a fault associated with an inverter selected from the first power inverter and the second power inverter, wherein the same fault action includes applying an equalized torque to each wheel axle operatively coupled to the drive unit.

Description

[0001] INTRODUCTION

[0002] The present disclosure relates to inverters for drive units of electric vehicles. A conventional electric vehicle having two electric motors per drive unit has two inverters (one per motor), and each inverter is controlled by its own inverter controller. The use of separate inverter controllers for each inverter increases weight and increases energy consumption, resulting in reduced vehicle range. SUMMARY

[0003] Various disclosed embodiments include an exemplary controller, a dual power inverter module, and an electric vehicle.

[0004] In an exemplary embodiment, a controller includes one or more processors associated with a first power inverter and a second power inverter for a drive unit of an electric vehicle. One or more computer-readable media for the one or more processors are each configured to store computer-executable instructions configured to cause its associated processor to apply a same fault action to the first power inverter and the second power inverter in response to a fault associated with an inverter selected from the first power inverter and the second power inverter, wherein the same fault action includes applying an equalized torque to each wheel axle operatively coupled to the drive unit.

[0005] In another exemplary embodiment, a dual power inverter module includes a DC link capacitor electrically connectable to a high voltage direct current (DC) power source. A first power inverter is electrically connectable to the DC link capacitor and is configured to convert the high voltage DC power to three-phase high voltage alternating current (AC) power. The first power inverter is further configured to supply the three-phase high voltage AC power to a first electric motor. A second power inverter is electrically connectable to the DC link capacitor and is configured to convert the high voltage DC power to three-phase high voltage AC power. The second power inverter is further configured to supply the three-phase high voltage AC power to a second electric motor. A controller includes one or more processors associated with the first power inverter and the second power inverter for a drive unit of an electric vehicle. One or more computer-readable media for the first processor and a second computer-readable media are each configured to store computer-executable instructions configured to cause its associated processor to apply a same fault action to the first power inverter and the second power inverter in response to a fault associated with an inverter selected from the first power inverter and the second power inverter, wherein the same fault action includes applying an equalized torque to each wheel axle operatively coupled to the drive unit.

[0006] In another illustrative embodiment, an electric vehicle includes a vehicle body, a high voltage direct current (DC) battery disposed within the vehicle body, a first electric motor and a second electric motor (e.g., left and right electric motors) that are mechanically couplable to rotate at least one set of wheel axles (e.g., to a wheel), and at least one dual power inverter module. The at least one dual power inverter module includes a DC link capacitor electrically connectable to the high voltage DC battery, a first power inverter electrically connectable to the DC link capacitor and configured to convert the high voltage DC power to three-phase high voltage alternating current (AC) power, the first power inverter being further configured to supply the three-phase high voltage AC power to an electric motor selected from the first electric motor and the second electric motor (e.g., left and right electric motors), a second power inverter electrically connectable to the DC link capacitor and configured to convert the high voltage DC power to three-phase high voltage AC power, the second power inverter being further configured to supply the three-phase high voltage AC power to another electric motor selected from the left electric motor and the right electric motor, and a common controller electrically connectable to the first power inverter and the second power inverter. The common controller is configured to control the first power inverter and the second power inverter. The common controller includes one or more processors associated with the first power inverter and the second power inverter. One or more computer-readable media for the first processor and the second processor are each configured to store computer-executable instructions configured to cause its associated processor to apply a same failure action to the first power inverter and the second power inverter in response to a fault associated with an inverter selected from the first power inverter and the second power inverter, where the same failure action includes applying an equalized torque to each wheel axle operatively coupled to the drive unit.

[0007] The above summary is intended to be illustrative and not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent to those skilled in the art upon examination of the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0008] Illustrative embodiments are illustrated in referenced drawings. The embodiments disclosed herein and in the drawings are intended to be illustrative and not limiting in any way.

[0009] FIG. 1A is a schematic diagram of an illustrative electric vehicle having at least one drive unit.

[0010] FIG. 1B is a perspective view of a lower vehicle body structure of the electric vehicle of FIG. 1 with an illustrative drive unit.

[0011] FIG. 2A yes FIG. 1B A perspective view of an exemplary driving unit.

[0012] FIG. 2B yes FIG. 1B Another perspective view of the drive unit.

[0013] FIG. 2C yes FIG. 1B Side plan view of the drive unit.

[0014] FIG. 2D yes FIG. 1B An exploded perspective view of the drive unit.

[0015] FIG. 2E This is a perspective view of another exemplary drive unit.

[0016] FIG. 3A It is a block diagram in the form of a partial schematic of an exemplary dual inverter with common control.

[0017] FIG. 3B This is a perspective view of an exemplary dual inverter with common control.

[0018] FIG. 4A This is a simplified schematic diagram of an exemplary dual inverter with a common DC link capacitor.

[0019] FIG. 4B and FIG. 4C It is a graph of the waveform without the elimination of ripples.

[0020] FIG. 4D This is a flowchart illustrating an exemplary method for synchronizing pulse width modulation clocks.

[0021] FIG. 4E and FIG. 4F It is a graph of an exemplary ripple waveform with elimination.

[0022] FIG. 4G The lookup table is shown.

[0023] FIG. 5A This is a block diagram of an exemplary component of a drive unit configured to place two inverters in a safe state in response to a detected fault associated with either inverter.

[0024] FIG. 5B It is a curve of torque versus speed.

[0025] FIG. 5C yes FIG. 5A A block diagram detailing the components.

[0026] FIG. 5D This is a simplified schematic diagram of an open-circuit upper and lower three-terminal power semiconductor device.

[0027] FIG. 5E is a simplified schematic diagram of a lower group of three-terminal power semiconductor devices shorted.

[0028] FIG. 5F is a simplified schematic diagram of an upper group of three-terminal power semiconductor devices shorted.

[0029] FIG. 5G is a flowchart of an illustrative method of placing two inverters of a drive unit in a safe state in response to a detected fault associated with either inverter.

[0030] FIG. 6A is a schematic diagram of an illustrative circuit for detecting loss of low voltage DC power.

[0031] FIG. 6B is a block diagram in the form of a partial schematic diagram of details of an illustrative backup circuit for providing low voltage DC power.

[0032] FIG. 6C is a flowchart of a method of placing two inverters of a drive unit in a safe state in response to loss of low voltage DC power.

[0033] Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION

[0034] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments can be utilized, and other changes can be made, without departing from the spirit or scope of the subject matter presented herein.

[0035] Various disclosed embodiments include illustrative dual power inverter modules, electric vehicles, and methods.

[0036] Reference is now made to FIG. 1A and FIG. 1BAnd given in overview, in various embodiments, the electric vehicle 10 includes a vehicle body 12. A high-voltage direct current (DC) battery 14 is disposed within the vehicle body 12. Left and right front wheels 16 (only the left front wheel 16 is shown) and left and right rear wheels 18 (only the left rear wheel 18 is shown) are configured to rotate. At least one drive unit 20 is mechanically couplable to rotate the front wheels 16 or the rear wheels 18 (and in some embodiments, one drive unit 20 is mechanically couplable to rotate the front wheels 16 and another drive unit 20 is mechanically couplable to rotate the rear wheels 18). Each drive unit 20 is electrically connectable to receive high-voltage DC power from the battery 14. Each drive unit 20 includes wheel shafts 22A and 22B that are mechanically couplable to rotate the associated wheels 16 or 18; and electric motors 24A and 24B that are mechanically couplable to rotate their associated wheel shafts 22A and 22B, respectively. As will be explained below, each drive unit 20 also includes a dual-power inverter module 26 that is electrically connectable to receive high-voltage DC power from the battery 14. The dual-power inverter module 26 includes two inverters (not shown) that are configured to generate three-phase high-voltage alternating current (AC) power from the high-voltage DC power and to provide the three-phase high-voltage AC power to the associated electric motor. A common controller (not shown) is configured to control both of the inverters in the dual-power inverter module 26.

[0037] For the sake of conciseness, the illustrative details are set forth below in the context of a motor vehicle by way of non-limiting example. However, it should be understood that the vehicle 10 can be any type of vehicle as desired, without limitation. By way of non-limiting example, in various embodiments, the vehicle 10 can be an electric vehicle (i.e., a full electric vehicle) or a hybrid vehicle. For example and by way of non-limiting example, in various embodiments, the vehicle 10 can include a motorized vehicle that is driven by wheels and / or tracks, such as but not limited to a car, a truck, a sport utility vehicle (SUV), a van, an all-terrain vehicle (ATV), a motorcycle, an electric bicycle, a tractor, a lawn mower such as but not limited to a riding lawn mower, a snowmobile, etc. By way of further non-limiting example, in various embodiments, the vehicle 10 can include a nautical vessel, such as but not limited to a boat, a ship, a submarine, a submersible, an autonomous underwater vehicle (AUV), etc. By way of further non-limiting example, in various embodiments, the vehicle 10 can include an aircraft, such as but not limited to a fixed-wing aircraft, a rotary-wing aircraft, and a lighter-than-air (LTA) aircraft.

[0038] Additionally, for the sake of brevity, illustrative details about the drive unit 20 are set forth in the context of a motor vehicle. As the vehicle 10 is not limited to the illustrative example of a motor vehicle, it should be appreciated that the drive unit 20 is also not limited to being suitable for use in a motor vehicle. To this end, in various embodiments, the motor(s) of the drive unit 20 are configured to drive the vehicle 10. That is, in various embodiments, the electric motor(s) of the drive unit 20 can drive any drive member that drives any propulsion device, such as but not limited to one or more wheels, one or more tracks, one or more propellers, one or more thrusters, one or more rotors, etc. associated with the vehicle 10.

[0039] For example, in some embodiments of a motor vehicle, one drive unit 20 can include one motor configured to drive one drive member (such as an axle or a chain ring) that drives one wheel or track; in some other embodiments of a motor vehicle, one drive unit 20 can include one motor configured to drive an axle that rotates two wheels or two tracks; and in some other embodiments of a motor vehicle, one drive unit 20 can include one motor configured to drive an axle that rotates one wheel or track and another motor configured to drive another axle that rotates another wheel or track.

[0040] Similarly, in some embodiments of a marine vessel, one drive unit 20 can include one motor configured to drive one propeller or thruster; in some other embodiments of a marine vessel, one drive unit 20 can include one motor configured to drive a shaft that rotates two propellers or two thrusters; and in some other embodiments of a marine vessel, one drive unit 20 can include one motor configured to drive a shaft that rotates one propeller or thruster and another motor configured to drive another shaft that rotates another propeller or thruster.

[0041] Likewise, in some embodiments of an aircraft, one drive unit 20 can include one motor configured to drive one propeller or rotor; in some other embodiments of an aircraft, one drive unit 20 can include one motor configured to drive a shaft that rotates two propellers or two rotors; and in some other embodiments of an aircraft, one drive unit 20 can include one motor configured to drive a shaft that rotates one propeller or rotor and another motor configured to drive another shaft that rotates another propeller or rotor.

[0042] Now that the overview has been given, illustrative details will be explained with examples, which are given for illustrative purposes only and not as limitations.

[0043] As described above, at least one drive unit 20 is mechanically coupled to rotate the front wheel 16 or the rear wheel 18 (and in some embodiments, one drive unit 20 is mechanically coupled to rotate the front wheel 16, and another drive unit 20 is mechanically coupled to rotate the rear wheel 18). Also as mentioned above, each drive unit 20 includes axles 22A and 22B, which are mechanically coupled to rotate the associated wheel 16 or 18; and electric motors 24A and 24B, which are mechanically coupled to rotate their respective associated axles 22A and 22B.

[0044] For further reference FIG. 2A to FIG. 2E In various embodiments, each electric motor 24A and 24B is mechanically coupled to its associated axle 22A and 22B via gear sets 28A and 28B, respectively. Each of the gear sets 28A and 28B is configured to provide speed and torque conversion from its associated electric motor 24A or 24B to its associated axle 22A or 22B, and ultimately to the associated wheel 16 or 18.

[0045] like FIG. 2D As shown, shaft 21A is configured to rotate via its associated rotor 27 of electric motor 24A, and shaft 21B is configured to rotate via its associated rotor 27 of electric motor 24B. Shafts 21A and 21B are supported and constrained within bearings (not shown) disposed on frame 19. Gear set 28A is disposed within frame 19 and configured to rotatably engage wheel shaft 22A, and gear set 28B is disposed within frame 19 and configured to rotatably engage wheel shaft 22B. Electric motor 24A is configured to rotatably engage gear set 28A, and electric motor 24B is configured to rotatably engage gear set 28B.

[0046] In various embodiments, each of gear sets 28A and 28B is configured to provide a speed and torque conversion from its associated electric motor 24A or 24B to its associated wheel axle 22A or 22B, and ultimately to the associated wheel 16 or 18. For example and given by way of illustration only and not by limitation, in various embodiments, gear 28C is configured to rotate by its associated axle 21A or 21B. Gear 28D is mounted on a shaft (not shown for clarity) and is configured to be meshingly engaged by gear 28C. Gear 28E is also mounted on a shaft (not shown for clarity). Gear 28F is mounted on wheel axle 22A or 22B and is configured to be meshingly engaged by gear 28E. It should be appreciated that in various embodiments, gear sets 28A and 28B can include any number of suitable gears (such as but not limited to planetary gears), with the gear ratios being selected according to the needs of the particular application to achieve the desired speed and torque conversion. It should be appreciated that gears for electric vehicles are well known in the art. As such, it is not necessary to further describe their construction and operation in order to understand the presently disclosed subject matter.

[0047] In some embodiments, wheel axles 22A and 22B can be fixedly coupled to their associated wheels 16 or 18. For example but not by way of limitation, in some such embodiments, front wheels 16 can be fixedly coupled to their associated wheel axles 22A and 22B. It should be appreciated that such fixed coupling can help reduce mechanical complexity and can help enable front wheels 16 to remain steerable, such as when towing vehicle 10 with front wheels 16 and rear wheels 18 engaged on a road surface (i.e., flat towing).

[0048] In some other embodiments, wheel axles 22A and 22B can be removably coupled to their associated wheels 16 or 18. For example but not by way of limitation, in some such embodiments, rear wheels 18 can be removably coupled to their associated wheel axles 22A and 22B. It should be appreciated that such removable coupling of rear wheels 18 can help avoid generating braking torque and / or uncontrolled power generation during towing.

[0049] It will be appreciated that each drive unit 20 drives either the left or right front wheels 16 or the left or right rear wheels 18. Thus, both electric motors 24A and 24B of a given drive unit 20 can experience the same or similar speed and torque demand ranges. To service such speed and torque demand ranges, in various embodiments, both electric motors 24A and 24B of a given drive unit 20 can have the same voltage and current ratings. For example, in various embodiments, such as in high voltage systems, the line-to-line voltage rating can be in the range of about 300 Vrms to about 600 Vrms, and the current rating can be in the range of about 300 Arms to about 900 Arms. By way of illustration given as a non-limiting example, an exemplary voltage rating can be 312 Vrms, and an exemplary current rating can be 550 Arms (based on a 400 VDC system). However, it will be appreciated that electric motors 24A and 24B can have any voltage rating and any current rating as required for a particular application.

[0050] In various embodiments, electric motors 24A and 24B can be any suitable type of electric motor as required. For example, in some embodiments, electric motors 24A and 24B can comprise synchronous electric motors. In some such embodiments, the synchronous electric motors can comprise, without limitation, permanent magnet electric motors, and the like. In some other embodiments, electric motors 24A and 24B can comprise, without limitation, asynchronous motors (or induction motors), similar to multi-phase AC induction motors, and the like.

[0051] As noted above, in various embodiments, each drive unit 20 drives either the left or right front wheels 16 or the left or right rear wheels 18, and thus, both electric motors 24A and 24B of a given drive unit 20 can experience the same or similar speed and torque demand ranges. Accordingly, in various embodiments, both inverters of a given drive unit 20 can have the same voltage output rating and the same current output rating. By way of illustration, but not limitation, in various embodiments, both inverters of a given drive unit 20 can have a voltage output rating of 312 Vrms and a current output rating of 550 Arms (based on a 400 VDC input). However, it will be appreciated that the inverters of a given drive unit 20 can have any voltage output rating and any current output rating as required for a particular application.

[0052] It will be appreciated that, in various embodiments, dual power inverter modules 26 can be physically associated with frame 19 in any suitable manner as required for a particular application. For example, but without limitation, in some embodiments, and as shown in FIG. 1, dual power inverter modules 26 can be modules within a sealed container and physically disposed on frame 19 outside of the frame. As another example, and as shown in FIG. 2, dual power inverter modules 26 can be modules within a sealed container and physically disposed on frame 19 inside of the frame. FIG. 2A to FIG. 2C As another example, and as shown in FIG. 3, dual power inverter modules 26 can be modules within a sealed container and physically disposed on frame 19 inside of the frame. As yet another example, and as shown in FIG. 4, dual power inverter modules 26 can be modules within a sealed container and physically disposed on frame 19 inside of the frame. FIG. 2EAs shown but not limited, in some other embodiments, the dual-power inverter module 26 can be installed integrally with the frame 19. In some such embodiments, the housing 29 has an open face (not shown) defined therein. An inverter circuit (described below) is disposed in the housing 29. In such embodiments, the open face of the housing 29 cooperates with an opening (not shown) in the frame 19. Such other embodiments are discussed in commonly owned U.S. Patent Application Serial No. 17 / 244,288, filed April 29, 2021, entitled “Inverter Module Installable Integrally with a Vehicle Drive Unit,” assigned to and filed by the Applicant, the entire contents of which are incorporated herein by reference.

[0053] Reference is additionally made to FIG. 3A and FIG. 3B In various embodiments, a dual-power inverter module (DPIM) 26 is provided. As described above, in various embodiments, the DPIM 26 includes two inverters 30A and 30B configured to generate three-phase high-voltage AC power from high-voltage DC power and provide the three-phase high-voltage AC power to an associated electric motor 24A or 24B; and a common controller 32 configured to control both inverters 30A and 30B.

[0054] In various embodiments, the DC link capacitor 34 can be electrically connected to a high-voltage DC power source, such as the battery 14. In some embodiments, the electrical connection to the battery 14 can include an electrical connection 36. A suitable electrical cable 38 can be electrically connected to the electrical connection 36 and can be electrically connected to the battery 14.

[0055] In various embodiments, the power inverter 30A can be electrically connected to the DC link capacitor 34 and configured to convert high-voltage DC power to three-phase high-voltage AC power. The power inverter 30A is further configured to supply the three-phase high-voltage AC power to an electric motor 24A, such as a right motor or a left motor. The power inverter 30B can be electrically connected to the DC link capacitor 34 and configured to convert high-voltage DC power to three-phase high-voltage AC power. The power inverter 30B is further configured to supply the three-phase high-voltage AC power to an electric motor 24B, such as the other of the left motor or the right motor.

[0056] In various embodiments, the common controller 32 can be electrically connected to the power inverter 30A and the power inverter 30B. The common controller 32 is configured to control the power inverter 30A and the power inverter 30B. The common controller 32 can be any suitable computer processor-based controller as desired. By way of example only and not by way of limitation, in various embodiments, the common controller 32 can include a computer processing unit (CPU), a general processor, a digital signal processor, a field programmable gate array, etc., and / or any combination thereof. While controllers are well known and further description of their construction and operation is not necessarily required for an understanding of the disclosed subject matter, further details regarding the common controller 32 will be set forth below with respect to additional functionality.

[0057] In various embodiments, the common controller 32 can be electrically connected to receive low voltage DC power, such as 12V DC. The common controller 32 can also be electrically connected to receive vehicle status signals and vehicle fault indication signals. Exemplary responses to various vehicle faults and 12V DC loss will be discussed further below.

[0058] In various embodiments, the power inverter 30A and the power inverter 30B each include a set 40 of three-terminal power semiconductor devices 42 and a set 44 of three-terminal power semiconductor devices 42.

[0059] In some embodiments, the three-terminal power semiconductor devices 42 can include insulated gate bipolar transistors (IGBTs). In some such embodiments, the IGBTs can include silicon (Si) IGBTs. In some embodiments, the three-terminal power semiconductor devices 42 can include metal oxide semiconductor field effect transistors (MOSFETs). In some such embodiments, the MOSFETs can include silicon carbide (SiC) MOSFETs. However, it should be appreciated that the three-terminal power semiconductor devices 42 can also include power semiconductor devices 42 that include at least three terminals, and can include additional terminals, such as, for example and without limitation, a Kelvin source terminal, a Kelvin emitter terminal, a current sense terminal, and / or a temperature sense terminal.

[0060] It should be appreciated that SiC MOSFETs can provide advantages over Si IGBTs at low phase currents, and have lower conduction drops compared to IGBTs below 700 Apk. However, it should be appreciated that this value can vary depending on the size of the inverter. Thus, it should be appreciated that SiC MOSFETs can provide up to about 3-5% efficiency gain in a typical drive cycle compared to Si IGBTs.

[0061] In some all-wheel drive (AWD) electric vehicles 10, the front wheels 16 serve as the only drive wheels until additional torque and / or power beyond a predetermined amount is required. In such electric vehicles 10, when torque and / or power beyond the predetermined amount is to be delivered, the rear wheels are driven only by their associated drive units 20. In some such AWD electric vehicles 10, to take advantage of the efficiency of SiC MOSFETs over Si IGBTs, the drive units 20 driving the front wheels 16 can include inverters 40 having SiC MOSFETs, and the drive units 20 driving the rear wheels 18 can include inverters 40 having Si IGBTs. However, it will be appreciated that any of the drive units 20 can include inverters 40 including either SiC MOSFETs or Si IGBTs as needed.

[0062] In various embodiments, the power inverter 30A includes a gate drive circuit 46A configured to drive the gate terminals 48 of the sets 40 and 44 of three-terminal power semiconductor devices 42 of the power inverter 30A. Similarly, the power inverter 30B includes a gate drive circuit 46B configured to drive the gate terminals 48 of the sets 40 and 44 of three-terminal power semiconductor devices 42 of the power inverter 30B. In various embodiments, the controller 32 is configured to generate, among other functions, low-power turn-on and turn-off signals 66A and 66B, and provide the turn-on and turn-off signals 66A and 66B to the gate drive circuits 46A and 46B, respectively. The low-power turn-on and turn-off signals 66A and 66B can be on the order of a few milliamps of current and logic-level voltages, such as 3.3V or 5V.

[0063] In various embodiments, the gate drive circuits 46A and 46B include suitable power amplifiers that amplify the low-power turn-on and turn-off signals 66A and 66B and generate high-power turn-on and turn-off signals 66A' and 66B'. To drive the gate terminals 48, the high-power turn-on and turn-off signals 66A' and 66B' can be on the order of hundreds of milliamps of current or on the order of amps, with voltages in the range of 15V to 20V, as needed for a particular application. The high-power turn-on and turn-off signals 66A' and 66B' are in turn electrically coupled to drive the associated gate terminals 48. Gate drive circuits are well known and further description of their construction and operation is not necessary for an understanding of the disclosed subject matter.

[0064] In view of the illustrative details provided above by way of non-limiting example, it will be appreciated that, in various embodiments, providing one controller 32 for both inverters 30A and 30B can provide the following uses: (i) a single interface for vehicle status signals and vehicle fault indication signals; (ii) a single DC link capacitor 34; (iii) a single common controller 32; and (iv) a single interface for low voltage DC power (such as 12V DC).

[0065] In view of the illustrative details provided above by way of non-limiting example, it will be appreciated that, in various embodiments, integrating the installation of the DPIM 26 with the drive unit 20 can provide integration of the coolant interface. For example, in various embodiments, water cooling provided for the inverters 30A and 30B can be provided to the stator windings of the electric motors 24A and 24B.

[0066] As noted above, in various embodiments, a single motor 24A or 24B drives a single wheel, such as one front wheel 16 or one rear wheel 18. It will be appreciated that each wheel can be operated at a unique speed and torque. By way of non-limiting example, cornering or loss of traction can produce different wheel speeds, while traction control or torque vectoring can result in different wheel torques. Also as noted above, in various embodiments, the dual power inverter module 26 combines the two inverters 30A and 30B into one module 26, and thus shares common components, such as the DC link capacitor 34.

[0067] To this end, various embodiments include only one DC link capacitor 34, which can be electrically connected to provide high voltage DC power to both inverters 30A and 30B of the DPIM 26. It will be appreciated that it can be desirable to reduce and possibly minimize the size of the DC link capacitor 34. As explained below, various embodiments can help to reduce the stress on the DC link capacitor 34 (which can have a reduced size) and the ripple current on the DC high voltage bus (which can include the cable 38) due to the high frequency current harmonics generated from the inverters 30A and 30B.

[0068] In various embodiments, the inverters 30A and 30B use pulse width modulation (PWM) to generate a variable amplitude and frequency voltage source to drive the electric motors 24A and 24B. Different PWM methods (such as, for example, continuous PWM and discontinuous PWM) can be employed as needed for a particular situation. Each of the PWM methods produces its own unique ripple current harmonic spectrum, which can be reflected on the DC bus.

[0069] For example, in continuous PWM, each phase is continuously switched (i.e., in various embodiments, all of the three-terminal power semiconductor devices 42 in both inverters 30A and 30B are continuously switched). Thus, continuous PWM can result in insignificant amounts of switching losses in inverters 30A and 30B. In continuous PWM, the second harmonic of the switching frequency is the dominant harmonic frequency in the ripple current. Continuous PWM, such as space vector modulation, can be used in situations such as when it is desirable to minimize harmonic content and ripple on the AC output and DC input currents, as well as to minimize acoustic noise. For example, some vehicles can use continuous PWM at high torque to minimize acoustic noise.

[0070] As another example, in discontinuous PWM, each phase is not continuously switched (i.e., in various embodiments, all of the three-terminal power semiconductor devices 42 in both inverters 30A and 30B are not continuously switched). In such embodiments, at any time only two of the three phases are switching, and the remaining third phase has the upper or lower switch continuously on, thereby helping to increase inverter efficiency and helping to reduce losses during discontinuous PWM. It should be appreciated that the use of discontinuous PWM can have other non-beneficial effects, such as an increase in acoustic noise or harmonic content in the AC output or DC input currents. In discontinuous PWM, each phase has two 60-degree sections in which the switches remain low or high and do not switch for a total of 120 degrees in the fundamental period. That is, in discontinuous PWM, each phase does not switch for one-third of the time. This results in significantly lower switching losses and higher efficiency. It should be appreciated that while discontinuous PWM requires lower switching losses than are required in continuous PWM, discontinuous PWM can require higher acoustic noise than is associated with continuous PWM, and harmonics can be placed on motors 24A and 24B and DC link capacitor 34. In discontinuous PWM, the first harmonic of the switching frequency is the dominant harmonic frequency. Discontinuous PWM can be used where the highest efficiency and lowest losses are desired, and acoustic noise is not a concern. For example, some vehicles can have thermal issues at high torque, and thus, discontinuous PWM is used to reduce losses under those conditions.

[0071] In various embodiments and with additional reference to FIG. 4A DC link capacitor 34 is used to decouple the effects of inductance L cable from the DC voltage source (i.e., battery 14) to inverters 30A and 30B. With additional reference to FIG. 4B and FIG. 4CThe DC link capacitor 34 provides a low-impedance path for the ripple current 50, which is generated by inverters 30A and 30B and may otherwise flow back to the DC high-voltage bus. The ripple current 50 is a factor in determining the size of the DC link capacitor 34, and therefore, reducing the ripple current 50 can help reduce the size of the DC link capacitor 34 (and the stress on it). The ripple current 50 is caused by the AC load current flowing into motors 24A and 24B and the pulse width modulation (PWM) of inverters 30A and 30B. FIG. 4B and FIG. 4C As shown and given for illustration only and not as a limitation, the motor current is 550 Arms, the modulation index is 0.48, the power factor is 1, the switching frequency is 10 kHz, and the fundamental frequency is 250 Hz. Without elimination, the ripple current 50 can have an amplitude of approximately 712 Arms.

[0072] For further reference FIG. 4D In various embodiments, a method 52 for synchronizing pulse width modulation (PWM) clocks is provided. It should be understood that, in various embodiments, synchronizing PWM clocks can help eliminate ripple current 50. Method 52 begins at block 53. At block 54, the PWM method of the first power inverter and the PWM method of the second power inverter are identified. At block 56, the switching frequency of the first power inverter and the switching frequency of the second power inverter are identified and compared. At block 58, an optimized phase shift between the first and second power inverters is determined in response to the PWM methods of the first and second power inverters and the switching frequencies of the first and second power inverters. At block 60, the optimized phase shift is synchronized between the first and second power inverters.

[0073] Method 52 ends at box 61.

[0074] like FIG. 4E and FIG. 4F As shown and given for illustration only and not as a limitation, the motor current is 550 Arms, the modulation index is 0.48, the power factor is 1, the switching frequency is 10 kHz, and the fundamental frequency is 250 Hz. With the elimination described herein, the ripple current 50 can be reduced to an amplitude of approximately 147 Arms.

[0075] In view of the above overview, in various implementation schemes, and as FIG. 3AAs shown, the common controller 32 includes a processor 64A and a processor 64B. In some embodiments, the processors 64A and 64B can be separate processors. However, it should be appreciated that in some other embodiments (using two PWM generators), the functions of the processors 64A and 64B can be combined into a single processor (e.g., using multitasking, multithreading, time slicing, etc.) as needed for a particular application. Whether the processors 64A and 64B are separate or combined into a single processor, it should be appreciated that the processor 64A functions as a master processor (or, in the case of a single processor, the functions of the processor 64A function as a master process), and the processor 64B functions as a slave processor (or, in the case of a single processor, the functions of the processor 64B function as a slave process).

[0076] The processor 64A is operatively coupled to a computer readable medium 65A, such as any suitable computer readable storage medium configured to store computer executable instructions configured to cause the processor 64A to perform the functions described below. The processor 64B is operatively coupled to a computer readable medium 65B, such as any suitable computer readable storage medium configured to store computer executable instructions configured to cause the processor 64B to perform the functions described below. The processor 64A is configured to generate a first clock signal (e.g., using a crystal) and a second clock signal for controlling the generation of on and off signals 66A for driving the power inverter 30A. The second clock signal is provided to the processor 64B to control the generation of on and off signals 66B for driving the power inverter 30B.

[0077] The processor 64A selects the PWM method for the power inverter 30A, and the processor 64B selects the PWM method for the power inverter 30B. The processor 64B (i.e., the slave processor) informs the processor 64A (i.e., the master processor) of its PWM method (except in the case of no PWM method switching). Factors for selecting continuous PWM and discontinuous PWM have been discussed above.

[0078] The processor 64A selects the switching frequency for the power inverter 30A, and the processor 64B selects the switching frequency for the power inverter 30B. The frequencies are even multiples of each other and are selected from predetermined values. Merely by way of illustration and not limitation, in various embodiments, the switching frequencies can be 2.5 kHz and 10 kHz, resulting in even multiples of four. However, it should be appreciated that other frequencies (resulting in even multiples) can be selected as desired. In various embodiments, the processor 64A (i.e., the master processor) outputs a reference at the lowest selectable frequency, with the desired phase shift as a function of the PWM mode.

[0079] The processor 64A is configured to determine an optimized phase shift between the power inverter 30A and the power inverter 30B in response to the PWM method of the power inverter 30A and the PWM method of the power inverter 30B and the switching frequency of the power inverter 30A and the switching frequency of the power inverter 30B. For example, in some such embodiments and with further reference to FIG. 4G , the processor 64A can access a lookup table 68 populated with cells containing optimized phase shift values arranged according to a row 70 of PWM methods and a column 72 of PWM methods. It will be appreciated that in some embodiments, the PWM method of the power inverter 30A and the PWM method of the power inverter 30B can be the same pulse width modulation method. It will also be appreciated that in some other embodiments, the PWM method of the power inverter 30A and the PWM method of the power inverter 30B can be different PWM methods.

[0080] As shown in FIG. 4G , when both power inverters 30A and 30B use continuous PWM, the phase shift is set to 90 degrees. When both power inverters 30A and 30B use discontinuous PWM, the phase shift is set to 180 degrees. In the case of different PWM methods, the phase is set to 90 degrees.

[0081] In some other such embodiments, the processor 64A can execute an algorithm for determining the optimized phase shift between the power inverter 30A and the power inverter 30B in response to the PWM method of the power inverter 30A and the PWM method of the power inverter 30B. For example, the algorithm can include if-then statements, such as:

[0082] if both PWM methods are continuous PWM, then the optimized phase shift is 90 degrees;

[0083] if both PWM methods are discontinuous PWM, then the optimized phase shift is 180 degrees; and

[0084] if one PWM method is continuous PWM and the other PWM method is discontinuous PWM, then the optimized phase shift is 90 degrees.

[0085] The processor 64A is further configured to synchronize the optimized phase shift between the power inverter 30A and the power inverter 30B. As noted above, the processor 64B is configured to receive the second clock signal and drive the power inverter 30B.

[0086] In various embodiments, the processor 64A is further configured to shift the second clock signal from the first clock signal by the determined optimized phase shift.

[0087] In various embodiments, the processor 64A is further configured to identify a dominant harmonic frequency between the PWM method of the power inverter 30A and the PWM method of the power inverter 30B and determine the optimal phase shift between the power inverter 30A and the power inverter 30B in response to the dominant harmonic frequency between the PWM method of the power inverter 30A and the PWM method of the power inverter 30B. It should be appreciated that determining the optimal phase shift between the power inverter 30A and the power inverter 30B in response to the dominant harmonic frequency between the PWM method of the power inverter 30A and the PWM method of the power inverter 30B can facilitate elimination of a dominant high frequency component of the ripple current 50.

[0088] In some such embodiments, the dominant harmonic frequency can include a second harmonic frequency (a harmonic of the switching frequency). For example, in such embodiments, the PWM method can include continuous PWM. In such embodiments, the optimal phase shift is 90 degrees. It should be appreciated that a phase shift of 90 degrees shifts the dominant harmonic (the second harmonic frequency) by 180 degrees, resulting in elimination of the dominant harmonic component of the ripple current 50.

[0089] In some other such embodiments, the dominant harmonic frequency can include a first harmonic frequency. For example, in such embodiments, the PWM method can include discontinuous PWM. In such embodiments, the optimal phase shift is 180 degrees. It should be appreciated that a phase shift of 180 degrees shifts the dominant harmonic (the first harmonic frequency) by 180 degrees, resulting in elimination of the dominant harmonic component of the ripple current 50.

[0090] It should be appreciated that the actual DC bus harmonics can reside in a sideband set around the switching frequency. The separation of these harmonics from the switching frequency harmonics is a function of the motor fundamental frequency.

[0091] In various embodiments, the processor 64A is configured to identify and compare the switching frequency of the power inverter 30A and the switching frequency of the power inverter 30B. As described above, only two frequencies that are even multiples of each other are used.

[0092] For example, in some embodiments, it can be desirable to change the switching frequency. For example, in some embodiments, the switching frequency can be 10 KHz. In such embodiments, at low motor speeds (e.g., below 500 RPM), it can be desirable to lower the switching frequency to 2.5 KHz to protect the switches 42 in the inverters 30A and 30B, thereby facilitating reduced stress in the inverters 30A and 30B. Maintaining an even relationship between the switching frequencies allows for harmonic alignment and improved opportunity to eliminate dominant harmonics.

[0093] Electric vehicles in which each wheel is independently driven by its own associated electric motor via its own axle without any mechanical coupling between the wheels. In such vehicles, if one inverter shuts down due to a fault and the other inverter does not react appropriately, there can be a torque difference between the two wheels. Such resulting torque differences can have a negative impact on the controllability of the vehicle.

[0094] To help avoid such torque differences and with additional reference to FIG. 5A to FIG. 5G In various embodiments, a fault associated with power inverter 30A or power inverter 30B (or the circuitry associated with both inverters 30A and 30B described below) results in the same fault action being applied to both inverters 30A and 30B (as described below). In such embodiments, applying the same fault action to both inverters 30A and 30B places inverters 30A and 30B in a "safe state" and helps to apply balanced torque to both wheels associated with drive unit 20 including inverters 30A and 30B. By applying the same fault action to both inverters 30A and 30B and balancing torque to both wheels of drive unit 20 including inverters 30A and 30B, various embodiments are able to help reduce the likelihood of torque difference generation that can have a negative impact on the controllability of the vehicle.

[0095] As described above, processor 64A is operably coupled to computer readable medium 65A, such as any suitable computer memory configured to store computer executable instructions configured to cause processor 64A to perform the functions described below. Also as described above, processor 64B is operably coupled to computer readable medium 65B, such as any suitable computer memory configured to store computer executable instructions configured to cause processor 64B to perform the functions described below. In various embodiments and as will be described below, the computer executable instructions are configured to cause their associated processors 64A and 64B, respectively, to apply the same fault action to power inverter 30A and power inverter 30B, respectively, to apply balanced torque to each wheel 16 or 18 operatively coupled to drive unit 20 in response to a fault associated with power inverter 30A or power inverter 30B.

[0096] In various embodiments and as FIG. 5A various faults associated with inverters 30A and 30B are monitored by processors 64A and 64B, respectively, for inverters 30A and 30B. For such faults, in various embodiments, processors 64A and 64B apply the same fault action to three-terminal power semiconductor devices 42 FIG. 3A) the same fault response is applied. In various embodiments, such faults associated with inverters 30A and 30B and monitored by processors 64A and 64B, respectively, can include, but are not limited to, overcurrent, overvoltage, undervoltage, overtemperature, overspeed, etc. In various embodiments, signals indicative of such faults can be provided to controller 32 via data link 74, which can include any suitable data communication connection or network as desired, such as but not limited to a wide area network (WAN), a local area network (LAN), a controller area network (CAN), a peer-to-peer network, a data bus, etc., and to processors 64A and 64B. In various embodiments, signals indicative of vehicle status, such as motor speed and voltage of battery 14, are also provided to controller 32 via data link 74.

[0097] In various embodiments and also as shown in FIG. 1, controller 32 includes a communication link 82 between processors 64A and 64B. It will be appreciated that communication link 82 can enable processor 64A or processor 64B to communicate to the other processor 64B or 64A, respectively, that a fault monitored by processor 64A or processor 64B has been detected, what fault action is to be taken, and what fault action is to be taken. Communication link 82 can include any suitable data link or data bus as desired. FIG. 5A

[0098] In various embodiments, fault actions for faults monitored by processors 64A and 64B with respect to inverters 30A and 30B, respectively, can include such as opening all of the three-terminal semiconductor devices 42 of inverters 30A and 30B and / or shorting the three-terminal semiconductor devices 42 of banks 40 or banks 44 of inverters 30A and 30B. As will be explained below, in various embodiments, the fault action imposed on both inverters 30A and 30B with respect to faults monitored by processors 64A and 64B depends on the speed of the motor. As will also be explained below, the fault action imposed on both inverters 30A and 30B with respect to faults not monitored by processors 64A and 64B does not depend on the speed of the motor.

[0099] ​In various embodiments and as noted above, the fault actions for the faults monitored by processors 64A and 64B for inverters 30A and 30B, respectively, in various embodiments can include such as opening all of the three-terminal semiconductor devices 42 of inverters 30A and 30B and / or shorting the three-terminal semiconductor devices 42 of banks 40 or banks 44 of inverters 30A and 30B and can depend on the speed of the motor. For such faults monitored by processors 64A and 64B, it will be appreciated that the fault actions applied to both inverters 30A and 30B simultaneously can help to reduce braking torque and reduce regenerative current to battery 14. Because processors 64A and 64B are operatively coupled to various data communication connections or networks to receive data regarding the speed of the motor, processors 64A and 64B are suitably configured to determine the same fault action to be applied based on the speed of the motor. In various embodiments, processor 64A selects the appropriate speed-dependent fault action for its associated electric motor 24A and processor 64B selects the appropriate speed-dependent fault action for its associated electric motor 24B. The fault actions for other faults not monitored by processors 64A and 64B do not depend on the speed of the motor and are discussed further below.

[0100] As FIG. 5B shown, in various embodiments, the same fault action to be applied to inverters 30A and 30B can be based on the speed of the motor. In such embodiments, the same fault action can include opening all of the three-terminal semiconductor devices 42 of inverters 30A and 30B at a threshold speed v th Below, all of the three-terminal semiconductor devices 42 of inverters 30A and 30B are opened, and at a threshold speed v th Above, the three-terminal semiconductor devices 42 of banks 40 or banks 44 of inverters 30A and 30B are shorted.

[0101] As FIG. 5B shown, graph 76 plots the speed of the motor against torque for various conditions of the three-terminal semiconductor devices 42 of inverters 30A and 30B. Curve 78 shows the torque resulting from opening all of the three-terminal semiconductor devices 42 of inverters 30A and 30B. Below a threshold speed v th Below, the torque is substantially insignificant, and at a threshold speed v th Above, as the speed of the motor increases, the braking torque becomes more and more significant. It will also be appreciated that in such cases, the back electromotive force (back EMF) increases with the increase in the speed of the motor, which in some cases can cause electric motors 24A and 24B to potentially operate as uncontrolled generators that can generate back EMF and apply unwanted regenerative current to DC link capacitor 34 and battery 14.

[0102] As FIG. 5BAs shown, curve 80 shows the torque resulting from a three-phase short of the three-phase semiconductor devices 42 of the set 40 or the set 44 of three-phase semiconductor devices 42. As the speed of the motor increases from zero, the braking torque rapidly increases and reaches a maximum value of braking torque. As the speed of the motor continues to increase, the braking torque decreases and approaches zero at a threshold speed v th the previous gradient-minimized value.

[0103] Accordingly, in various embodiments in which faults are monitored by the processors 64A and 64B for the inverters 30A and 30B, the fault actions suitably include speed-dependent fault actions that can help to simultaneously minimize the braking torque and unwanted regenerative current to the DC link capacitor 34 and the battery 14. In such embodiments, the fault actions suitably include opening all of the three-phase power semiconductor devices 42 in both of the inverters 30A and 30B when the speed of the motor is less than a threshold speed v th and shorting the three-phase power semiconductor devices 42 of one set of three-phase power semiconductor devices 42 (i.e., set 40 or set 44) of the inverters 30A and 30B when the speed of the motor is greater than the threshold speed v th

[0104] In various embodiments, the fault actions based on the curves 78 and 80 can be implemented using the back-EMF and voltage of the battery 14 (as opposed to taking fault actions directly in response to a reported motor speed). For example, in various embodiments, the motor back-EMF is calculated and compared to the voltage of the battery. In such embodiments, when the back-EMF is less than the battery voltage (by a design safety margin selected as needed), then the speed-dependent fault action includes opening all of the three-phase power semiconductor devices 42 in both of the inverters 30A and 30B. When the back-EMF exceeds a predetermined percentage of the battery voltage, then the speed-dependent fault action includes shorting the three-phase power semiconductor devices 42 of one set of three-phase power semiconductor devices 42 (i.e., set 40 or set 44) of the inverters 30A and 30B. If needed, using an amount of hysteresis can prevent “chattering” back and forth between different fault actions.

[0105] As FIG. 5A ​As shown, processor 64A is associated with power inverter 30A and processor 64B is associated with power inverter 30B. Memory 65A (i.e., computer readable medium) and memory 65B (likewise, computer readable medium) are each configured to store computer executable instructions configured to cause its associated processor 64A and 64B, respectively, to apply the same fault action to power inverter 30A and power inverter 30B, respectively, to apply an equalized torque to each wheel 16 or 18 operatively coupled to drive unit 20 in response to a fault associated with power inverter 30A or power inverter 30B.

[0106] Also as FIG. 5A shown, in various embodiments, signals indicative of parameters such as vehicle speed, faults such as those described above, etc. are supplied to controller 32 via data link 74 and provided to processors 64A and 64B. In such embodiments, the computer executable instructions are further configured to cause its associated processor 64A and 64B to monitor for faults.

[0107] Low voltage DC power, such as 12V, is provided to controller 32 to power components as needed. Controller 32 in turn provides 12V DC power to gate drive circuits 46A and 46B.

[0108] As FIG. 5A shown, processor 64A is operatively coupled to provide control signals 86 to driver 46A1 of gates 48 of set 40 (sometimes referred to as the "upper set") and to provide control signals 88 to driver 46A2 of gates 48 of set 44 (sometimes referred to as the "lower set"). Similarly, processor 64B is operatively coupled to provide control signals 90 to driver 46B1 of gates 48 of set 40 (sometimes referred to as the "upper set") and to provide control signals 92 to driver 46B2 of gates 48 of set 44 (sometimes referred to as the "lower set"). In various embodiments, drivers 46A1, 46A2, 46B1 and 46B2 are suitable power amplifiers that amplify low power control signals 86, 88, 90 and 92 and generate high power fault action signals 86', 88', 90' and 92' that are in turn provided to their associated gate terminals 48.

[0109] As FIG. 5CAs shown, in various embodiments, providing control signals 86, 88, 90, and 92 to their respective drivers 46A1, 46A2, 46B1, and 46B2 requires additional circuitry. Each processor 64A and 64B is operatively coupled to receive fault indication signals as described above, and processors 64A and 64B are operatively coupled to each other via communication link 82. Processor 64A is operatively coupled to provide control signals 86 and 88 to buffers 94 and 96, respectively, and processor 64B is operatively coupled to provide control signals 90 and 92 to buffers 98 and 100, respectively. Buffers 94, 96, 98, and 100 are any suitable buffers, such as, but not limited to, octal buffers, and the like.

[0110] Buffer 94 is operatively coupled to driver 46A1, buffer 96 is operatively coupled to driver 46A2, buffer 98 is operatively coupled to driver 46B1, and buffer 100 is operatively coupled to driver 46B2. When processor 64A or processor 64B receives a monitored fault indication signal for the associated inverter 30A or 30B, the processor receiving the monitored fault indication signal communicates the presence of the monitored fault via communication link 82. The fault action is as follows.

[0111] When processor 64A receives a fault indication signal, processor 64A communicates to processor 64B via communication link 82 that a fault monitored by processor 64A has been detected, what fault action will be taken by processor 64B, and what fault action processor 64B will take (as described below). Conversely, when processor 64B receives a fault indication signal, processor 64B communicates to processor 64A via communication link 82 that a fault monitored by processor 64B has been detected, what fault action will be taken by processor 64A, and what fault action processor 64A will take (as described below). It will also be appreciated that, in various embodiments, the processor receiving the fault indication signal also performs the fault action (which requires the other processor to also take).

[0112] When the speed of the motor is less than a threshold speed v thWhen a fault is detected (or the reverse EMF is less than the voltage of battery 14 by at least the design safety margin), processors 64A and 64B generate control signals 86, 88, 90, and 92, which are configured to disconnect all gate terminals 48 of inverters 30A and 30B, thus causing all three-terminal power semiconductor devices 42 of inverters 30A and 30B to open. Control signals 86, 88, 90, and 92 are provided to buffers 94, 96, 98, and 100, respectively, and subsequently to drivers 46A1, 46A2, 46B1, and 46B2, which provide fault action signals 86', 88', 90', and 92' to all gate terminals 48 of inverters 30A and 30B. FIG. 5D As shown, all three-terminal power semiconductor devices in groups 40 and 44 of inverters 30A and 30B are opened.

[0113] When the motor speed is greater than the threshold speed v th When a fault is detected (or the reverse EMF exceeds a predetermined percentage of the battery voltage), processors 64A and 64B generate control signals 86, 88, 90, and 92. These control signals are configured to disconnect the gate terminal 48 of the three-terminal power semiconductor device 42 in one of groups 40 or 44 of inverters 30A and 30B, and to connect the gate terminal 48 of the three-terminal power semiconductor device 42 in the other of groups 44 or 40 of inverters 30A and 30B. Therefore, the three-terminal power semiconductor device 42 in one of groups 40 or 44 of inverters 30A and 30B is open-circuited, and the three-terminal power semiconductor device 42 in the other of groups 44 or 40 of inverters 30A and 30B is short-circuited.

[0114] It should be understood that the three-terminal power semiconductor device 42 of either group 40 or 44 of inverters 30A and 30B can be open-circuited or short-circuited as needed. It should also be understood that a three-terminal power semiconductor device 42 that has already failed will not be open-circuited or short-circuited (because it has already failed). In some embodiments and as in... FIG. 5EAs shown, the three-terminal power semiconductor devices 42 of group 40 of both inverters 30A and 30B are open-circuited, and the three-terminal power semiconductor devices 42 of group 44 of both inverters 30A and 30B are short-circuited. In this embodiment, processors 64A and 64B generate control signals 86 and 90, which are configured to disconnect all gate terminals 48 of group 40 of inverters 30A and 30B, and thus open-circuit all three-terminal power semiconductor devices 42 in group 40 of inverters 30A and 30B. Processors 64A and 64B also generate control signals 88 and 92, which are configured to turn on all gate terminals 48 of group 44 of inverters 30A and 30B, and thus short-circuit all three-terminal power semiconductor devices 42 in group 44 of inverters 30A and 30B. Control signals 86, 88, 90 and 92 are provided to buffers 94, 96, 98 and 100 respectively, and then to drivers 46A1, 46A2, 46B1 and 46B2, which provide fault operation signals 86', 88', 90' and 92' to all gate terminals 48 of inverters 30A and 30B.

[0115] In some other implementations and such FIG. 5F As shown, the three-terminal power semiconductor devices 42 of group 44 of both inverters 30A and 30B are open-circuited, and the three-terminal power semiconductor devices 42 of group 40 of both inverters 30A and 30B are short-circuited. In this embodiment, processors 64A and 64B generate control signals 86 and 90, which are configured to disconnect all gate terminals 48 of group 44 of inverters 30A and 30B, and thus open-circuit all three-terminal power semiconductor devices 42 of group 44 of inverters 30A and 30B. Processors 64A and 64B also generate control signals 88 and 92, which are configured to turn on all gate terminals 48 of group 40 of inverters 30A and 30B, and thus short-circuit all three-terminal power semiconductor devices 42 of group 40 of group 40 of inverters 30A and 30B. Control signals 86, 88, 90 and 92 are provided to buffers 94, 96, 98 and 100 respectively, and then to drivers 46A1, 46A2, 46B1 and 46B2, which provide fault operation signals 86', 88', 90' and 92' to all gate terminals 48 of inverters 30A and 30B.

[0116] In various implementation schemes, and also as FIG. 5A and FIG. 5CAs shown, various faults associated with inverters 30A and 30B are not monitored by processors 64A and 64B of inverters 30A and 30B respectively, because such faults are faults in one or both of processors 64A and / or 64B or in the circuitry associated with processors 64A and 64B (described below). For such faults, in various embodiments, by enabling the three-terminal power semiconductor device 42 of one of groups 40 or 44 of inverters 30A and 30B (… FIG. 3A A short circuit affects the three-terminal power semiconductor devices 42 of both inverters 30A and 30B. FIG. 3A The same fault response is applied. Because the functionality of processors 64A and 64B is unverifiable under such fault conditions, it is unverifiable that processors 64A and 64B can receive and process information about the motor speed (or the reverse EMF or voltage of battery 14). Therefore, a default fault action is required in such cases. In various embodiments, the default action is a three-phase short circuit of the three-terminal power semiconductor device 42 in one of groups 44 or 40 of inverters 30A and 30B.

[0117] In various implementation schemes and such FIG. 5A and FIG. 5C As shown, controller 32 includes health monitoring circuitry 102 configured to monitor the health of processors 64A and 64B via data links 104 and 106, respectively. In some such embodiments, health monitoring circuitry 102 includes a field-programmable gate array (“FPGA”). In such embodiments, health monitoring circuitry 102 may be programmed to perform safety checks, such as manual safety checks, and to monitor whether processors 64A and / or 64B are operating normally (or fully operating normally). In some such embodiments, health monitoring circuitry 102 may be programmed to implement a rolling counter to perform such monitoring of processors 64A and 64B. In some such embodiments, processors 64A and 64B also monitor whether health monitoring circuitry 102 is operational. Therefore, a fault in health monitoring circuitry 102 is considered a fault in the circuitry associated with processors 64A and 64B.

[0118] In various implementation schemes and also as FIG. 5A and FIG. 5C As shown, controller 32 includes a three-phase short-circuit circuit 108. In such embodiments, the three-phase short-circuit circuit 108 is configured to generate a fault action signal (described below) for faults not monitored by processors 64A and 64B, since faults may include faults in processors 64A and / or 64B and / or health monitoring circuits 102. The fault action signal generated by the three-phase short-circuit circuit 108 passes through a three-terminal power semiconductor device 42 of one of groups 40 or 44 of inverters 30A and 30B.FIG. 3A ) shorting, triac power semiconductor devices 42 of both inverters 30A and 30B FIG. 3A ) applying the same fault response.

[0119] In various embodiments, the three-phase shorting circuit 108 is external to the processors 64A and 64B and is configured to apply the same fault action to the power inverter 30A and the power inverter 30B to apply an equalized torque to each wheel 16 or 18 operatively coupled to the drive unit 20 in response to a fault that is not monitored by the processor 64A or the processor 64B. As FIG. 5A and FIG. 5C shown, the three-phase shorting circuit 108 is coupled to receive the control signal 110 from the health monitoring circuit 102, the control signal 112 from the processor 64A, and the control signal 114 from the processor 64B. The health monitoring circuit 102 is configured to generate the control signal 110 in response to receiving a processor fault indication signal from the processor 64A via the data link 104 indicating a fault within the processor 64A or receiving a processor fault indication signal from the processor 64B via the data link 106 indicating a fault within the processor 64B. The processors 64A and 64B are configured to generate the control signals 112 and 114, respectively, in response to detecting a fault of the health monitoring circuit 102, such as but not limited to a failure of the rolling counter, via the data links 104 and 106, respectively.

[0120] In various embodiments and as shown in FIG. 5C the three-phase shorting circuit 108 includes a voltage regulator 116, a buffer 118, and a buffer 120. In some such embodiments, the voltage regulator 116 includes a voltage regulator configured to convert 12VDC to 5VDC. In such embodiments, the control signals 110, 112, and 114 are suitably 12VDC signals. In response to applying any of the 12VDC control signals 110, 112, or 114, the voltage regulator 116 outputs a 5VDC control signal 122. The control signal 122 is input to the buffers 118 and 120. The buffer 118 is coupled to provide the control signal 122 to the driver 46A2 of the bank 44 of the power inverter 30A. The driver 46A2 generates and provides the fault action signal 88' to the gate terminal 48 of the bank 44 of the power inverter 30A, thereby shorting the triac power semiconductor devices 42 of the bank 44 of the power inverter 30A. The buffer 120 is coupled to provide the control signal 122 to the driver 46B2 of the bank 44 of the power inverter 30B. The driver 46B2 generates and provides the fault action signal 92' to the gate terminal 48 of the bank 44 of the power inverter 30B, thereby shorting the triac power semiconductor devices 42 of the bank 44 of the power inverter 30B.

[0121] It should be appreciated that shorting the three-terminal power semiconductor devices 42 of the bank 44 of inverters 30A and 30B is given by way of illustration and not limitation. In some embodiments, the three-terminal power semiconductor devices 42 of the bank 40 of inverters 30A and 30B are shorted (and the three-terminal power semiconductor devices 42 of the bank 44 of inverters 30A and 30B remain open).

[0122] With additional reference to FIG. 5G In various embodiments, an example method 124 is provided for applying a same fault action to a first power inverter and a second power inverter to apply a balanced torque to each wheel operatively coupled to a drive unit in response to a fault associated with the first power inverter or the second power inverter.

[0123] The method 124 begins at block 126. At block 128, a fault associated with a first power inverter or a second power inverter of a drive unit of an electric vehicle is detected. At block 130, in response to detecting the fault, a same fault action is applied to the first power inverter and the second power inverter to apply a balanced torque to each wheel operatively coupled to the drive unit. The method 124 ends at block 130.

[0124] In various embodiments, a first processor for the first power inverter and a second processor for the second power inverter can monitor for the fault.

[0125] In various embodiments, a processor for an inverter having a fault associated therewith can communicate the fault action to a processor for an inverter not having a fault associated therewith.

[0126] In various embodiments, the fault action can include opening all bank three-terminal power semiconductor devices in the first power inverter and the second power inverter when a motor speed is less than a threshold speed, or shorting a bank of three-terminal power semiconductor devices in the first power inverter and the second power inverter when the motor speed is greater than the threshold speed.

[0127] In various embodiments, the fault associated with the first power inverter or the second power inverter of a drive unit of an electric vehicle can include a fault in a first processor for the first power inverter, or a second processor for the second power inverter, or a health monitoring circuit for the first processor and the second processor.

[0128] In various embodiments, applying the same fault action to the first power inverter and the second power inverter to apply balanced torque to each wheel operatively coupled to the drive unit can include applying the same fault action to the first power inverter and the second power inverter to apply balanced torque to each wheel operatively coupled to the drive unit by circuitry located external to the first processor and the second processor.

[0129] In various embodiments, the fault action can include shorting a set of three-terminal power semiconductor devices in the first power inverter and the second power inverter.

[0130] Notwithstanding, it will be appreciated that in some situations, the speed of one motor can differ from the speed of the other motor. For example, during a turn, the outer wheels can spin faster than the inner wheels. Similarly, the wheels can spin at different speeds in various wheel slip situations. In some such situations, because the processor 64A selects an appropriate speed-dependent fault action for its associated electric motor 24A and the processor 64B selects an appropriate speed-dependent fault action for its associated electric motor 24B, the speed-dependent fault action (e.g., based on the back-EMF and voltage of the battery 14) of one motor of the drive unit 20 can differ from the speed-dependent fault action of the other motor of the drive unit 20.

[0131] In addition to the faults associated with the inverters 30A and 30B described above, a loss of low voltage DC power to the controller 32, such as 12V DC and referred to herein as 12V, results in the application of the same fault action to both inverters 30A and 30B to help avoid torque imbalances between the two wheels 16 or 18 driven by the same drive unit 20.

[0132] It will be appreciated that, as FIG. 5A and FIG. 5C shown, the processors 64A and 64B, the drivers 46A1, 46A2, 46B1, and 46B2, the health monitoring circuit 102, and the three-phase short circuit circuit 108 all include components that are powered by the low voltage DC power (12V) supplied to the controller 32. It will be appreciated that a loss of 12V supplied to the controller 32 means that the processors 64A and 64B, the drivers 46A1, 46A2, 46B1, and 46B2, the health monitoring circuit 102, and the three-phase short circuit circuit 108 are not available to apply the same fault action to both inverters 30A and 30B, as described above.

[0133] Accordingly, in various embodiments and as described below, the capability to apply the same fault action to both inverters 30A and 30B in the event of a loss of 12V supplied to the controller 32 is provided.

[0134] AsFIG. 5A and FIG. 5C as shown and with further reference to FIG. 6A to FIG. 6B In various embodiments and by way of overview, the detection circuit 140 is configured to detect a loss of low voltage DC power (12V) supplied to the controller 32. The backup power circuit 84A is associated with the power inverter 30A and the backup power circuit 84B is associated with the power inverter 30B. Each backup power circuit 84A and 84B is configured to convert high voltage DC power (such as 450VDC) to low voltage DC power (such as, for example, a buck DC-DC converter) in response to detecting a loss of low voltage DC power supplied to the controller 32. The three-phase short circuit circuit 108 is configured to apply the same fault action to the power inverter 30A and the power inverter 30B to apply an equalized torque to each wheel 16 or 18 operatively coupled to the drive unit 20 in response to detecting a loss of low voltage DC power supplied to the controller 32.

[0135] As shown in FIG. 5A , FIG. 5C and FIG. 6A In various embodiments, the detection circuit 140 uses an optocoupler 141 to detect a loss of low voltage DC power (12V) supplied to the controller 32. The low voltage DC power (such as 12V) is supplied to a resistor Rl that is electrically connected in series to a resistor R2. The resistors Rl and R2 act as a voltage divider. A control signal 143 at a suitable voltage (such as, but not limited to, 5V) is supplied by a node 145 between the resistors Rl and R2 to a light emitting diode (LED) 145 of the optocoupler 141. When energized, the LED 145 converts an electrical input into light and emits light (visible light or infrared (IR) light). A phototransistor 147 detects the light emitted by the LED 145 and turns on. In various embodiments, the phototransistor 149 is a pull-down transistor. The phototransistor 149 is coupled to provide an enable signal 151 to the backup power circuits 84A and 84B.

[0136] During normal operation, the control signal 143 is supplied to the LED 147 and the LED 147 emits light. The phototransistor 149 detects the light and turns on. Because the phototransistor 149 is a pull-down transistor, when the phototransistor 149 turns on, the enable signal 151 is low. When the enable signal 151 is low, the enable signal 151 pulls down the backup power circuits 84A and 84B (such as buck DC-DC converters) so that the backup power circuits 84A and 84B are turned off and prevent the application of a three-phase short circuit.

[0137] In the event of a loss of low-voltage DC power (12V), signal 143 disappears and LED 147 stops emitting light. Consequently, phototransistor 149 disconnects and enable signal 151 goes high. When enable signal 151 is high, backup power circuits 84A and 84B are activated and a three-phase short circuit is applied, as described below. For example, enable signal 151 can activate the buck DC-DC converter in each of backup power circuits 84A and 84B to convert high-voltage DC power to low-voltage DC power (12V).

[0138] In various embodiments, gate drive circuits 46A and 46B respectively include backup power supply circuits 84A and 84B. High-voltage DC power (such as 450V) is supplied to each of the backup power supply circuits 84A and 84B. Each backup power supply circuit 84A and 84B is configured to convert the 450VDC power into low-voltage DC power, such as 12VDC power. Therefore, if desired, backup power supply circuits 84A and 84B appropriately include a buck DC-DC converter (as described above), a voltage divider circuit (as described below), etc.

[0139] like FIG. 6B As shown, in some embodiments, if desired, each backup power circuit 84A and 84B may optionally include a normally open relay 152 having a relay coil 154 operatively coupled to receive low-voltage DC power (12V) from the controller 32. In such embodiments, the normally open relay 152 also includes a normally open contact 156. As described above, during normal operation, low-voltage DC power 12V is supplied to the relay coil 154, and the relay coil 154 is energized, thereby opening the normally open contact 156. In the event of a loss of low-voltage DC power (12V), the relay coil 154 is de-energized, thereby closing the normally open contact 156. Therefore, in such embodiments, the detection circuit 140 appropriately includes the relay coil 154, and the low-voltage DC power (12V) from the controller 32 can be considered a control signal.

[0140] In such embodiments, each backup power supply circuit 84A and 84B suitably includes a voltage divider 158 operatively coupled to receive high voltage DC power. The voltage divider 158 is configured to convert the high voltage DC power to low voltage DC power, and is further configured to output the low voltage DC power to a normally open contact 156. In such embodiments, during normal operation (when low voltage DC power is provided to the relay coil 154 and the normally open contact 156 is open), the backup power supply circuits 84A and 84B do not provide 12V power. Instead, in the event of a loss of low voltage DC power (12V) (when the relay coil 154 is de-energized and the normally open contact 156 is closed), the backup power supply circuits 84A and 84B provide 12V power. Thus, in such embodiments, each backup power supply circuit 84A and 84B also suitably includes a normally open contact 156.

[0141] As noted above, in various embodiments, the power inverter 30A and the power inverter 30B each include two groups 40 and 44 of three-terminal power semiconductor devices 42. As described below, the three-phase short circuit circuit 108 is further configured to short circuit one group 40 or 44 of three-terminal power semiconductor devices 42 in the power inverter 30A and the power inverter 30B in response to detecting a loss of low voltage DC power supplied to the controller 32.

[0142] As FIG. 5A and FIG. 5C Regardless of how the loss of low voltage DC power (12V) is detected and how the low voltage DC power (12V) is generated by the backup power supply circuits 84A and 84B, the low voltage DC power (12V) is supplied from the backup power supply circuits 84A and 84B to the voltage regulator 116. In response to the application of low voltage DC power (12V), the voltage regulator 116 outputs a 5V DC control signal 122. The control signal 122 is input to buffers 118 and 120. The buffer 118 is coupled to provide the control signal 122 to the driver 46A2 of the group 44 of the power inverter 30A. The driver 46A2 generates and provides a fault action signal 88' to the gate terminal 48 of the group 44 of the power inverter 30A, thereby shorting the three-terminal power semiconductor devices 42 of the group 44 of the power inverter 30A. The buffer 120 is coupled to provide the control signal 122 to the driver 46B2 of the group 44 of the power inverter 30B. The driver 46B2 generates and provides a fault action signal 92' to the gate terminal 48 of the group 44 of the power inverter 30B, thereby shorting the three-terminal power semiconductor devices 42 of the group 44 of the power inverter 30B.

[0143] It should be appreciated that shorting the three-terminal power semiconductor devices 42 of the bank 44 of inverters 30A and 30B is given by way of illustration and not limitation. In some embodiments, the three-terminal power semiconductor devices 42 of the bank 40 of inverters 30A and 30B are shorted (and the three-terminal power semiconductor devices 42 of the bank 44 of inverters 30A and 30B remain open).

[0144] In various embodiments and as shown in FIG. 1, a method 160 for applying a same fault action to two inverters of a drive unit of an electric vehicle in the event of a loss of 12V supply to a common controller of the two inverters is provided. FIG. 6C

[0145] The method 160 begins at block 162. At block 164, a loss of low voltage direct current (DC) power supplied to a controller of a first processor of a first power inverter and a second processor of a second power inverter for a drive unit of an electric vehicle is detected. At block 166, high voltage DC power is converted to low voltage DC power in response to detecting the loss of low voltage DC power supplied to the controller. At block 168, a same fault action is applied to the first power inverter and the second power inverter to apply a balanced torque to each wheel operatively coupled to the drive unit in response to detecting the loss of low voltage DC power supplied to the controller. The method 160 stops at block 170.

[0146] In various embodiments, the control signal can be provided in response to a presence of low voltage DC power supplied to the controller.

[0147] In various embodiments, applying the same fault action to the first power inverter and the second power inverter to apply the balanced torque to each wheel operatively coupled to the drive unit in response to detecting the loss of low voltage DC power supplied to the controller can include applying the same fault action to the first power inverter and the second power inverter to apply the balanced torque to each wheel operatively coupled to the drive unit in response to an absence of the control signal.

[0148] In various embodiments, the fault action can include shorting a bank of three-terminal power semiconductor devices in one of the first power inverter and the second power inverter.

[0149] ​Those skilled in the art will recognize that at least a portion of the devices and / or processes described herein can be integrated into a data processing system. Those skilled in the art will recognize that a data processing system generally includes one or more of a system unit housing, a video display device, memory such as volatile or non-volatile memory, processors such as microprocessors or digital signal processors, computational entities such as operating systems, drivers, graphical user interfaces, and applications programs, one or more interaction devices (e.g., a touch pad, a touch screen, an antenna, etc.), and / or control systems including feedback loops and control motors (e.g., feedback for sensing position and / or velocity; control motors for moving and / or adjusting components and / or quantities). A data processing system can be implemented utilizing suitable commercially available components, such as those typically found in data computing / communication and / or network computing / communication systems.

[0150] As used in the foregoing / aftergoing disclosure, the term module can refer to a set of one or more components arranged in a particular way, or a set of one or more general components that can be configured to operate in a particular way at one or more particular points in time and / or that can also be configured to operate in one or more additional ways at one or more additional times. For example, the same hardware or the same portions of hardware can be configured / reconfigured in sequence / parallel time as a first type of module (e.g., at a first time), a second type of module (e.g., at a second time, which in some cases can coincide with, overlap, or follow the first time), and / or a third type of module (e.g., at a third time, which in some cases can coincide with, overlap, or follow the first and / or second times), etc. Reconfigurable and / or controllable components (e.g., general purpose processors, digital signal processors, field programmable gate arrays, etc.) can be configured as a first module with a first purpose, then as a second module with a second purpose, then as a third module with a third purpose, etc. The transition of reconfigurable and / or controllable components can occur in as little as a few nanoseconds, or can occur over a period of minutes, hours, or days.

[0151] In some such examples, when a component is configured to perform a secondary purpose, it may no longer be able to perform that primary purpose until it is reconfigured. Components can switch between configurations as different modules in as few nanoseconds. Components can be reconfigured dynamically; for example, a component reconfiguring from a first module to a second module may occur precisely when the second module is needed. Components can be reconfigured in stages; for example, portions of a first module that are no longer needed may be reconfigured into a second module, even before the first module has completed its operation. Such reconfiguration may occur automatically or through prompting from an external source, whether that source is another component, instruction, signal, condition, external stimulus, or similar.

[0152] For example, the central processing unit of a personal computer can operate at various times as a module for displaying graphics on a screen, for writing data to a storage medium, for receiving user input, and for multiplying by two large prime numbers, by configuring its logic gates according to its instructions. Such reconfiguration may be invisible to the naked eye and in some implementations may include activation, deactivation, and / or rerouting of various parts of the component (e.g., switches, logic gates, inputs, and / or outputs). Therefore, in examples present in the preceding / following disclosures, if an example includes or describes multiple modules, that example includes the possibility that the same hardware can implement more than one of the described modules simultaneously or in discrete time or timing. Whether more components, fewer components, or the same number of components as the number of modules are used, the implementation of multiple modules is merely an implementation choice and generally does not affect the operation of the modules themselves. Therefore, it should be understood that any description of multiple discrete modules in this disclosure includes implementing these modules as any number of underlying components, including but not limited to a single component that reconfigures itself over time to perform the functions of multiple modules and / or multiple components that are similarly reconfigured, and / or dedicated reconfigurable components.

[0153] In some cases, one or more components may be referred to herein as “configured to,” “configured by,” “configurable to,” “operable / operating as,” “suitable / adaptable to,” “capable of,” “adaptable to,” etc. Those skilled in the art will recognize that, unless the context otherwise requires, such terms (e.g., “configured to”) generally cover active state components and / or passive state components and / or standby state components.

[0154] While specific aspects of the subject matter described herein have been shown and described, it will be apparent to those skilled in the art that changes and modifications may be made based on the teachings herein without departing from the subject matter and its broader aspects, and therefore the appended claims cover all such changes and modifications within their scope, as is the true spirit and scope of the subject matter described herein. Those skilled in the art will understand that, in general, the terminology used herein, particularly in the appended claims (e.g., the body of the appended claims), is intended to denote “open-ended” terms (e.g., the term “comprising” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “at least having,” the term “including” should be interpreted as “comprising but not limited to,” etc.). Those skilled in the art will further understand that if a class intent is a specific number of introduced claim statements, such intent will be explicitly stated in the claims, and if no such statement is present, such intent does not exist. For example, to aid understanding, the following appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing a claim statement with the indefinite article "a" or "an" limits any particular claim containing such an introduced claim statement to a claim containing only one such statement, even when the same claim includes the introductory phrase "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and / or "an" should generally be interpreted as meaning "at least one" or "one or more"); the same applies to the use of definite articles used to introduce a claim statement. Furthermore, even when a specific number of introduced claim statements are explicitly stated, those skilled in the art will recognize that such a statement should generally be interpreted as meaning at least the number stated (e.g., simply stating "two statements" without further modification generally means at least two statements, or two or more statements). Furthermore, in cases where conventions such as "at least one of A, B, and C" are used, generally speaking, such a construction is intended to mean that a person skilled in the art will understand that the convention (e.g., "a system having at least one of A, B, and C" will include, but is not limited to, systems having only A, having only B, having only C, having A and B, having A and C, having B and C, and / or A, B, and C, etc.). A person skilled in the art will further understand that, unless the context otherwise requires, extractive terms and / or phrases that typically present two or more alternative terms (whether in the specification, claims, or drawings) should be understood to contemplate the possibility of including one, any, or both of the terms. For example, the phrase "A or B" will generally be understood to include the possibility of "A" or "B" or "A and B".

[0155] The detailed description set forth above describes various embodiments of the application through the use of block diagrams, flowcharts, and / or examples. While the foregoing detailed description has set forth various embodiments of the application via the use of block diagrams, flowcharts, and / or examples, it will be understood by those within the art that the application is not limited to the embodiments described herein; rather, the detailed description has been presented for purposes of illustration only and by further example, one skilled in the art will recognize that the application is equally applicable to any device, system, or method that has the functionality described herein. Moreover, the language used in this specification should not be taken as a restrictive means for the scope of the application, but as a description of the many embodiments of the application. Accordingly, the claims and their equivalents are intended to cover all such alternatives and modifications as are within the spirit and scope of the application. Numerous specific details are described in this specification to provide a thorough understanding of the application. However, in certain instances, well-known or conventional details are not described in order to not unnecessarily obscure the present application in detail. Also, well-known or conventional details that are functionally or structurally similar to other details described herein are not necessarily described in order to not unnecessarily obscure the present application in detail. Accordingly, the skilled artisan will understand that the application can be practiced with the elements and / or steps set forth herein with one or more modifications, as is apparent to one skilled in the art, and the elements and / or steps set forth herein are exemplary rather than mandatory. The application is not limited in scope by the format of the specification, including but not limited to its arrangement of example embodiments into sections such as Section or Section. In this regard, no aspect of the application is a requirement of all embodiments to exclude any features when the disclosure is broadened to further embodiments shrunk from the examples. It is intended that aspects of the application as described herein can be practiced without all of the acts or

[0156] Those skilled in the art will appreciate that the operations described above are typically performed in any sequence unless otherwise indicated herein. In addition, although various operational flows are presented herein in a sequence(s), it should be understood that the various operations can be performed in other orders than those which are illustrated, or can be performed concurrently, which can involve progress out of sequence that can cause variability in the name of the orders of execution. Unless otherwise specified herein, no sequence of operations is intended to reflect a strict logical order unless specified herein. In this regard, the terms "responsive" or "in response to," e.g., as used in the context of two operations, are generally not intended to mean causal, unless otherwise indicated herein. Rather, such terms indicate that the second operation is performed in response to or in reaction to the first operation.

[0157] While the disclosed subject matter has been described in terms of illustrative embodiments, it will be apparent to those skilled in the art that various modifications can be made without departing from the scope of the claimed subject matter as set forth in the requirements of the patent claims.

Claims

1. A controller, comprising: One or more processors, said one or more processors being associated with a first power inverter and a second power inverter for a drive unit of an electric vehicle; and One or more computer-readable media for use with the one or more processors, each computer-readable medium being configured to store computer-executable instructions configured to cause its associated processor to apply the same fault action to the first power inverter and the second power inverter in response to a fault associated with an inverter selected from the first power inverter and the second power inverter, wherein the same fault action includes applying equalized torque to each axle operatively coupled to the drive unit. The computer-executable instructions are further configured to cause their associated processor to monitor the fault, and The fault action also includes actions selected from those performed based on the motor speed: opening all multiple sets of three-terminal power semiconductor devices in the first power inverter and the second power inverter when the motor speed is less than a threshold speed, and short-circuiting one set of three-terminal power semiconductor devices in each of the first power inverter and the second power inverter when the motor speed is greater than the threshold speed.

2. The controller of claim 1, further comprising a communication link, wherein the one or more processors include a first processor associated with the first power inverter for the drive unit and a second processor associated with the second power inverter, and the communication link is between the first processor and the second processor.

3. The controller of claim 2 further includes a three-phase short-circuit circuit located outside the first processor and the second processor, and configured to apply the same fault action to the first power inverter and the second power inverter in response to a fault not monitored by the first processor and the second processor, wherein the same fault action includes applying equalized torque to each axle operatively coupled to the drive unit.

4. The controller according to claim 3 further includes a health monitoring circuit configured to monitor the health of the first processor and the second processor.

5. The controller according to claim 4, wherein: The fault includes faults selected from the processor chosen from the first processor and the second processor, and faults in the health monitoring circuitry; and The three-phase short-circuit circuit is further configured to short-circuit a set of three-terminal power semiconductor devices in the first power inverter and the second power inverter in response to a fault selected from a processor chosen from the first processor and the second processor, and a fault in the health monitoring circuit.

6. A dual-power inverter module, comprising: A DC link capacitor, which can be electrically connected to a high-voltage DC power source; A first power inverter is electrically connected to the DC link capacitor and configured to convert high-voltage DC power into three-phase high-voltage AC power, and the first power inverter is further configured to supply the three-phase high-voltage AC power to a first electric motor. A second power inverter is electrically connected to the DC link capacitor and configured to convert high-voltage DC power into three-phase high-voltage AC power, and the second power inverter is further configured to supply the three-phase high-voltage AC power to a second electric motor. and Controller, the controller includes: One or more processors, said one or more processors being associated with a first power inverter and a second power inverter for a drive unit of an electric vehicle; and One or more computer-readable media for use with the one or more processors, each computer-readable medium being configured to store computer-executable instructions configured to cause its associated processor to apply the same fault action to the first power inverter and the second power inverter in response to a fault associated with an inverter selected from the first power inverter and the second power inverter, wherein the same fault action includes applying equalized torque to each axle operatively coupled to the drive unit. The computer-executable instructions are further configured to cause their associated processor to monitor the fault, and The fault action also includes actions selected from those performed based on the motor speed: opening all multiple sets of three-terminal power semiconductor devices in the first power inverter and the second power inverter when the motor speed is less than a threshold speed, and short-circuiting one set of three-terminal power semiconductor devices in each of the first power inverter and the second power inverter when the motor speed is greater than the threshold speed.

7. The module of claim 6, further comprising a communication link, wherein the one or more processors include a first processor associated with the first power inverter for the drive unit and a second processor associated with the second power inverter, and the communication link is between the first processor and the second processor.

8. The module of claim 7 further includes a three-phase short-circuit circuit located outside the first processor and the second processor, and configured to apply the same fault action to the first power inverter and the second power inverter in response to a fault not monitored by the first processor and the second processor, wherein the same fault action includes applying equal torque to each axle operatively coupled to the drive unit.

9. The module according to claim 8 further includes a health monitoring circuit configured to monitor the health of the first processor and the second processor.

10. The module according to claim 9, wherein: The fault includes faults selected from the processor chosen from the first processor and the second processor, and faults in the health monitoring circuitry; and The three-phase short-circuit circuit is further configured to short-circuit a set of three-terminal power semiconductor devices in the first power inverter and the second power inverter in response to a fault selected from a processor chosen from the first processor and the second processor, and a fault in the health monitoring circuit.

11. An electric vehicle, comprising: Body; A high-voltage DC battery, wherein the high-voltage DC battery is disposed within the vehicle body; A first electric motor and a second electric motor, the first electric motor and the second electric motor being mechanically coupled to rotate at least one set of wheel axles; and At least one dual-power inverter module, the at least one dual-power inverter module comprising: A DC link capacitor, which is electrically connected to the high-voltage DC battery; A first power inverter is electrically connected to the DC link capacitor and configured to convert high-voltage DC power into three-phase high-voltage AC power. The first power inverter is further configured to supply the three-phase high-voltage AC power to an electric motor selected from the first electric motor and the second electric motor. A second power inverter, electrically connected to the DC link capacitor and configured to convert high-voltage DC power into three-phase high-voltage AC power, is further configured to supply the three-phase high-voltage AC power to another electric motor selected from the first and second electric motors; and A common controller, electrically connected to the first power inverter and the second power inverter, configured to control the first power inverter and the second power inverter, the common controller comprising: One or more processors associated with the first power inverter and the second power inverter; and One or more computer-readable media for use with the one or more processors, each computer-readable medium being configured to store computer-executable instructions configured to cause its associated processor to apply the same fault action to the first power inverter and the second power inverter in response to a fault associated with an inverter selected from the first power inverter and the second power inverter, wherein the same fault action includes applying equalized torque to each axle operatively coupled to the drive unit. The computer-executable instructions are further configured to cause their associated processor to monitor the fault, and The fault action also includes actions selected from those performed based on the motor speed: opening all multiple sets of three-terminal power semiconductor devices in the first power inverter and the second power inverter when the motor speed is less than a threshold speed, and short-circuiting one set of three-terminal power semiconductor devices in each of the first power inverter and the second power inverter when the motor speed is greater than the threshold speed.

12. The vehicle of claim 11, further comprising a communication link, wherein the one or more processors include a first processor associated with the first power inverter for the drive unit and a second processor associated with the second power inverter, and the communication link is between the first processor and the second processor.

13. The vehicle of claim 12, further comprising a three-phase short-circuit circuit located external to the first processor and the second processor, and configured to apply the same fault action to the first power inverter and the second power inverter in response to a fault not monitored by the first processor and the second processor, wherein the one or more processors include a first processor associated with the first power inverter for the drive unit and a second processor associated with the second power inverter.

14. The vehicle of claim 13, further comprising a health monitoring circuit configured to monitor the health of the first processor and the second processor, wherein: The fault includes faults selected from the processor chosen from the first processor and the second processor, and faults in the health monitoring circuitry; and The three-phase short-circuit circuit is further configured to short-circuit a set of three-terminal power semiconductor devices in the first power inverter and the second power inverter in response to a fault selected from a processor chosen from the first processor and the second processor, and a fault in the health monitoring circuit.

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