A multi-cylinder synchronous control system and method

Abstract

The present invention relates to a multi-cylinder synchronous control system and method, belonging to the field of servo control. First, time synchronization within 1 μs is achieved based on the PTP protocol, and then multi-cylinder synchronous control is realized based on highly synchronous displacement and pressure given signals and PID feedback control. The present invention can reliably achieve high-precision synchronous control of multiple hydraulic cylinders, avoid problems such as structural damage of the equipment due to uneven force distribution, or poor motion effect of mechanical equipment due to poor synchronization effect, so as to achieve high-precision synchronous control of multiple hydraulic cylinders and ensure the safety and reliability of the equipment. Based on the above cylinder synchronous control method, high-precision synchronous control of multiple hydraulic cylinders can be well achieved, avoiding problems such as equipment damage or poor motion effect caused by low synchronization accuracy.

Description

Technical Field

[0001] The present invention belongs to the field of servo control, and relates to a multi-cylinder synchronous control system and method. Background Art

[0002] In modern industrial mechanical equipment, hydraulic cylinders are increasingly used. They are basic motion components that convert hydraulic energy into mechanical energy and perform linear reciprocating motion (or swinging motion), and have the characteristics of simple structure, fast control response, smooth motion, and high precision. On the other hand, as the structure and motion mode of modern mechanical equipment become more and more complex, the situation where multiple hydraulic cylinders act on the same equipment simultaneously is also increasing. For example, continuous casting equipment for metallurgy, large forging hydraulic presses, ejection systems for shipborne aircraft, etc. all require the synchronous cooperation of multiple hydraulic cylinders.

[0003] To achieve the synchronous cooperation of multiple hydraulic cylinders, it is necessary to ensure that the working state parameters such as the actual displacement and pressure of these hydraulic cylinders strictly follow the given values, and must follow the given values simultaneously. Otherwise, it is easy for the mechanical equipment to have structural damage problems due to uneven force distribution, or the mechanical equipment may have poor motion effects due to poor synchronization. Therefore, a high-precision synchronous control method for multiple hydraulic cylinders is very important.

[0004] Patent for Invention: "A Method for Synchronous Control of Multiple Hydraulic Cylinders" (Patent Application No. 200910190950.4) discloses a method for synchronous control of multiple hydraulic cylinders. The control method includes the following steps: A. The controller determines whether the actual displacement value PV of a cylinder reaches the stroke value at a certain moment. If it reaches, the PID set value SP is made equal to the stroke value; if it does not reach, the PID set value SP is calculated based on the actual position value PV of the hydraulic cylinder; using the PID algorithm based on SP and PV to obtain an opening set value of a proportional valve, and the proportional valve moves the valve core according to this opening set value, causing the movement of the hydraulic cylinder; B. The actual position value PV of the hydraulic cylinder is fed back to the controller, and step A is entered; the synchronous control method in the present invention is not limited to the number of moving cylinders, there is no division of labor between the master and slave moving cylinders, the movement speed and accuracy of the cylinders can be adjusted through parameters, the movement speed of the cylinders is not fixed, and it reaches the target value at the fastest speed. The closer the displacement values of the frontmost cylinder and the rearmost cylinder are, the faster the overall movement speed is.

[0005] The invention patent: "Multi-cylinder Synchronous Control Method and System Based on PI Algorithm" (Patent Application No. 202210689961.2) discloses a multi-cylinder synchronous control method and system based on PI algorithm. First, obtain the basic fixed value of the analog signal used to control the movement of the hydraulic cylinder; and obtain the displacement difference between two adjacent hydraulic cylinders in the k-th sampling period and the cumulative value of the displacement differences within k sampling periods; then, based on the basic fixed value, proportional coefficient, and integral coefficient, obtain the analog signal value corresponding to each hydraulic cylinder in real time; finally, based on the analog signal value of each hydraulic cylinder, perform high-precision synchronous control of the multi-cylinder mechanism.

[0006] The above-mentioned invention patent proposes several different multi-cylinder synchronous control systems and methods, which are basically from the perspective of PID algorithm design. And the present invention designs a synchronous control method based on time synchronization, which is very different from the above methods. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a multi-cylinder synchronous control system and method. First, achieve time synchronization within 1 μs based on the PTP protocol, and then achieve multi-cylinder synchronous control based on highly synchronized displacement and pressure given signals and PID feedback control. The present invention can reliably achieve high-precision synchronous control of multiple hydraulic cylinders, avoid problems such as structural damage of the equipment due to uneven force distribution, or poor movement effects of mechanical equipment due to poor synchronization effect, so as to achieve high-precision synchronous control of multiple hydraulic cylinders and ensure the safety and reliability of the equipment.

[0008] To achieve the above purpose, the present invention provides the following technical solutions:

[0009] A multi-cylinder synchronous control system, which includes a control host computer, several hydraulic cylinders, several cylinder controllers, and a PTP switch;

[0010] The PTP switch is an Ethernet switch that supports the Precision Time Protocol IEEE 1588V2.

[0011] Among them, each hydraulic cylinder is controlled by a separate cylinder controller for movement.

[0012] Each hydraulic cylinder is also equipped with a displacement and pressure sensor, which is responsible for collecting the actual displacement and pressure signals of the hydraulic cylinder. The cylinder controller uses the actual displacement and pressure signals to achieve high-precision PID closed-loop feedback control.

[0013] The control host computer and multiple cylinder controllers are all connected to the PTP switch through network cables to achieve Ethernet interconnection communication.

[0014] Optionally, the cylinder controller uses an FPGA chip as the main control chip;

[0015] The FPGA chip is equipped with peripheral circuits: a temperature-controlled crystal oscillator module, a signal conditioning circuit for displacement and pressure sensors, an Ethernet network interface, and a physical layer PHY chip.

[0016] Among them, the temperature-controlled crystal oscillator module is used to generate a clock signal with a constant frequency. The FPGA chip performs frequency division and multiplication on this clock, and uses the high-quality clock after frequency division and multiplication as the working clock.

[0017] The FPGA chip consists of an oil cylinder PID algorithm control module and an Ethernet communication module.

[0018] The oil cylinder PID algorithm control module calculates displacement and pressure set signals; runs the PID algorithm and outputs control signals to the hydraulic cylinder; finally, makes the actual displacement and pressure signals collected by the displacement and pressure sensors and modulated by the signal conditioning circuit strictly follow the displacement and pressure set signals.

[0019] The Ethernet communication module is connected to the PHY chip, receives, sends, and processes Ethernet data, enabling the oil cylinder controller to have Ethernet communication capabilities.

[0020] Optionally, the Ethernet communication module of the FPGA chip consists of multiple sub-modules, including a MAC layer module, an IP layer module, a UDP / TCP layer module, and a PTP time synchronization module;

[0021] The PTP time synchronization module contains a counter module for generating PTP hardware timestamps.

[0022] Among them, the PTP time synchronization module and the PTP switch are responsible for receiving, sending, and processing PTP clock synchronization messages specified by the PTP protocol, achieving time synchronization within 1 μs between multiple oil cylinder controllers. Time synchronization is the basis for multi-cylinder synchronous control.

[0023] The PTP clock synchronization messages include Sync, Follow_up, Pdelay_req, Pdelay_resp, and Pdelay_resp_follow_up messages. Other PTP clock synchronization message types are not processed, reducing the complexity of FPGA programming and the consumption of logic resources. On the other hand, it reduces the number of PTP clock synchronization messages in the network and reduces the network load.

[0024] The UDP / TCP layer module is responsible for receiving, sending, and processing UDP / TCP data messages. The UDP / TCP data messages include: PTP master-slave status setting messages, PTP time synchronization status notification messages, oil cylinder synchronous control start / stop messages, and oil cylinder displacement and pressure information messages; the UDP / TCP data messages are used to control the normal operation of the multi-cylinder synchronous control system.

[0025] Optionally, the FPGA chip further includes a clock manager. An input clock and a frequency division / multiplication coefficient are provided to the clock manager. The clock manager performs fine frequency multiplication and division on the input clock according to the frequency division / multiplication coefficient, and outputs high-quality working clocks with multiple frequencies for different modules to use.

[0026] Among them, the working clock of the oil cylinder PID algorithm control module is 50 MHz, and the working clock of the Ethernet communication module is 125 MHz. In particular, the working frequency of the counter module is 250 MHz, that is, the resolution of the PTP hardware timestamp is 4 ns. Time synchronization means that the time difference corresponding to the difference in the count values of the counter modules of different oil cylinder controllers is controlled within 1 μs.

[0027] A multi-cylinder synchronization control method, which includes the following steps:

[0028] Step A1, designate one of the multiple oil cylinder controllers as the master clock, and the others as slave clocks.

[0029] The implementation method of the above step A1 is: control the host computer to send a PTP master-slave status setting message, and designate one of the multiple oil cylinder controllers as the master clock Master, and the others as slave clocks Slave. The UDP / TCP layer module identifies the message information and notifies the PTP time synchronization module to work in the master clock state or the slave clock state.

[0030] Step A2, based on the PTP protocol, all slave clocks perform time synchronization and frequency synchronization with the master clock.

[0031] The implementation method of the time synchronization in the above step A2 is:

[0032] A211. The PTP clock synchronization module of the master clock periodically notifies the MAC layer module to send Sync and Follow_up messages. After the PTP clock synchronization module of the slave clock receives the Sync and Follow_up messages, it calculates the clock deviation and the sum of the link delays between the master and slave clocks.

[0033] A212. Measure the link delay based on the P2P delay measurement method. To reduce network load and improve real-time performance, it is stipulated that:

[0034] i) The P2P delay measurement between the master clock and the PTP switch is only initiated by the PTP switch;

[0035] ii) The P2P delay measurement between the slave clock and the PTP switch is only initiated by the slave clock;

[0036] iii) Periodically initiate P2P delay measurement.

[0037] A213. Based on the PTP protocol, the PTP clock synchronization module of the slave clock periodically calculates the link delay between the master and slave clocks.

[0038] A214. According to A211 and A213, the PTP clock synchronization module of the slave clock calculates the clock deviation and adjusts the count value of the internal counter module, that is, adjusts the PTP hardware timestamp, to complete clock synchronization. Each time the PTP clock synchronization module of the slave clock receives a Follow_up message, it completes one clock synchronization.

[0039] The implementation method of frequency synchronization in step A2 is as follows:

[0040] A221. In A214, when it is judged that the clock deviation is greater than the specified value for several consecutive times, the PTP clock synchronization module of the slave clock starts frequency synchronization and proceeds to step A222.

[0041] A222. When the PTP clock synchronization module of the slave clock receives a Follow_up message sent by the master clock, it immediately records the PTP hardware timestamp T of the master clock carried in the Follow_up message master_ , and its own PTP hardware timestamp T slave_1 , and at the same time records the adjustment value T of its own PTP hardware timestamp in this clock synchronization offset . When receiving the next Follow_up message, it immediately records the PTP hardware timestamp T of the master clock carried in the Follow_up message master_ , and its own PTP hardware timestamp T slave_2 . Then the ratio of the sum of the operating frequencies f slave of the slave clock counter module to the operating frequency f master of the master clock counter module is:

[0042]

[0043] A223. The PTP clock synchronization module of the slave clock calculates the frequency division and multiplication factor according to the ratio of the operating frequencies and sends it to the clock manager. The clock manager adjusts the operating frequency of the counter module accordingly to complete one frequency synchronization, and at the same time proceeds to step A221 to determine again whether frequency synchronization is required.

[0044] Step A3, determine whether all slave clocks have completed time synchronization and frequency synchronization with the master clock. If so, proceed to step A4; if not, proceed to step A5.

[0045] Step A4, the system enables cylinder synchronization control.

[0046] Step A5, the system stops cylinder synchronization control.

[0047] The implementation methods of steps A3, A4, and A5 are as follows: When the slave clock completes or breaks away from the clock synchronization and frequency synchronization with the master clock, it notifies the UDP / TCP module to send a PTP time synchronization status notification message. After receiving the message, if the control host computer determines that all slave clocks have completed the clock synchronization and frequency synchronization with the master clock, it issues a hydraulic cylinder synchronization control start message to start the synchronization control. After determining that a certain slave clock has broken away from the clock synchronization and frequency synchronization with the master clock, it immediately issues a hydraulic cylinder synchronization control stop message to stop the synchronization control.

[0048] After receiving the above-mentioned hydraulic cylinder synchronization control start / stop message, the UDP / TCP module notifies the hydraulic cylinder PID algorithm control module to start / stop the synchronization control.

[0049] The hydraulic cylinder synchronization control start message also contains a synchronization control mode indication and a motion mode indication, and the hydraulic cylinder PID algorithm control module adopts different synchronization control algorithms according to the message indication.

[0050] Optionally, in step A2, the sliding average filtering algorithm is used to filter the link delay between the master and slave clocks for time synchronization, and the filtered link delay is used for time synchronization. The formula for the sliding average filtering algorithm is:

[0051]

[0052] In the formula, θ n is the link delay between the master and slave clocks calculated for the nth time; β is the weight; T n-1 is the link delay between the master and slave clocks obtained after the (n - 1)th sliding average filtering; T n is the link delay between the master and slave clocks obtained after the nth sliding average filtering.

[0053] Optionally, in step A2, the ratio of the working frequencies in frequency synchronization is calculated continuously for multiple times, and the sliding average filtering algorithm is used to filter the ratio of the working frequencies, and the finally filtered ratio of the working frequencies is used for frequency synchronization.

[0054] Optionally, in step A4, when the synchronization control mode indication is the absolute synchronization mode, the synchronization control method is as follows:

[0055] B1. The hydraulic cylinder PID algorithm control modules of the master and slave clocks both calculate the displacement and pressure given signals according to the motion mode indication at the specified time starting point. The displacement and pressure given signals are time-varying signals, and the PTP hardware timestamp is used as the time variable. The motion modes include, for example, sinusoidal motion, linear motion, and single-step motion;

[0056] B2. The hydraulic cylinder PID algorithm control module 11 of the master and slave clocks uses PID closed-loop control to make the actual displacement and pressure signals of the hydraulic cylinder strictly follow the displacement and pressure given signals.

[0057] Optionally, in step A4, when the synchronization control mode indicates the tracking synchronization mode, the synchronization control method is as follows:

[0058] C1. The oil cylinder PID algorithm control module of the master clock calculates the oil cylinder displacement and pressure given signals according to the motion mode indication at the specified time starting point. The displacement and pressure given signals are time-varying signals, and the PTP hardware timestamp of the master clock is used as the time variable. The motion modes include, for example, sinusoidal motion, linear motion, and single-step motion.

[0059] C2. The oil cylinder PID algorithm control module of the master clock periodically notifies the UDP / TCP module to send the oil cylinder displacement and pressure information message, which includes the oil cylinder displacement and pressure given signals of the master clock at the sending moment and the PTP hardware timestamp of the master clock.

[0060] C3. After receiving the oil cylinder displacement and pressure information message, the UDP / TCP module of the slave clock sends the message information to the oil cylinder PID algorithm control module. The oil cylinder PID algorithm control module calculates the oil cylinder displacement and pressure given signals of the slave clock at the receiving moment according to the difference between the PTP hardware timestamp of the slave clock at the receiving moment and the PTP hardware timestamp of the master clock, and the oil cylinder displacement and pressure given signals of the master clock. At the same time, the complete oil cylinder displacement and pressure given signals of the slave clock are calculated by means of interpolation and fitting.

[0061] C4. The oil cylinder PID algorithm control modules of the master and slave clocks perform PID closed-loop control to make the actual displacement and pressure signals of the hydraulic cylinder strictly follow the displacement and pressure given signals.

[0062] Optionally, in step A5, the method for stopping synchronization control is as follows:

[0063] D1. The oil cylinder PID algorithm control modules of the master and slave clocks calculate the motion stop displacement and pressure given signals at the specified time starting point. The motion stop displacement and pressure given signals are signals that reach the specified and fixed displacement and pressure values within the specified time.

[0064] D2. The oil cylinder PID algorithm control modules of the master and slave clocks perform PID closed-loop control to make the actual displacement and pressure signals of the hydraulic cylinder strictly follow the motion stop displacement and pressure given signals.

[0065] The beneficial effects of the present invention are as follows: The present invention mainly realizes time synchronization based on the PTP clock synchronization protocol. On this basis, highly synchronized cylinder displacement and pressure given signals are calculated, and then the synchronous control of the cylinders is realized through PID control. By constructing a PID algorithm control module and an Ethernet communication module in the FPGA, and cooperating with the control host computer and the PTP switch, the synchronous control of the cylinders is specifically realized. Based on the above cylinder synchronous control method, the high-precision synchronous control of multiple hydraulic cylinders can be well realized, avoiding problems such as equipment damage or poor motion effect caused by low synchronous accuracy.

[0066] Other advantages, objectives, and features of the present invention will be described to some extent in the subsequent specification, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following specification. Brief Description of the Drawings

[0067] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail preferably in conjunction with the drawings, where:

[0068] Figure 1 It is the structure diagram of the multi-cylinder synchronous control system according to the embodiment of the present invention;

[0069] Figure 2 It is the structure diagram of the function modules of the cylinder controller according to the embodiment of the present invention;

[0070] Figure 3 It is the structure diagram of the function modules of the FPGA chip in the cylinder controller according to the embodiment of the present invention;

[0071] Figure 4 It is the flow chart of the multi-cylinder synchronous control method according to the embodiment of the present invention;

[0072] Reference numerals: 1 - industrial tablet computer, 2 - hydraulic cylinder, 3 - cylinder controller, 4 - PTP switch, 5 - displacement and pressure sensor, 6 - FPGA chip, 7 - oven-controlled crystal oscillator module, 8 - signal conditioning circuit of displacement and pressure sensor, 9 - Ethernet network interface, 10 - PHY chip, 11 - cylinder PID algorithm control module, 12 - Ethernet communication module, 13 - MAC layer module, 14 - IP layer module, 15, UDP / TCP layer module, 16 - PTP time synchronization module, 17 - counter module, 18 - clock manager. Detailed Embodiments

[0073] The following describes the implementation modes of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0074] Among them, the attached drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and should not be construed as a limitation to the present invention; in order to better illustrate the embodiments of the present invention, some components in the attached drawings will be omitted, enlarged or reduced, which does not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the attached drawings may be omitted.

[0075] In the attached drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or position relationship, it is based on the orientation or position relationship shown in the attached drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the position relationship in the attached drawings are only for illustrative purposes and should not be construed as a limitation to the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0076] As Figure 1 shown, a multi-cylinder synchronous control system and method proposed by the present invention has the following system composition: a control host computer 1, multiple hydraulic cylinders 2, multiple cylinder controllers 3, a PTP switch 4, and multiple displacement and pressure sensors 5.

[0077] Among them, the PTP switch 4 is an Ethernet switch that supports the Precision Time Protocol IEEE 1588V2 (also known as PTP).

[0078] Each hydraulic cylinder 2 is controlled in motion by a separate cylinder controller 3.

[0079] Each hydraulic cylinder 2 is also equipped with a displacement and pressure sensor 5, which is responsible for collecting the actual displacement and pressure signals of the hydraulic cylinder. The cylinder controller 3 uses the actual displacement and pressure signals to achieve high-precision PID closed-loop feedback control.

[0080] The control host computer 1 and multiple cylinder controllers 3 are both connected to the PTP switch 4 through network cables to achieve Ethernet interconnection communication.

[0081] As Figure 2 shown, the oil cylinder controller 3 uses the FPGA chip 6 as the main control chip. The FPGA chip 6 is also equipped with peripheral circuits: a constant temperature crystal oscillator module 7, a signal conditioning circuit 8 for the displacement and pressure sensors 5, an Ethernet network interface 9, and a physical layer PHY chip 10.

[0082] Among them, the constant temperature crystal oscillator module 7 is used to generate a clock signal with a constant frequency. The FPGA chip 6 divides and multiplies the frequency of this clock, and uses the high-quality clock after frequency division and multiplication as the working clock.

[0083] The FPGA chip 6 is mainly composed of an oil cylinder PID algorithm control module 11 and an Ethernet communication module 12.

[0084] The oil cylinder PID algorithm control module 11 calculates the displacement and pressure given signals; runs the PID algorithm and outputs a control signal to the hydraulic cylinder 2; finally makes the displacement and pressure actual signals collected by the displacement and pressure sensors 5 and modulated by the signal conditioning circuit 8 strictly follow the displacement and pressure given signals.

[0085] The Ethernet communication module 12 is connected to the PHY chip 10, transceiver and processes Ethernet data, enabling the oil cylinder controller 3 to have Ethernet communication functions.

[0086] As Figure 3 shown, the Ethernet communication module 12 in the FPGA chip 6 is composed of multiple sub-modules, including a MAC layer module 13, an IP layer module 14, a UDP / TCP layer module 15, and a PTP time synchronization module 16. In particular, the PTP time synchronization module 16 includes a counter module 17 for generating PTP hardware timestamps.

[0087] Among them, the PTP time synchronization module 16 and the PTP switch 4 are responsible for transceiver and processing of PTP clock synchronization messages specified by the PTP protocol, realizing time synchronization within 1 μs between multiple oil cylinder controllers. Time synchronization is the basis for multi-cylinder synchronous control.

[0088] The above PTP clock synchronization messages are only the necessary Sync, Follow_up, Pdelay_req, Pdelay_resp, Pdelay_resp_follow_up messages. Other PTP clock synchronization message types are not processed, thereby reducing the complexity of FPGA programming and the consumption of logic resources. On the other hand, it reduces the number of PTP clock synchronization messages in the network, thereby reducing the network load and improving the network real-time performance.

[0089] Since the PTP clock synchronization message is encapsulated in the MAC layer data packet, the PTP time synchronization module is at the same level as the IP layer module. The MAC layer module delivers the packet to the PTP time synchronization module or the IP layer module according to the MAC layer data type.

[0090] The UDP / TCP layer module is responsible for receiving, sending, and processing UDP / TCP data packets. There are various types of UDP / TCP data packets: PTP master-slave status setting packets, PTP time synchronization status notification packets, oil cylinder synchronization control start / stop packets, oil cylinder displacement and pressure information packets, and so on. These UDP / TCP packets are used to control the normal operation of the multi-cylinder synchronization control system.

[0091] As Figure 3 shown, the FPGA chip 6 also includes a clock manager 18, which provides an input clock and a frequency division / multiplication coefficient for the clock manager 18. The clock manager 18 performs fine frequency multiplication and division on the input clock according to the frequency division / multiplication coefficient, and outputs high-quality working clocks of various frequencies for different modules to use.

[0092] Among them, the working clock of the oil cylinder PID algorithm control module 11 is 50 MHz, and the working clock of the Ethernet communication module 12 is 125 MHz. In particular, the working frequency of the counter module 17 is 250 MHz. Therefore, the resolution of the PTP hardware timestamp in the present invention is 4 ns, which provides a guarantee for controlling the time synchronization accuracy within 1 μs. The so-called time synchronization is to control the time difference corresponding to the difference in the count values of the counter modules of different oil cylinder controllers within 1 μs.

[0093] The above 250 MHz is a relatively high frequency at which the current mainstream FPGA chip 6 can stably operate. With the improvement of the manufacturing process of the FPGA chip 6, this frequency should be further increased, thereby improving the resolution of the PTP hardware timestamp and the time synchronization accuracy.

[0094] Figure 4 is the logic flow chart of the multi-cylinder synchronization control method, and the steps are as follows:

[0095] Step A1, designate one of the multiple oil cylinder controllers as the master clock, and the others as slave clocks.

[0096] The implementation method of the above step A1 is: control the host computer 1 to send a PTP master-slave status setting packet, designating one of the multiple oil cylinder controllers 3 as the master clock (Master), and the others as slave clocks (Slave). The UDP / TCP layer module 15 identifies the packet information and then notifies the PTP time synchronization module 16 to work in the master clock state or the slave clock state.

[0097] Step A2, based on the PTP protocol, all slave clocks perform time synchronization and frequency synchronization with the master clock.

[0098] The implementation method of time synchronization in the above step A2 is as follows:

[0099] A211. The PTP clock synchronization module 16 of the master clock periodically notifies the MAC layer module to send Sync and Follow_up messages. This period is generally 2s. After receiving the Sync and Follow_up messages, the PTP clock synchronization module 16 of the slave clock calculates the sum of the clock deviation and link delay between the master and slave clocks.

[0100] A212. Link delay refers to the time consumed by the time synchronization message from one network port terminal through the network cable to the opposite network port. In the present invention, the calculation is performed according to the P2P delay measurement method (one end sends a Pdelay_Req message, that is, initiates P2P delay measurement, and the other end feeds back Pdelay_Resp and Pdelay_Resp_Follow_up messages after receiving them. The P2P delay measurement initiator can calculate the link delay after receiving the feedback). Generally, both ends need to initiate P2P delay measurement. However, in order to reduce network load and improve real-time performance, the present invention stipulates that: i) The P2P delay measurement between the master clock and the PTP switch 4 is only initiated by the PTP switch 4; ii) The P2P delay measurement between the slave clock and the PTP switch 4 is only initiated by the slave clock; iii) P2P delay measurement is periodically initiated, and this period is generally 1s.

[0101] A213. After receiving the Follow_up message, the PTP switch 4 adds the sum of the link delay between the master clock and the switch and the residence time of the message in the PTP switch to the correction field of the Follow_up message. After receiving the Follow_up message forwarded by the PTP switch 4, the PTP clock synchronization module 16 of the slave clock can obtain the link delay between the master and slave clocks by combining the link delay between the slave clock and the PTP switch 4 and the delay in the Follow_up correction field. The above link delay between the master and slave clocks is calculated periodically, and this period is basically the same as the P2P delay measurement period, generally 1s.

[0102] A214. According to A211 and A213, the PTP clock synchronization module 16 of the slave clock calculates the clock deviation, and then adjusts the count value of the internal counter module 17, that is, adjusts the PTP hardware timestamp, to complete clock synchronization. Every time the PTP clock synchronization module 16 of the slave clock receives a Follow_up message, it calculates the clock deviation once and performs clock synchronization once.

[0103] The implementation method of frequency synchronization in the above step A2 is as follows:

[0104] A221. In A214, when it is determined that the clock deviation is greater than the specified value for several consecutive times, for example, greater than 1 μs for 3 consecutive times, it indicates that there is a large difference in the working frequencies of the counter modules 17 of the master and slave times. Because when there is a difference in the working frequencies, as the working time increases, the difference in the count values of the counter module 17 will continuously accumulate, resulting in the clock deviation still being greater than the specified value before the next clock synchronization despite periodic clock synchronization. Then, the PTP clock synchronization module 16 of the slave clock starts frequency synchronization.

[0105] A222. When the PTP clock synchronization module of the slave clock receives the Follow_up message sent by the master clock, it immediately records the PTP hardware timestamp T of the master clock carried in the Follow_up message master_ , and its own PTP hardware timestamp T slave_1 , and at the same time records the adjustment value T of its own PTP hardware timestamp in this clock synchronization offset . When receiving the next Follow_up message, it immediately records the PTP hardware timestamp T of the master clock carried in the Follow_up message master_ , and its own PTP hardware timestamp T slave_2 . Then, the ratio of the working frequency f slave of the slave clock counter module to the working frequency f master of the master clock counter module is:

[0106]

[0107] A223. The PTP clock synchronization module 16 of the slave clock calculates the frequency division and multiplication factor according to the ratio of the working frequencies and sends it to the clock manager 18. The clock manager 18 adjusts the working frequency of the counter module 17 accordingly to complete a frequency synchronization, and at the same time goes to step A221 to determine again whether frequency synchronization is required.

[0108] Step A3, determine whether all slave clocks have completed time synchronization and frequency synchronization with the master clock. If so, go to step A4; if not, go to step A5.

[0109] Step A4, the system enables the oil cylinder synchronization control.

[0110] Step A5, the system stops the oil cylinder synchronization control.

[0111] The implementation methods of the above steps A3, A4, and A5 are as follows: When the slave clock completes or breaks away from the clock synchronization and frequency synchronization with the master clock, it will notify the UDP / TCP module 15 to send a PTP time synchronization status notification message. After receiving it, if the control host computer 1 determines that all slave clocks have completed the clock synchronization and frequency synchronization with the master clock, it will send an oil cylinder synchronization control start message to start the synchronization control. After determining that a certain slave clock has broken away from the clock synchronization and frequency synchronization with the master clock, it will immediately send an oil cylinder synchronization control stop message to stop the synchronization control.

[0112] After receiving the above oil cylinder synchronization control start / stop message, the UDP / TCP module 15 notifies the oil cylinder PID algorithm control module 11 to start / stop the synchronization control.

[0113] The oil cylinder synchronization control start message also contains a synchronization control mode indication and a motion mode indication, and the oil cylinder PID algorithm control module 11 adopts different synchronization control algorithms according to the message indication.

[0114] In the time synchronization of the above step A2, the link delay affects the calculation of the clock deviation and is the main factor affecting the time synchronization accuracy. This delay fluctuates continuously with time, temperature, etc. To reduce the influence of the link delay fluctuation on the time synchronization accuracy, a moving average filtering algorithm is used to filter the link delay, and the filtered link delay is used to calculate the time deviation and perform time synchronization. The formula of the moving average filtering algorithm is:

[0115]

[0116] In the above formula, θ n is the link delay between the master and slave clocks calculated for the nth time; β is the weight; T n-1 is the link delay between the master and slave clocks obtained after the (n - 1)th moving average filtering; T n is the link delay between the master and slave clocks obtained after the nth moving average filtering.

[0117] In the frequency synchronization of the above step A3, the operating frequency of the counter module 17 of the master and slave clocks fluctuates continuously with time, temperature, etc. To reduce the influence of the operating frequency fluctuation on the frequency synchronization accuracy, the ratio of the operating frequencies should be calculated continuously for multiple times, and a moving average filtering algorithm is used to filter the ratio of the operating frequencies, and the ratio of the operating frequencies after the last filtering is used to calculate the frequency division and multiplication factor for frequency synchronization. The moving average filtering algorithm is similar to formula (2), but the weight β is taken as 0.5.

[0118] In the above step A4, when the synchronization control mode indication is the absolute synchronization mode, the synchronization control method is as follows:

[0119] For the oil cylinder PID algorithm control modules 11 of the master and slave clocks, at the specified time starting point, the displacement and pressure given signals are calculated according to the motion mode instructions (such as sinusoidal motion, linear motion, single-step motion).

[0120] The above displacement and pressure given signals are time-varying signals, and the PTP hardware timestamp is used as the time variable. Since time synchronization and frequency synchronization have been completed, the displacement and pressure given signals of the master and slave clocks are synchronously in real time.

[0121] For the oil cylinder PID algorithm control modules 11 of the master and slave clocks, through PID closed-loop control, the actual displacement and pressure signals of the hydraulic cylinder 2 are made to strictly follow the displacement and pressure given signals.

[0122] In the above step A4, when the synchronization control mode instruction is the tracking synchronization mode, the synchronization control method is as follows:

[0123] For the oil cylinder PID algorithm control module 11 of the master clock, at the specified time starting point, the oil cylinder displacement and pressure given signals are calculated according to the motion mode instructions (such as sinusoidal motion, linear motion, single-step motion).

[0124] The above displacement and pressure given signals are time-varying signals, and the PTP hardware timestamp is used as the time variable.

[0125] For the oil cylinder PID algorithm control module 11 of the master clock, it periodically notifies the UDP / TCP module 15 to send the oil cylinder displacement and pressure information message, and the message contains the master clock oil cylinder displacement and pressure given signals at the sending moment, as well as the PTP hardware timestamp of the master clock. The sending period is determined according to the network capacity and synchronization control accuracy, and is generally 1 ms.

[0126] After the UDP / TCP module 15 of the slave clock receives the oil cylinder displacement and pressure information message, it sends the message information to the oil cylinder PID algorithm control module 11. The oil cylinder PID algorithm control module 11 calculates the slave clock oil cylinder displacement and pressure given signals at the receiving moment according to the difference between the PTP hardware timestamp of the slave clock at the receiving moment and the PTP hardware timestamp of the master clock, and the master clock oil cylinder displacement and pressure given signals. At the same time, through methods such as interpolation and fitting, the complete slave clock oil cylinder displacement and pressure given signals are calculated.

[0127] For the oil cylinder PID algorithm control modules 11 of the master and slave clocks, through PID closed-loop control, the actual displacement and pressure signals of the hydraulic cylinder 2 are made to strictly follow the displacement and pressure given signals.

[0128] In the above step A5, the stop synchronization control method is as follows:

[0129] For the oil cylinder PID algorithm control modules 11 of the master and slave clocks, the motion stop displacement and the pressure given signal are calculated at the specified starting time of the time. The motion stop displacement and the pressure given signal are signals that reach the specified and fixed displacement and pressure values within the specified time.

[0130] The above-mentioned motion stop displacement and pressure given signal are time-varying signals, and the PTP hardware timestamp is used as the time variable. Since the time synchronization and frequency synchronization have been completed, the motion stop displacement and pressure given signals of the master and slave clocks are synchronously real-time.

[0131] For D2, the oil cylinder PID algorithm control modules 11 of the master and slave clocks, through PID closed-loop control, make the actual signals of the displacement and pressure of the hydraulic cylinder 2 strictly follow the motion stop displacement and the pressure given signal. Finally, the hydraulic cylinder 2 stops moving simultaneously and smoothly, avoiding damage.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A multi-cylinder synchronous control system, characterized in that: The system includes a control host computer, several hydraulic cylinders, several cylinder controllers, and a PTP switch; The PTP switch is an Ethernet switch that supports the Precision Time Protocol IEEE 1588V2; Among them, each hydraulic cylinder is controlled for movement by a separate cylinder controller; Each hydraulic cylinder is also equipped with a displacement and pressure sensor, which is responsible for collecting the actual displacement and pressure signals of the hydraulic cylinder; the cylinder controller uses the actual displacement and pressure signals to achieve high-precision PID closed-loop feedback control; The control host computer and multiple cylinder controllers are all connected to the PTP switch through network cables to achieve Ethernet interconnection communication; The cylinder controller uses an FPGA chip as the main control chip; The FPGA chip is equipped with peripheral circuits: a constant temperature crystal oscillator module, a signal conditioning circuit for displacement and pressure sensors, an Ethernet network interface, and a physical layer PHY chip; Among them, the constant temperature crystal oscillator module is used to generate a clock signal with a constant frequency. The FPGA chip divides and multiplies the frequency of this clock, and uses the high-quality clock after frequency division and multiplication as the working clock; The FPGA chip consists of a cylinder PID algorithm control module and an Ethernet communication module; The cylinder PID algorithm control module calculates the displacement and pressure given signals; runs the PID algorithm and outputs a control signal to the hydraulic cylinder; finally, makes the actual displacement and pressure signals collected by the displacement and pressure sensors and modulated by the signal conditioning circuit strictly follow the displacement and pressure given signals; The Ethernet communication module is connected to the PHY chip, receives, sends, and processes Ethernet data, enabling the cylinder controller to have Ethernet communication functions; The FPGA chip also includes a clock manager, provides an input clock and frequency division and multiplication coefficients for the clock manager. The clock manager performs fine frequency multiplication and division on the input clock according to the frequency division and multiplication coefficients, and outputs high-quality working clocks of multiple frequencies for different modules to use; Among them, the working clock of the cylinder PID algorithm control module is 50MHz, and the working clock of the Ethernet communication module is 125MHz; the working frequency of the counter module is 250MHz, that is, the resolution of the PTP hardware timestamp is 4ns; time synchronization means that the time difference corresponding to the difference in the count values of the counter modules of different cylinder controllers is controlled within 1μs.

2. The multi-cylinder synchronization control system according to claim 1, wherein: The Ethernet communication module of the FPGA chip consists of multiple sub-modules, including a MAC layer module, an IP layer module, a UDP / TCP layer module, and a PTP time synchronization module; The PTP time synchronization module includes a counter module for generating PTP hardware timestamps; Among them, the PTP time synchronization module and the PTP switch are responsible for receiving, sending, and processing the PTP clock synchronization messages specified by the PTP protocol to achieve time synchronization within 1μs between multiple cylinder controllers. Time synchronization is the basis for multi-cylinder synchronous control; The PTP clock synchronization messages include Sync, Follow_up, Pdelay_req, Pdelay_resp, and Pdelay_resp_follow_up messages; other PTP clock synchronization message types are not processed, reducing the complexity of FPGA programming and the consumption of logic resources; on the other hand, the number of PTP clock synchronization messages in the network is reduced, reducing the network load; The UDP / TCP layer module is responsible for receiving, sending, and processing UDP / TCP data messages; the UDP / TCP data messages include: PTP master-slave status setting messages, PTP time synchronization status notification messages, oil cylinder synchronization control start / stop messages, and oil cylinder displacement and pressure information messages; the UDP / TCP data messages are used to control the normal operation of the multi-cylinder synchronization control system.

3. A multi-cylinder synchronous control method, characterized in that: The method includes the following steps: Step A1, specify one of the multi-oil cylinder controllers as the master clock and the rest as slave clocks; The implementation method of the above step A1 is: control the host computer to send a PTP master-slave status setting message, specifying one of the multiple oil cylinder controllers as the master clock Master and the others as slave clocks Slave; the UDP / TCP layer module recognizes the message information and notifies the PTP time synchronization module to work in the master clock state or the slave clock state; Step A2, based on the PTP protocol, all slave clocks perform time synchronization and frequency synchronization with the master clock; The implementation method of the time synchronization in the above step A2 is: A211. The PTP clock synchronization module of the master clock periodically notifies the MAC layer module to send Sync and Follow_up messages; after the PTP clock synchronization module of the slave clock receives the Sync and Follow_up messages, it calculates the clock deviation and the sum of the link delays between the master and slave clocks; A212. Measure the link delay based on the P2P delay measurement method. To reduce the network load and improve the real-time performance, it is stipulated that: i) The P2P delay measurement between the master clock and the PTP switch is only initiated by the PTP switch; ii) The P2P delay measurement between the slave clock and the PTP switch is only initiated by the slave clock; iii) Periodically initiate P2P delay measurement; A213. Based on the PTP protocol, the PTP clock synchronization module of the slave clock periodically calculates the link delay between the master and slave clocks; A214. According to A211 and A213, the PTP clock synchronization module of the slave clock calculates the clock deviation and adjusts the count value of the internal counter module, that is, adjusts the PTP hardware timestamp to complete the clock synchronization; the PTP clock synchronization module of the slave clock completes one clock synchronization every time it receives a Follow_up message; The implementation method of the frequency synchronization in the above step A2 is: A221. In A214, if it is determined that the clock deviation is greater than the specified value for several consecutive times, the PTP clock synchronization module of the slave clock starts frequency synchronization and proceeds to step A222; When the PTP clock synchronization module of the slave clock receives the Follow_up message sent by the master clock, it immediately records the PTP hardware timestamp T of the master clock carried in the Follow_up message master_1 , and its own PTP hardware timestamp T slave_1 . At the same time, record the adjustment value T of its own PTP hardware timestamp in this clock synchronization offset ; when receiving the next Follow_up message, immediately record the PTP hardware timestamp T of the master clock carried in the Follow_up message master_2 , and its own PTP hardware timestamp T slave_2 ; then the ratio of the working frequency f of the slave clock counter module slave and the working frequency f of the master clock counter module master is: The PTP clock synchronization module of the slave clock calculates the frequency division and multiplication coefficient according to the ratio of the working frequencies, and sends it to the clock manager. The clock manager adjusts the working frequency of the counter module accordingly to complete one frequency synchronization. Meanwhile, it goes to step A221 to determine again whether frequency synchronization is required. Step A3: Determine whether all slave clocks have completed time synchronization and frequency synchronization with the master clock. If so, go to step A4; if not, go to step A5. Step A4: The system enables the cylinder synchronization control. Step A5: The system stops the cylinder synchronization control. The implementation methods of steps A3, A4, and A5 are as follows: When a slave clock completes or breaks away from the clock synchronization and frequency synchronization with the master clock, it notifies the UDP / TCP module to send a PTP time synchronization status notification message. After receiving it, if the control host computer determines that all slave clocks have completed the clock synchronization and frequency synchronization with the master clock, it sends a cylinder synchronization control start message to enable the synchronization control. After determining that a certain slave clock has broken away from the clock synchronization and frequency synchronization with the master clock, it immediately sends a cylinder synchronization control stop message to stop the synchronization control. After receiving the above cylinder synchronization control start / stop message, the UDP / TCP module notifies the cylinder PID algorithm control module to start / stop the synchronization control. The cylinder synchronization control start message also contains a synchronization control mode indication and a motion mode indication. The cylinder PID algorithm control module adopts different synchronization control algorithms according to the message indication.

4. A multi-cylinder synchronous control method according to claim 3, characterized in that: In step A2, the sliding average filtering algorithm is used to filter the link delay between the master and slave clocks for time synchronization, and the filtered link delay is used for time synchronization. The formula of the sliding average filtering algorithm is: where θ n is the link delay between the master and slave clocks calculated for the nth time; β is the weight; T n-1 is the link delay between the master and slave clocks obtained after the (n - 1)th moving average filtering; T n is the link delay between the master and slave clocks obtained after the nth moving average filtering.

5. A multi-cylinder synchronous control method according to claim 3, characterized in that: In step A2, the ratio of the working frequencies in frequency synchronization is calculated multiple times continuously. The sliding average filtering algorithm is used to filter the ratio of the working frequencies, and the finally filtered ratio of the working frequencies is used for frequency synchronization.

6. A multi-cylinder synchronous control method according to claim 3, characterized in that: In step A4, when the synchronization control mode indication is the absolute synchronization mode, the synchronization control method is as follows: B1. The cylinder PID algorithm control modules of the master and slave clocks calculate the displacement and pressure given signals according to the motion mode indication at the specified time starting point. The displacement and pressure given signals are time-varying signals, and the PTP hardware timestamp is used as the time variable. The motion modes include sinusoidal motion, linear motion, and single-step motion. B2. The cylinder PID algorithm control modules (11) of the master and slave clocks use PID closed-loop control to make the actual displacement and pressure signals of the hydraulic cylinder strictly follow the displacement and pressure given signals.

7. A multi-cylinder synchronous control method according to claim 3, characterized in that: In step A4, when the synchronization control mode indication is the tracking synchronization mode, the synchronization control method is as follows: C1. The cylinder PID algorithm control module of the master clock calculates the cylinder displacement and pressure given signals according to the motion mode indication at the specified time starting point. The displacement and pressure given signals are time-varying signals, and the PTP hardware timestamp is used as the time variable. The motion modes include sinusoidal motion, linear motion, and single-step motion. The oil cylinder PID algorithm control module of the master clock periodically notifies the UDP / TCP module to send the oil cylinder displacement and pressure information message, which includes the oil cylinder displacement and pressure given signals of the master clock at the sending moment and the PTP hardware timestamp of the master clock; After receiving the oil cylinder displacement and pressure information message, the UDP / TCP module of the slave clock sends the message information to the oil cylinder PID algorithm control module; the oil cylinder PID algorithm control module calculates the oil cylinder displacement and pressure given signals of the slave clock at the receiving moment according to the difference between the PTP hardware timestamp of the slave clock and the PTP hardware timestamp of the master clock at the receiving moment and the oil cylinder displacement and pressure given signals of the master clock; at the same time, the complete oil cylinder displacement and pressure given signals of the slave clock are calculated by interpolation and fitting methods; The oil cylinder PID algorithm control modules of the master and slave clocks perform PID closed-loop control to make the actual displacement and pressure signals of the hydraulic cylinder strictly follow the displacement and pressure given signals.

8. A multi-cylinder synchronous control method according to claim 3, characterized in that: In the step A5, the stop synchronization control method is as follows: D1. The oil cylinder PID algorithm control modules of the master and slave clocks calculate the movement stop displacement and pressure given signals at the specified time starting point; the movement stop displacement and pressure given signal is a signal that reaches a specified and fixed displacement and pressure value within a specified time; D2. The oil cylinder PID algorithm control modules of the master and slave clocks perform PID closed-loop control to make the actual displacement and pressure signals of the hydraulic cylinder strictly follow the movement stop displacement and pressure given signals.

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