Semiconductor structure and manufacturing method thereof

Abstract

The present application relates to a semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure includes: providing a substrate, the substrate including a semiconductor substrate, a gate structure, and a dielectric layer, wherein a drain region and a source region are formed in the semiconductor substrate, the gate structure is located between the source region and the drain region, and the dielectric layer covers the gate structure and the semiconductor substrate; forming a contact hole in the substrate, the contact hole penetrating the dielectric layer to the source region and / or the drain region; forming a semiconductor connection structure at least in the contact hole, and forming a contact structure that contacts and covers the surface of the semiconductor connection structure; and forming a conductive structure on the contact structure. The present application can reduce the impact of stress generated during the formation of the contact structure on device performance.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In integrated circuit manufacturing, metal silicides are widely used to form contacts between source and drain electrodes and metals, effectively reducing contact resistance. However, the formation of metal silicides also generates stress. Stress can alter the mobility of semiconductor carriers, impacting semiconductor device performance. For example, the stress caused by metal silicide formation can increase the saturation current of an NMOS device by 20%. Summary of the Invention

[0003] Based on this, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same.

[0004] A method for manufacturing a semiconductor structure, in one embodiment, includes:

[0005] Providing a substrate, the substrate comprising a semiconductor substrate, a gate structure, and a dielectric layer, wherein a drain region and a source region are formed in the semiconductor substrate, the gate structure is located between the source region and the drain region, and the dielectric layer covers the gate structure and the semiconductor substrate;

[0006] forming a contact hole in the substrate, wherein the contact hole penetrates the dielectric layer to the source region and / or the drain region;

[0007] forming a semiconductor connection structure at least in the contact hole, and forming a contact structure that contacts and covers a surface of the semiconductor connection structure;

[0008] A conductive structure is formed on the contact structure.

[0009] In one embodiment, in a direction perpendicular to the extending direction of the contact hole, the contact structure passes through the inside and outside of the region where the contact hole is located.

[0010] In one embodiment, forming a semiconductor connection structure at least in the contact hole and forming a contact structure contacting a surface of the semiconductor connection structure includes:

[0011] The semiconductor connection structure is formed in the contact hole and on the surface of the dielectric layer, and the contact structure is formed on the surface of the semiconductor connection structure.

[0012] In one embodiment, the semiconductor connection structure includes a first connection structure and a second connection structure. The semiconductor connection structure is formed in the contact hole and on the surface of the dielectric layer, and the contact structure is formed on the surface of the semiconductor connection structure, including:

[0013] epitaxially growing the first connection structure inside the contact hole;

[0014] forming a second connection material layer on the surface of the first connection structure and the surface of the dielectric layer;

[0015] forming a contact material layer on the surface of the second connecting material layer;

[0016] Through heat treatment, the contact material layer reacts with a portion of the second connection material layer to form the contact structure, and the remaining second connection material layer constitutes the second connection structure.

[0017] In one embodiment, the epitaxially growing the first connection structure inside the contact hole includes:

[0018] epitaxially growing a first connection material layer based on the semiconductor substrate at the bottom of the contact hole until the first connection material layer fills up and exceeds the contact hole;

[0019] Based on the dielectric layer on both sides of the contact hole, chemical mechanical polishing is performed on the first connection material layer to remove the first connection material layer outside the contact hole. The remaining first connection material layer constitutes the first connection structure.

[0020] In one embodiment, the thickness of the second connection material layer is 10% to 50% of the thickness of the first connection structure.

[0021] In one embodiment, forming a second connection material layer on the surface of the first connection structure and the surface of the dielectric layer includes:

[0022] A second connection material layer is formed on the surface of the first connection structure and the surface of the dielectric layer by a chemical vapor deposition method.

[0023] In one embodiment, after the contact material layer and a portion of the second connection material layer are reacted with each other by heat treatment to form the contact structure, and the remaining second connection material layer forms the second connection structure, the method further comprises:

[0024] The remaining contact material layer is removed.

[0025] In one embodiment, the conductive structure includes a barrier layer and a conductive layer, and forming the conductive structure on the contact structure includes:

[0026] forming a barrier layer on the surface of the contact structure;

[0027] A conductive layer is formed on the surface of the barrier layer.

[0028] In one embodiment,

[0029] The step of forming a semiconductor connection structure in the contact hole and on the surface of the dielectric layer, and forming a contact structure on the surface of the semiconductor connection structure, comprises:

[0030] Epitaxially growing a semiconductor connection material layer based on the semiconductor substrate at the bottom of the contact hole until the semiconductor connection material layer fills and covers the surface of the dielectric layer;

[0031] planarizing the semiconductor connection material layer, removing a portion of the semiconductor connection material layer outside the contact hole, and the remaining semiconductor connection material layer constitutes the semiconductor intermediate material layer;

[0032] forming a contact material layer on the surface of the semiconductor intermediate material layer;

[0033] The contact material layer reacts with a portion of the semiconductor intermediate material layer through heat treatment to form the contact structure, and the remaining semiconductor intermediate material layer constitutes the semiconductor connection structure.

[0034] A semiconductor structure comprising:

[0035] A substrate, comprising a semiconductor substrate, a gate structure, and a dielectric layer, wherein the semiconductor substrate has a source region and a drain region, the gate structure is located between the source region and the drain region, and the dielectric layer covers the gate structure and the semiconductor substrate;

[0036] a contact hole, located in the substrate, extending from the dielectric layer to the source region and / or the drain region;

[0037] a semiconductor connection structure, located at least in the contact hole and in contact with the source region and / or the drain region;

[0038] a contact structure, contacting and covering the surface of the semiconductor connection structure;

[0039] The conductive structure is located on the contact structure.

[0040] In one embodiment, the semiconductor connection structure is located in the contact hole and on the surface of the dielectric layer, and the contact structure is located on the surface of the semiconductor connection structure.

[0041] In one embodiment, the semiconductor connection structure includes:

[0042] a first connection structure, located in the contact hole and in contact with the source region and / or the drain region;

[0043] The second connection structure is located on the surface of the first connection structure and the surface of the dielectric layer.

[0044] In one embodiment, the first connecting structure fills the contact hole.

[0045] In one embodiment, the conductive structure includes:

[0046] a barrier layer, located on the surface of the contact structure;

[0047] The conductive layer is located on the surface of the barrier layer.

[0048] In one embodiment, the barrier layer includes a titanium nitride layer, the conductive layer includes a metal layer, the semiconductor connection structure includes a doped polysilicon layer, and the contact structure includes a metal silicide layer.

[0049] In the semiconductor structure and its manufacturing method, the contact structure and the conductive channel between the source region and the drain region are isolated by the semiconductor connection structure, thereby reducing the influence of stress generated when the contact structure is formed on device performance.

[0050] At the same time, in some embodiments, since the contact structure passes through the inside and outside of the area where the contact hole is located in a direction perpendicular to the extension direction of the contact hole, the contact surface between the conductive structure and the contact structure also passes through the inside and outside of the area where the contact hole is located in this direction, thereby greatly increasing the contact area between the contact structure and the conductive structure, thereby effectively reducing the contact resistance between the two, thereby effectively reducing the power consumption of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided in one embodiment;

[0053] Figures 2 to 11 A schematic diagram of a semiconductor structure fabrication process is provided in one embodiment;

[0054] Figures 12 to 18 A schematic structural diagram of a semiconductor structure fabrication process is provided in another embodiment.

[0055] Description of reference numerals:

[0056] 100-substrate, 110-semiconductor substrate, 111-source region, 112-drain region, 120-gate structure, 121-gate dielectric layer, 122-polysilicon layer, 123-gate barrier layer, 124-gate metal layer, 130-dielectric layer, 100a-contact hole, 200-semiconductor connection structure, 210-first connection structure, 220-second connection structure, 221-second connection material layer, 201-semiconductor connection material layer, 202-semiconductor intermediate material layer, 300-contact structure, 301-contact material layer, 400-conductive structure, 410-barrier layer, 420-conductive layer. DETAILED DESCRIPTION

[0057] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0059] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0060] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0061] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.

[0063] In one embodiment, see Figure 1 , provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0064] Step S100, providing a substrate 100, the substrate comprising a semiconductor substrate 110, a gate structure 120 and a dielectric layer 130, wherein a drain region 112 and a source region 111 are formed in the semiconductor substrate 110, the gate structure 120 is located between the source region 111 and the drain region 112, and the dielectric layer 130 covers the gate structure 120 and the semiconductor substrate 110, see Figure 2 ;

[0065] Step S200: forming a contact hole 100a in the substrate 100. The contact hole 100a penetrates the dielectric layer 130 to the source region 111 and / or the drain region 112. Figure 3 ;

[0066] Step S300, forming a semiconductor connection structure 200 at least in the contact hole 100a, and forming a contact structure 300 that contacts and covers the surface of the semiconductor connection structure 200, see Figure 8 ;

[0067] Step S400: forming a conductive structure 400 on the contact structure 300. Figure 11 .

[0068] In step S100, a semiconductor substrate 110 may include, but is not limited to, a silicon substrate. Shallow trench isolation (STI) structures may be formed within the semiconductor substrate 110. The STI structures isolate the semiconductor substrate 110 into multiple active regions. Each active region is used to form a semiconductor device such as a MOS transistor. A drain region 112 and a source region 111 are both formed within the active region. The active region between the source region 111 and the drain region 112 forms a conductive channel.

[0069] The gate structure 120 is located between the source region 111 and the drain region 112 .

[0070] As an example, the gate structure 120 may be formed on the semiconductor substrate 110 between the source region 111 and the drain region 112 .

[0071] Specifically, the gate structure 120 may include a gate dielectric layer 121, a polysilicon layer 122, a gate barrier layer 123, and a gate metal layer 124, etc., which are sequentially formed on the semiconductor substrate 110. The gate dielectric layer 121 may be made of silicon dioxide (SiO2), etc. The gate barrier layer 123 may be made of titanium nitride (TiN), etc. The gate metal layer 124 may be made of tungsten (W), etc.

[0072] Of course, the form of the gate structure 120 is not limited to this. For example, the gate structure 120 may also be a buried gate structure. In this case, a trench is formed in the active region, the gate structure 120 is formed in the trench, and the source region 111 and the drain region 112 are formed on both sides of the trench.

[0073] The dielectric layer 130 may include multiple insulating dielectric layers (not shown) that cover the gate structure 120 and the semiconductor substrate 110 to provide insulation protection thereto. Of course, the dielectric layer 130 may also include one insulating dielectric layer, which is not limited here.

[0074] In step S200 , a plurality of contact holes 100 a may be formed in the substrate 100 by etching or other methods.

[0075] In step S300, the semiconductor connection structure 200 is formed at least in the contact hole 100a. That is, the semiconductor connection structure 200 can be formed only in the contact hole 100a, or can be formed simultaneously in the contact hole 100a and on the surface of the dielectric layer 130 outside the contact hole 100a (see Figure 8 ).

[0076] The semiconductor connection structure 200 is a semiconductor structure that has been doped to provide good electrical conductivity. It has the same doping type as the source region 111 and the drain region 112. This allows for good conductive contact with the source region 111 and the drain region 112. For example, the semiconductor connection structure 200 can be made of the same material (e.g., silicon) as the semiconductor substrate 110 and have the same doping concentration as the source region 111 and the drain region 112.

[0077] The contact structure 300 contacts the surface of the semiconductor connection structure 200, thereby achieving good conductive contact therewith. Specifically, the contact structure 300 can be a metal silicide (such as cobalt silicide (CoSi)).

[0078] In step S400 , the conductive structure 400 may be made of a metal material (such as metal W). The conductive structure 400 is connected to the semiconductor connection structure 200 via the contact structure 300 , thereby effectively reducing contact resistance.

[0079] In this embodiment, since the contact structure 300 and the conductive channel between the source region 111 and the drain region 112 are isolated by the semiconductor connection structure 200 , the influence of stress generated when the contact structure 300 is formed on device performance can be reduced.

[0080] In one embodiment, the contact structure 300 formed in step S300 passes through the inside and outside of the region where the contact hole is located in a direction perpendicular to the direction in which the contact hole extends. In this case, the contact surface between the conductive structure 400 and the contact structure 300 can also pass through the inside and outside of the region where the contact hole is located in this direction, thereby greatly increasing the contact area between the contact structure 300 and the conductive structure 400, effectively reducing the contact resistance between the two, and thus effectively reducing device power consumption.

[0081] In one embodiment, step S300 includes:

[0082] In step S300 a , a semiconductor connection structure 200 is formed in the contact hole 100 a and on the surface of the dielectric layer 130 , and a contact structure 300 is formed on the surface of the semiconductor connection structure 200 .

[0083] In this case, the semiconductor connection structure 200 is formed simultaneously on the surface of the dielectric layer 130 within the contact hole 100a and outside the contact hole 100a, while the contact structure 300 is formed on the surface of the semiconductor connection structure 200. Therefore, the contact area between the contact structure 300 and the conductive structure 400 can be increased while also increasing the contact area between the contact structure 300 and the semiconductor connection structure 200, thereby reducing the contact resistance therebetween.

[0084] Therefore, this embodiment can further reduce the contact resistance between the conductive structure 400 and the semiconductor connection structure 200 , thereby further reducing the power consumption of the device.

[0085] In one embodiment, see Figure 8 The semiconductor connection structure 200 includes a first connection structure 210 and a second connection structure 220. Both the first connection structure 210 and the second connection structure 220 are semiconductor structures that have been doped to provide good electrical conductivity. Furthermore, the materials and doping concentrations of the two structures can be the same or different.

[0086] At this time, step S300a includes:

[0087] Step S311: epitaxially grow the first connection structure 210 inside the contact hole 100a. Figure 5 ;

[0088] Step S312: forming a second connection material layer 221 on the surface of the first connection structure 210 and the surface of the dielectric layer 130. Figure 6 ;

[0089] Step S313: forming a contact material layer 301 on the surface of the second connection material layer 221. Figure 7 ;

[0090] Step S314: Through heat treatment, the contact material layer 301 reacts with a portion of the second connection material layer 221 to form a contact structure 300, and the remaining second connection material layer 221 constitutes the second connection structure 220. Figure 8 .

[0091] In step S311, the first connection structure 210 is epitaxially grown on the semiconductor substrate 110 at the bottom of the contact hole 100a (specifically, on the source region 111 and the drain region 112 at the bottom of the contact hole 100a). As an example, when the semiconductor substrate 110 is a silicon substrate, the first connection structure 210 can be homogeneously grown on the silicon substrate.

[0092] In step S312 , as an example, the second connection material layer 221 may be formed on the surface of the first connection structure 210 and the surface of the dielectric layer 130 by chemical vapor deposition.

[0093] Of course, the second connection material layer 221 may also be formed by other methods (such as physical vapor deposition), and there is no limitation to this.

[0094] In step S313, the contact material layer 301 may be made of metal cobalt (Co) and / or titanium (Ti), etc. It may also be formed on the surface of the second connection material layer 221 by deposition. The deposition thickness of the contact material layer 301 may be 5 nm to 10 nm.

[0095] In step S314 , the heat treatment may include subjecting the structure after the contact material layer 301 is formed to a high temperature annealing at 400° C. to 800° C. At this time, the metal material such as Co diffuses into the second connection material layer 221 and reacts with it, thereby forming SiCo, CoTi, etc. as the contact structure 300 .

[0096] Meanwhile, the remaining unreacted second connection material layer 221 constitutes the second connection structure 220 .

[0097] In this embodiment, the first connection structure 210 and the second connection structure 220 formed through different steps together constitute the semiconductor connection structure 200 , thereby making the manufacturing process thereof more convenient.

[0098] In one embodiment, step S311 includes:

[0099] Step S311, based on the semiconductor substrate 110 at the bottom of the contact hole 100a, epitaxially grow the first connection material layer 211 until the first connection material layer 211 fills up and exceeds the contact hole 100a, see Figure 4 ;

[0100] Step S312: Based on the dielectric layer 130 on both sides of the contact hole 100a, the first connection material layer 211 is subjected to chemical mechanical polishing to remove the first connection material layer 211 outside the contact hole 100a. The remaining first connection material layer 211 constitutes the first connection structure 210. Figure 5 .

[0101] In step S311 , a first connection material layer 211 is epitaxially grown from the semiconductor substrate 110 (specifically, the source 111 and the drain 112 ) at the bottom of the contact hole 100 a .

[0102] In step S312, the top film layer of the dielectric layer 130 on both sides of the contact hole 100a may include a polishing stop layer 131, such as a silicon nitride film layer. In this case, during chemical mechanical polishing, the polishing process may automatically stop at the top film layer of the dielectric layer 130 (e.g., the silicon nitride film layer), thereby removing the first connection material layer 211 outside the contact hole 100a. The remaining first connection material layer 211 fills the contact hole 100a, thereby forming the first connection structure 210.

[0103] In this embodiment, the contact hole 100a can be filled and leveled by the first connection structure 210. This allows the second connection material layer 221 and the contact material layer 301 formed in subsequent steps to be formed on a flat surface, thereby making the second connection material layer 221 and the contact material layer 301 uniform in thickness and flat in surface.

[0104] In one embodiment, the thickness of the second connection material layer 221 formed in step S312 is set to 10% to 50% of the thickness of the first connection structure 210 (i.e., the depth of the contact hole 100a). In this case, after a portion of the second connection material layer 221 reacts with the contact material layer 301 in step S314, the second connection structure 220 formed by the remaining second connection material layer 221 has sufficient thickness to form a good conductive contact with the contact structure 300 formed by the reaction, thereby effectively reducing power consumption; and the thickness of the remaining second connection material layer 221 is not too high to affect the overall thickness of the device.

[0105] In one embodiment, after step S314, the method further includes:

[0106] Step S315, removing the remaining contact material layer 301, see Figure 9 .

[0107] At this time, step S400 can directly deposit the conductive structure material on the surface of the contact structure 300 to form the conductive structure 400 , thereby ensuring that the performance of the conductive structure 400 is stable and reliable.

[0108] Of course, in some embodiments, the remaining contact material layer 301 may not be removed after step S314 . At this time, a conductive structure material may be deposited on the surface of the remaining contact material layer 301 to form the conductive structure 400 .

[0109] In one embodiment, the conductive structure 400 includes a barrier layer 410 and a conductive layer 420. In this case, step S400 includes:

[0110] Step S410: forming a barrier layer 410 on the surface of the contact structure 300. Figure 10 ;

[0111] Step S420, forming a conductive layer 420 on the surface of the barrier layer 410, see Figure 11 .

[0112] In step S410 , a material such as titanium nitride may be deposited on the surface of the contact structure 300 by chemical vapor deposition or the like, thereby forming a barrier layer 410 .

[0113] In step S420 , a metal material (such as W) may be deposited on the surface of the barrier layer 410 by chemical vapor deposition or sputtering, thereby forming the conductive layer 420 .

[0114] In this embodiment, by forming the barrier layer 410 between the conductive layer 420 and the contact structure 300 , it is possible to effectively prevent metal atoms in the conductive layer from diffusing into the contact structure 300 and affecting its performance.

[0115] In one embodiment, step S300a includes:

[0116] Step S321: epitaxially grow a semiconductor connection material layer 201 based on the semiconductor substrate 110 at the bottom of the contact hole 100a, until the semiconductor connection material layer 201 fills and covers the surface of the dielectric layer 130. Figure 12 ;

[0117] Step S322, planarizing the semiconductor connection material layer 201, removing a portion of the semiconductor connection material layer 201 outside the contact hole 100a, and the remaining semiconductor connection material layer 201 constitutes the semiconductor intermediate material layer 202, see Figure 13 ;

[0118] Step S323, forming a contact material layer 301 on the surface of the semiconductor intermediate material layer 202, see Figure 14 ;

[0119] Step S324: Through heat treatment, the contact material layer 301 reacts with a portion of the semiconductor intermediate material layer 202 to form a contact structure 300. The remaining semiconductor intermediate material layer 202 constitutes the semiconductor connection structure 200. Figure 15 .

[0120] In step S321 , the epitaxially grown semiconductor connection material layer 201 further extends to the surface of the dielectric layer 130 and covers the surface of the dielectric layer 130 .

[0121] In step S322 , only a portion of the semiconductor connection material layer 201 outside the contact hole 100 a is removed, while the other portion remains on the surface of the dielectric layer 130 .

[0122] In step S323 , a contact material layer 301 is formed on the planarized surface.

[0123] In step S324 , the remaining semiconductor intermediate material layer 202 includes the semiconductor intermediate material layer 202 located within the contact hole 100 a and the unreacted semiconductor intermediate material layer 202 outside the contact hole 100 a .

[0124] The semiconductor connection structure 200 formed in this embodiment is formed by the same process film layer, and therefore has good uniformity.

[0125] It is understood that after step S324, the remaining contact material layer 301 may be removed. Figure 16 Meanwhile, the subsequent step S400 may include:

[0126] Step S410: forming a barrier layer 410 on the surface of the contact structure 300. Figure 17 ;

[0127] Step S420, forming a conductive layer 420 on the surface of the barrier layer 410, see Figure 18 .

[0128] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0129] In one embodiment, a semiconductor structure is further provided, including a substrate 100 , a contact hole 100 a , a semiconductor connection structure 200 , a contact structure 300 , and a conductive structure 400 .

[0130] Substrate 100 includes a semiconductor substrate 110, a gate structure 120, and a dielectric layer 130. Semiconductor substrate 110 includes a source region 111 and a drain region 112. Gate structure 120 is located between source region 111 and drain region 112. Dielectric layer 130 covers gate structure 120 and semiconductor substrate 110. Contact hole 100a is located in substrate 100 and extends from dielectric layer 130 to source region 111 and / or drain region 112. Semiconductor connection structure 200 is located at least within contact hole 100a and contacts source region 111 and / or drain region 112.

[0131] The contact structure 300 contacts and covers the surface of the semiconductor connection structure 200 .

[0132] The conductive structure 400 is located on the contact structure 300 .

[0133] In one embodiment, the semiconductor connection structure 200 is located in the contact hole 100 a and on the surface of the dielectric layer 130 , and the contact structure 300 is located on the surface of the semiconductor connection structure 200 .

[0134] In one embodiment, the semiconductor connection structure 200 includes a first connection structure 210 and a second connection structure 220. The first connection structure 210 is located in the contact hole 100a and contacts the source region 111 and / or the drain region 112. The second connection structure 220 is located on the surface of the first connection structure 210 and the surface of the dielectric layer 130.

[0135] In one embodiment, the first connection structure 210 fills the contact hole 100 a .

[0136] In one embodiment, the conductive structure 400 includes a barrier layer 410 and a conductive layer 420 . The barrier layer 410 is located on the surface of the contact structure 300 . The conductive layer 420 is located on the surface of the barrier layer 410 .

[0137] In one embodiment, the barrier layer 410 includes a titanium nitride layer, the conductive layer 420 includes a metal layer, the semiconductor connection structure 200 includes a doped polysilicon layer, and the contact structure 300 includes a metal silicide layer.

[0138] For specific limitations on the semiconductor structure, please refer to the limitations on the semiconductor structure manufacturing method above, which will not be repeated here.

[0139] Throughout this specification, references to terms such as "one embodiment," "some embodiments," and "ideal embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0140] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a semiconductor substrate, a gate structure, and a dielectric layer, wherein a drain region and a source region are formed in the semiconductor substrate, the gate structure is located between the source region and the drain region, and the dielectric layer covers the gate structure and the semiconductor substrate; forming a contact hole in the substrate, wherein the contact hole penetrates the dielectric layer to the source region and / or the drain region; A semiconductor connection structure is formed in the contact hole and on the surface of the dielectric layer, and a contact structure is formed on the surface of the semiconductor connection structure, comprising: epitaxially growing a first connection structure in the contact hole; forming a second connection material layer on the surface of the first connection structure and the surface of the dielectric layer; forming a contact material layer on the surface of the second connection material layer; and reacting the contact material layer with a portion of the second connection material layer through heat treatment to form the contact structure, with the remaining second connection material layer constituting a second connection structure, wherein the semiconductor connection structure includes the first connection structure and the second connection structure, the contact structure contacts and covers the surface of the semiconductor connection structure, and in a direction perpendicular to the extension direction of the contact hole, the contact structure passes through the inside and outside of the region where the contact hole is located; A conductive structure is formed on the contact structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The epitaxially growing the first connection structure inside the contact hole includes: epitaxially growing a first connection material layer based on the semiconductor substrate at the bottom of the contact hole until the first connection material layer fills up and exceeds the contact hole; Based on the dielectric layer on both sides of the contact hole, chemical mechanical polishing is performed on the first connection material layer to remove the first connection material layer outside the contact hole. The remaining first connection material layer constitutes the first connection structure.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The thickness of the second connection material layer is 10% to 50% of the thickness of the first connection structure.

4. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, wherein: The forming of a second connection material layer on the surface of the first connection structure and the surface of the dielectric layer includes: The second connection material layer is formed on the surface of the first connection structure and the surface of the dielectric layer by a chemical vapor deposition method.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: After the contact material layer and a portion of the second connection material layer are reacted with each other through heat treatment to form the contact structure, and the remaining second connection material layer forms the second connection structure, the method further includes: The remaining contact material layer is removed.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The conductive structure includes a barrier layer and a conductive layer. The conductive structure is formed on the contact structure, including: forming a barrier layer on the surface of the contact structure; A conductive layer is formed on the surface of the barrier layer.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming a semiconductor connection structure in the contact hole and on the surface of the dielectric layer, and forming a contact structure on the surface of the semiconductor connection structure, comprises: Epitaxially growing a semiconductor connection material layer based on the semiconductor substrate at the bottom of the contact hole until the semiconductor connection material layer fills the contact hole and covers the surface of the dielectric layer; planarizing the semiconductor connection material layer, removing a portion of the semiconductor connection material layer outside the contact hole, and the remaining semiconductor connection material layer constitutes a semiconductor intermediate material layer; forming a contact material layer on the surface of the semiconductor intermediate material layer; The contact material layer reacts with a portion of the semiconductor intermediate material layer through heat treatment to form the contact structure, and the remaining semiconductor intermediate material layer constitutes the semiconductor connection structure.

8. A semiconductor structure, characterized in that The semiconductor structure is manufactured by the method for manufacturing the semiconductor structure according to claim 1, comprising: A substrate, comprising a semiconductor substrate, a gate structure, and a dielectric layer, wherein the semiconductor substrate has a source region and a drain region, the gate structure is located between the source region and the drain region, and the dielectric layer covers the gate structure and the semiconductor substrate; a contact hole, located in the substrate, extending from the dielectric layer to the source region and / or the drain region; a semiconductor connection structure, located at least in the contact hole and in contact with the source region and / or the drain region; a contact structure, contacting and covering the surface of the semiconductor connection structure; The conductive structure is located on the contact structure.

9. The semiconductor structure according to claim 8, wherein: The semiconductor connection structure is located in the contact hole and on the surface of the dielectric layer, and the contact structure is located on the surface of the semiconductor connection structure.

10. The semiconductor structure according to claim 9, wherein: The semiconductor connection structure includes: a first connection structure, located in the contact hole and in contact with the source region and / or the drain region; The second connection structure is located on the surface of the first connection structure and the surface of the dielectric layer.

11. The semiconductor structure according to claim 10, wherein: The first connecting structure fills the contact hole.

12. The semiconductor structure according to claim 8, wherein: The conductive structure includes: a barrier layer, located on the surface of the contact structure; The conductive layer is located on the surface of the barrier layer.

13. The semiconductor structure according to claim 12, wherein: The barrier layer includes a titanium nitride layer, the conductive layer includes a metal layer, the semiconductor connection structure includes a doped polysilicon layer, and the contact structure includes a metal silicide layer.

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