Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a substrate, a plurality of back plate electrodes located on a first surface side of the substrate, and a protective layer located on the first surface side and covering the back plate electrodes. The thermal conductivity of the protective layer is greater than or equal to 400 W / (m*k). The protective layer is provided with an opening corresponding to the position of each back plate electrode. The area of the back plate electrode exposed from the opening is used for bonding connection with a light-emitting chip. In this way, the heat dissipation path of the light-emitting chip is prolonged, and the heat dissipation performance of the light-emitting chip is effectively improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Micro LED chip display technology, also known as miniaturized and matrixed light-emitting chip technology, refers to a high-density, tiny LED array integrated on a single chip. It has advantages such as high efficiency, short response time, long lifespan, and wide operating range, and is now widely used in terminal products such as televisions, augmented and virtual reality (AR / VR), automotive displays, wearable devices, and smartphones.

[0003] However, after long-term research, the inventors discovered that the temperature of the light-emitting chip gradually increases over time during use. When the temperature reaches a certain threshold, defects already present within the chip material can rapidly multiply and proliferate. At this point, the light-emitting layer of the chip is at risk of being invaded by these defects, potentially adversely affecting the chip's luminous efficiency, chip lifespan, and the lifespan of the display panel. Therefore, solving the heat dissipation problem of the light-emitting chip has become an urgent issue. Summary of the Invention

[0004] The main technical problem solved by this application is to provide an array substrate and display panel that can extend the heat dissipation path of the light-emitting chip and effectively improve the heat dissipation performance of the light-emitting chip.

[0005] To address the aforementioned technical problems, this application provides a technical solution: an array substrate comprising a substrate; a plurality of backplane electrodes located on one side of a first surface of the substrate; and a protective layer located on one side of the first surface and covering the backplane electrodes; wherein the thermal conductivity of the protective layer is greater than or equal to 400 W / (m*k), and the protective layer has openings corresponding to the positions of each backplane electrode, with a portion of the backplane electrode exposed through the openings for bonding with a light-emitting chip. In this design, since the light-emitting chip generates a large amount of heat during operation, the protective layer with a thermal conductivity greater than or equal to 400 W / (m*k) allows the heat from the light-emitting chip to be transferred through the backplane electrodes to the thermally conductive protective layer, providing a heat dissipation channel for the light-emitting chip, effectively extending the heat dissipation path, improving the heat dissipation performance of the light-emitting chip, and thus improving the reliability of the light-emitting chip.

[0006] In this design, the resistivity of the protective layer gradually increases along the direction from the substrate to the back electrode. This design extends the heat dissipation path and water-oxygen path of the light-emitting chip, further improving the reliability of the chip.

[0007] In this design, along the direction from the substrate to the back electrode, the protective layer comprises a doped protective layer and an undoped protective layer stacked sequentially. The doped protective layer comprises a host material and a dopant material, wherein the thermal conductivity of the host material of the doped protective layer and the thermal conductivity of the undoped protective layer are both greater than or equal to 400 W / (m*k). Preferably, the host material of the doped protective layer is the same as the material of the undoped protective layer. More preferably, the host material of the doped protective layer and the material of the undoped protective layer both comprise diamond-like carbon. This design allows the conductivity of the protective layer to vary in a gradient along the direction from the substrate to the back electrode, reducing delamination and peeling between the layers.

[0008] The doped protective layer comprises a first doped sub-protective layer and a second doped sub-protective layer stacked sequentially, with the first doped sub-protective layer located between the first surface and the second doped sub-protective layer. The doped material in the first doped sub-protective layer comprises a metal, and the doped material in the second doped protective layer comprises a non-metal. Preferably, the mass of the doped material in the first doped sub-protective layer accounts for less than or equal to 10% of the total mass of the first doped sub-protective layer, and the mass of the doped material in the second doped protective layer accounts for less than or equal to 30% of the total mass of the second doped protective layer. This design allows for a transition in the elastic modulus between the first and second doped sub-protective layers, improving deformation compatibility under bending, folding, or load conditions, and reducing delamination and peeling.

[0009] In this design, the metal doping ratio in the first dopant layer gradually decreases along the direction from the substrate to the back electrode; and / or, the non-metal doping ratio in the second dopant layer gradually decreases along the direction from the substrate to the back electrode. This design allows for a smoother transition in the elastic modulus between the layers of the first and second dopant layers, further preventing delamination.

[0010] The array substrate further includes a thin-film transistor layer located between the plurality of backplane electrodes and the first surface, and a blind via extending toward the substrate is disposed within the thin-film transistor layer adjacent to the backplane electrodes. This design improves the heat dissipation performance of the light-emitting chip and enhances its reliability.

[0011] In this design, one end of the blind via is connected to the backplate electrode; or, the backplate electrode is electrically connected to the metal layer furthest from the substrate in the thin-film transistor layer, and one end of the blind via is connected to the metal layer furthest from the substrate. This design allows heat from the light-emitting chip to be directly transferred to the blind via, effectively improving the heat dissipation performance of the light-emitting chip.

[0012] The thin-film transistor layer includes: a semiconductor layer located on one side of the first surface, comprising multiple channel regions and a first conductive region and a second conductive region located on both sides of each channel region; a patterned first metal layer located on the side of the semiconductor layer facing away from the first surface; a patterned second metal layer located on the side of the first metal layer facing away from the first surface; and a patterned third metal layer located on the side of the second metal layer facing away from the first surface, wherein the third metal layer has a first pass terminal electrically connected to the first conductive region and a second pass terminal electrically connected to the second conductive region; and the first pass terminal is electrically connected to the backplate electrode; wherein the blind via extends from the side of the first pass terminal facing away from the backplate electrode to the first surface; or, the blind via extends from the side of the backplate electrode facing the substrate to the first surface; preferably, in the extension direction of the blind via, the blind via includes a first sub-blind via and a second sub-blind via, wherein the first metal layer and / or the second metal layer are disposed between the first sub-blind via and the second sub-blind via. This design provides an effective heat dissipation channel for the light-emitting chip.

[0013] The surface of the area where the backplate electrode is exposed from the opening has an uneven structure. This design effectively extends the heat dissipation path of the light-emitting chip and improves its lifespan.

[0014] To address the aforementioned technical problems, another technical solution adopted in this application is to provide a display panel comprising an array substrate as mentioned in any of the above embodiments and a plurality of light-emitting chips, wherein the light-emitting chips are bonded and connected to the backplate electrode. This design enables the display panel to possess advantages such as good heat dissipation performance, long service life, and high display quality.

[0015] Unlike existing technologies, the advantages of this application are as follows: This application provides an array substrate and a display panel, wherein the array substrate includes a substrate; a plurality of backplate electrodes located on one side of a first surface of the substrate; and a protective layer located on one side of the first surface and covering the backplate electrodes; wherein the thermal conductivity of the protective layer is greater than or equal to 400 W / (m*k), and the protective layer has openings corresponding to the positions of each backplate electrode, with the exposed area of ​​a portion of the backplate electrode used for bonding with a light-emitting chip. Through the above design, since the light-emitting chip generates a large amount of heat during operation, the heat from the light-emitting chip is transferred through the backplate electrodes to the thermally conductive protective layer by the protective layer with a thermal conductivity greater than or equal to 400 W / (m*k), providing a heat dissipation channel for the light-emitting chip, effectively extending the heat dissipation path of the light-emitting chip, improving the heat dissipation performance of the light-emitting chip, and thus improving the reliability of the light-emitting chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0017] Figure 1 This is a schematic diagram of the structure of one embodiment of the array substrate of this application;

[0018] Figure 2 yes Figure 1 A schematic diagram of the structure of one embodiment of the middle protective layer;

[0019] Figure 3 yes Figure 2 A schematic diagram of the structure of one embodiment of the medium-doped protective layer;

[0020] Figure 4 This is a schematic diagram of another embodiment of the array substrate of this application;

[0021] Figure 5 yes Figure 1 A schematic diagram of one embodiment of the backplate electrode;

[0022] Figure 6 This is a schematic diagram of the structure of one embodiment of the display panel of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0024] Please see Figure 1 , Figure 1This is a schematic diagram of one embodiment of the array substrate of this application. The array substrate 100 provided in this application includes a substrate 10, a plurality of backplate electrodes 20, and a protective layer 30. The substrate 10 can be a glass substrate or a flexible substrate made of a polymer, such as polyimide (PI). The plurality of backplate electrodes 20 are located on one side of the first surface 101 of the substrate 10. The protective layer 30 is located on one side of the first surface 101 and covers the backplate electrodes 20. The protective layer 30 has openings 50 corresponding to the positions of each backplate electrode 20, and the exposed areas of a portion of the backplate electrode 20 are used for bonding with a light-emitting chip (not shown). Furthermore, in other embodiments, the array substrate 100 may also include a thin-film transistor layer 40, which is located between the plurality of backplate electrodes 20 and the first surface 101. The thin-film transistor layer 40 has a plurality of driving circuits, which are electrically connected to the backplate electrodes 20 and used to drive the light-emitting chip to emit light.

[0025] It is understood that a portion of the backplate electrode 20 is covered by the protective layer 30, while a portion of the backplate electrode 20 is exposed through the opening 50 of the protective layer 30. In this embodiment, the thermal conductivity of the protective layer 30 is greater than or equal to 400 W / (m*k), for example, the thermal conductivity of the protective layer 30 is set to 400 W / (m*k), 600 W / (m*k), or 800 W / (m*k). Through the above embodiment, since the light-emitting chip generates a large amount of heat during operation, the heat from the light-emitting chip is transferred through the backplate electrode 20 to the thermally conductive protective layer 30 by utilizing the protective layer 30 with a thermal conductivity greater than or equal to 400 W / (m*k), providing a heat dissipation channel for the light-emitting chip, effectively extending the heat dissipation path of the light-emitting chip, improving the heat dissipation performance of the light-emitting chip, and thus improving the reliability of the light-emitting chip.

[0026] Optionally, in this embodiment, the protective layer 30 includes multiple layers of insulators stacked together, and the resistivity of each insulator layer is in the Y direction along the substrate 10 to the back electrode 20 (specifically as shown in the attached figure). Figure 1 The resistivity gradually increases as shown. In other words, the resistivity of the insulator layer in the protective layer 30 is lower the closer it is to the back electrode 20. Through the above implementation method, the resistivity of the protective layer 30 changes in a gradient, ensuring that the insulation performance of the protective layer 30 increases sequentially in the Y direction from the substrate 10 to the back electrode 20. This design not only extends the heat dissipation path of the light-emitting chip, but also extends the water and oxygen path, better blocking external water vapor and oxygen, and further improving the reliability of the light-emitting chip.

[0027] Please see Figure 2 , Figure 2 yes Figure 1A schematic diagram of one embodiment of the protective layer 30. Along the Y direction from the substrate 10 to the back electrode 20, the protective layer 30 includes a doped protective layer 301 and an undoped protective layer 302 stacked sequentially. The doped protective layer 301 is mainly composed of a host material and a dopant material; for example, the dopant material can be a metal or a non-metal, or both. Optionally, the thickness of the undoped protective layer 302 ranges from 100 nm to 1 μm, for example, it can be set to 100 nm, 500 nm, or 1 μm. The thickness of the doped protective layer 301 is determined by the number of layers and is not specifically limited here. Furthermore, the thermal conductivity of the host material of the doped protective layer 301 and the thermal conductivity of the undoped protective layer 302 must satisfy a condition greater than or equal to 400 W / (m*k). Through the above embodiments, the conductivity of the protective layer 30 on the side adjacent to the back electrode 20 is improved by using doped materials, so that the protective layer 30 has a gradient change in the direction Y along the substrate 10 to the back electrode 20, thereby reducing the internal stress in the doped protective layer 301 and reducing the delamination and peeling phenomena between the film layers.

[0028] In one embodiment, the main material of the doped protective layer 301 can be the same as that of the undoped protective layer 302 to reduce the difficulty of fabrication. Of course, in other embodiments, the main material of the doped protective layer 301 and the undoped protective layer 302 can be different materials, as long as the selected materials meet the requirements for thermal conductivity.

[0029] Optionally, in this embodiment, diamond-like carbon (DLC) material can be used as the main material of the doped protective layer 301 and the material of the undoped protective layer 302. Specifically, diamond-like carbon (DLC) is a recently emerging material based on SP... 2 Carbon bonds and SP 3 A diamond-like carbon (DLC) material is an amorphous metastable structure formed by carbon bonds. It shares similar properties with diamond but also possesses the atomic composition of graphite, exhibiting high hardness, high resistivity, good optical properties, and excellent tribological characteristics. When used in the doped protective layer 301 and the undoped protective layer 302, it can improve heat dissipation and water / oxygen barrier properties.

[0030] Of course, in other embodiments, the materials of the main material of the doped protective layer 301 and the material of the undoped protective layer 302 may also include graphene, carbon nanotubes, alumina, porous diamond, boron nitride, etc. The thermal conductivity of the above materials is greater than or equal to 400W / (m*k), and no specific limitation is made here.

[0031] Please refer to the following: Figure 1 and Figure 3 , Figure 3 yes Figure 2A schematic diagram of one embodiment of the doped protective layer 301. In this embodiment, the doped protective layer 301 includes a first doped sub-protective layer 3011 and a second doped sub-protective layer 3012 stacked sequentially, with the first doped sub-protective layer 3011 located between the first surface 101 and the second doped sub-protective layer 3012. The dopant material in the first doped sub-protective layer 3011 includes a metal, and the dopant material in the second doped protective layer 3012 includes a non-metal. Through the above implementation, metal is doped into the first dopant protective layer 3011 and non-metal is doped into the second dopant protective layer 3012, so that the resistivity of each dopant protective layer increases sequentially along the Y direction from the substrate 10 to the back electrode 20. On the one hand, this can extend the heat dissipation path and the water-oxygen path, improving the reliability of the LED chip; on the other hand, it allows for a transition in the elastic modulus between the first dopant protective layer 3011 and the second dopant protective layer 3012, improving the deformation coordination of the first dopant protective layer 3011 and the second dopant protective layer 3012 under bending, folding, or load, reducing delamination and peeling, and avoiding delamination between the first dopant protective layer 3011 and the second dopant protective layer 3012. In addition, the doping of metal and non-metal results in a gradient transition between the first dopant protective layer 3011 and the second dopant protective layer 3012 along the Y direction from the substrate 10 to the back electrode 20, so that the doped protective layer 301 has both conductive and heat dissipation functions as well as insulating functions.

[0032] In one specific embodiment, the first dopant protective layer 3011 is doped with a metal. Optionally, the metal doped in the first dopant protective layer 3011 includes one or more of copper, aluminum, and silver. For example, the metal doped in the first dopant protective layer 3011 can be copper and aluminum. Optionally, the thickness of the first dopant protective layer 3011 ranges from 100 nm to 2 μm; for example, the thickness can be set to 100 nm, 1 μm, or 2 μm. Optionally, the mass of the metal doped in the first dopant protective layer 3011 accounts for a proportion greater than 0 and less than or equal to 10% of the total mass of the first dopant protective layer 3011; for example, the mass of the metal doped in the first dopant protective layer 3011 accounts for 1%, 3%, 5%, 8%, or 10% of the total mass of the first dopant protective layer 3011. By doping metal into the first dopant protective layer 3011 and reasonably setting the doping ratio of the metal, the internal stress in the first dopant protective layer 3011 can be reduced, the adhesion between the first dopant protective layer 3011 and the adjacent layer can be improved, and delamination and peeling phenomena can be reduced.

[0033] In this embodiment, the second dopant protective layer 3012 is doped with a non-metal. Optionally, in some embodiments, the non-metal doped in the second dopant protective layer 3012 includes one or more elements such as nitrogen, silicon, and phosphorus. For example, the metal doped in the second dopant protective layer 3012 can be nitrogen and silicon. Optionally, the thickness of the second dopant protective layer 3012 ranges from 100 nm to 2 μm; for example, the thickness can be set to 100 nm, 1 μm, or 2 μm. Optionally, the mass of the non-metal doped in the second dopant protective layer 3012 accounts for a proportion greater than 0 and less than or equal to 30% of the total mass of the second dopant protective layer 3012; for example, the mass of the non-metal doped in the second dopant protective layer 3012 accounts for 1%, 10%, 20%, 28%, or 30% of the total mass of the second dopant protective layer 3012. By doping non-metals into the second dopant protective layer 3012 and reasonably setting the doping ratio of non-metals, the coordinating effect of non-metallic elements on the main material in the second dopant protective layer 3012 can be fully utilized, reducing the internal stress in the second dopant protective layer 3012 and reducing the occurrence of delamination.

[0034] Please continue reading. Figure 1 and Figure 3 In one specific embodiment, the first doped sub-protective layer 3011 includes multiple first sub-layers (not shown). Along the direction from the substrate 10 to the back electrode 20, the metal doping ratio of each first sub-layer in the first doped sub-protective layer 3011 gradually decreases, resulting in a gradual decrease in conductivity along the Y direction from the substrate 10 to the back electrode 20. This allows the first doped sub-protective layer 3011 to simultaneously perform conductive heat dissipation and insulating functions. It should be noted that the metal doping ratio here refers to the proportion of the mass of the metal doped in the first sub-layer to the total mass of the first sub-layer. In the above design, the doping ratio of the doped metal changes in a gradient, resulting in a smoother transition in the elastic modulus between the layers in the first doped sub-protective layer 3011, stronger adhesion between layers, and further prevention of delamination.

[0035] In another embodiment, the second doped sub-protective layer 3012 includes a plurality of second sub-layers (not shown), and the non-metallic doping ratio of each second sub-layer in the second doped sub-protective layer 3012 gradually decreases along the Y direction from the substrate 10 to the back electrode 20. It should be noted that the non-metallic doping ratio here refers to the proportion of the mass of non-metallic dopant in the second sub-layer to the total mass of the second sub-layer. Through the above embodiments, the elastic modulus between the layers in the second doped sub-protective layer 3012 achieves a smoother transition, further preventing delamination. Optionally, for the first sub-layer and the second sub-layer at the junction of the first doped sub-protective layer 3011 and the second doped sub-protective layer 3012, along the Y direction from the substrate 10 to the back electrode 20, the proportion of metal doped in the first sub-layer furthest from the first surface 101 to the total mass of the first sub-layer is greater than or equal to 5% and less than 10%, and the proportion of non-metallic doped in the second sub-layer closest to the first surface 101 to the total mass of the second sub-layer is greater than 0 and less than or equal to 30%. For example, the metal doping ratio of the first sublayer at the interface is 5%, and the non-metal doping ratio of the second sublayer is 30%. The above embodiment enables a smoother transition in the elastic modulus at the interface between the first dopant layer and the second dopant layer.

[0036] Please see Figure 4 , Figure 4This is a schematic diagram of another embodiment of the array substrate of this application. The thin-film transistor layer 40 provided in this embodiment includes a semiconductor layer 401, a patterned first metal layer 402, a patterned second metal layer 403, and a patterned third metal layer 404. The semiconductor layer 401 is located on one side of the first surface 101, and its material includes, but is not limited to, low-temperature polycrystalline silicon. The semiconductor layer 401 can serve as an oxide active layer, and materials such as IGZO, IZO, AZO, and IGZTO can be selected. The semiconductor layer 401 includes multiple channel regions 4011 and a first conductive region 4012 and a second conductive region 4013 located on both sides of each channel region 4011. Specifically, when the thin-film transistor is a PMOS TFT, boron can be doped by ion implantation; when the thin-film transistor is an NMOS... In TFT, phosphorus can be doped by ion implantation; the first metal layer 402 is located on the side of the semiconductor layer 401 away from the first surface 101, and the first metal layer 402 can serve as the gate layer, and the materials selected include, but are not limited to, Mo, Al, Cu, MoTi, MoNb, etc.; the second metal layer 403 is located on the side of the first metal layer 402 away from the first surface 101; the third metal layer 404 is located on the side of the second metal layer 403 away from the first surface 101, and the third metal layer 404 can serve as the source / drain layer, and the materials selected include, but are not limited to, Ti, Al, TiAlTi, Mo, MoAlMo, TiCu, TiCuTi, MoCuMo, etc.; and the third metal layer 404 is provided with a first pass terminal 4041 electrically connected to the first conductive region 4012 and a second pass terminal 4042 electrically connected to the second conductive region 4013; and the first pass terminal 4041 is electrically connected to the back electrode 20. Furthermore, in this embodiment, an insulating layer is provided between the semiconductor layer 401 and the first metal layer 402. The material of this insulating layer includes, but is not limited to, one or more of silicon oxide, silicon nitride, and silicon oxynitride. An insulating layer is provided between the first metal layer 402 and the second metal layer 403. This insulating layer can serve as a capacitor insulating layer, and its material includes, but is not limited to, an inorganic layer composed of one or more of silicon oxide, silicon nitride, and silicon oxynitride, and may also include an organic layer with a low dielectric constant. An insulating layer is provided between the third metal layer 404 and the second metal layer 403. This insulating layer serves a planarization function and can be selected from one or more of inorganic and organic materials. In addition, the first pass terminal 4041 can be electrically connected to the first conductive region 4012 at the corresponding position through a conductive hole, and the second pass terminal 4042 can be electrically connected to the second conductive region 4013 at the corresponding position through a conductive hole. The material of the conductive material in the conductive hole can be the same as the material of the third metal layer 404.

[0037] Furthermore, such as Figure 4As shown, in this embodiment, a blind via 405 extending toward the substrate 10 is provided in the thin-film transistor layer 40 near the back electrode 20. Specifically, during the fabrication of the array substrate, blind vias 405 are formed at predetermined positions in the thin-film transistor layer 40 near the back electrode 20 using processes such as exposure, development, and etching, and the extending direction of the blind via 405 is toward the substrate 10. Through the above embodiment, the blind via 405 provided in the thin-film transistor layer 40 near the back electrode 20 adds a new heat dissipation channel for heat transfer of the light-emitting chip during use, solving the problem of heat dissipation failure caused by the poor thermal conductivity of the insulating layer in the thin-film transistor layer 40, improving the heat dissipation performance of the light-emitting chip, and thus improving the reliability of the light-emitting chip.

[0038] Optionally, one end of the blind via 405 is connected to the backplate electrode 20. Since the backplate electrode 20 is made of metal, the excellent thermal conductivity of metal does not affect the heat dissipation of the light-emitting chip. Therefore, one end of the blind via 405 can be directly positioned on the side of the backplate electrode 20 closest to the first surface 101 and connected to the backplate electrode 20. The above embodiment directly transfers the heat from the light-emitting chip to the blind via 405 through the backplate electrode 20, providing an effective heat dissipation channel for the light-emitting chip and improving its heat dissipation performance.

[0039] Optionally, the backplane electrode 20 is electrically connected to the metal layer furthest from the substrate 10 in the thin-film transistor layer 40, and one end of the blind via 405 is connected to the metal layer furthest from the substrate 10. In this embodiment, the metal layer furthest from the substrate 10 is the third metal layer 404, and one end of the blind via 405 is connected to the third metal layer 404. Since the third metal layer 404 and the backplane electrode 20 are electrically connected, and both are made of metal, one end of the blind via 405 can be located on the side of the third metal layer 404 near the first surface 101 and connected to the third metal layer 404. Through the above implementation, the heat of the light-emitting chip is transferred to the third metal layer 404 through the backplane electrode 20, and then to the blind via 405 through the third metal layer 404. This method can also provide an effective heat dissipation channel for the light-emitting chip, effectively improving the heat dissipation performance of the light-emitting chip.

[0040] Please continue reading. Figure 4 In one embodiment, the blind via 405 extends continuously from the side of the first passage end 4041 away from the backplate electrode 20 to the first surface 101. Alternatively, the blind via 405 extends continuously from the side of the backplate electrode 20 facing the substrate 10 to the first surface 101. Both embodiments provide an effective heat dissipation channel for the light-emitting chip.

[0041] Of course, in other embodiments, the blind via 405 may also extend intermittently from the side of the first passage end 4041 away from the back plate electrode 20 or from the side of the back plate electrode 20 facing the substrate 10 to the first surface 101. This embodiment cleverly utilizes other metal layers with good conductivity in the thin film transistor layer 40 to intermittently set the blind via 405 in the thin film transistor layer 40. The heat of the light-emitting chip is also transferred through other metal layers, further improving the heat dissipation performance of the light-emitting chip.

[0042] The following describes in detail the implementation of the intermittently configured blind via 405. In this embodiment, in the extending direction of the blind via 405, the blind via 405 includes a first sub-blind via 4051 and a second sub-blind via 4052. One end of the first sub-blind via 4051 is connected to the backplane electrode 20, and one end of the second sub-blind via 4052 is connected to the first surface 101. A first metal layer 402 is disposed between the first sub-blind via 4051 and the second sub-blind via 4052. Through the above implementation, the heat of the light-emitting chip is transferred to the first sub-blind via 4051 through the backplane electrode 20, and then transferred to the second sub-blind via 4052 through the first sub-blind via 4051 and the first metal layer 402. The heat dissipation effect of the light-emitting chip is improved by utilizing the first metal layer 402 with good thermal conductivity, further enhancing the heat dissipation performance of the light-emitting chip.

[0043] Of course, in other embodiments, a second metal layer 403 may be provided between the first sub-blind hole 4051 and the second sub-blind hole 4052, or the first metal layer 402 and the second metal layer 403 may be provided simultaneously, as long as the metal layer can be used to achieve effective heat dissipation of the chip, no specific limitation is made here.

[0044] In one embodiment, the array substrate further includes an electrostatic discharge circuit disposed on the side of the protective layer 30 facing away from the substrate 10, and the backplate electrode 20 is electrically connected to the electrostatic discharge circuit. Through the electrical connection between the backplate electrode 20 and the electrostatic discharge circuit, heat generated during the operation of the light-emitting chip is released; and static electricity generated during the operation of the backplate electrode 20 is discharged, preventing static electricity in the backplate electrode 20 from adversely affecting the light-emitting chip.

[0045] Please see Figure 5 , Figure 5 yes Figure 1 A schematic diagram of one embodiment of the backplate electrode. In one embodiment, the surface of the area exposed from the opening of the backplate electrode 20 can be formed into a concave-convex structure using photolithography, dry etching, or other fabrication methods. The vertical cross-section of the protrusion in this concave-convex structure can be rectangular (e.g., ...). Figure 5 (as shown in (a)) or triangle (as shown in...) Figure 5 As shown in (b)); similarly, the vertical cross-section of the concave portion in this concave-convex structure can be rectangular (e.g., ...). Figure 5(as shown in (a)) or a triangle or inverted trapezoid (as shown in (a)) Figure 5 The shape of the vertical cross-section is not specifically limited here, but can be shown in (b) or elliptical. Through the above embodiments, the heat dissipation path during the light-emitting chip's heating and luminescence processes can be effectively extended, thereby improving the chip's lifespan.

[0046] Of course, in other embodiments, the cross-sectional shape of the area of ​​the back electrode 20 exposed from the opening 50 can also be a mesh or other specific shape, as long as it can extend the heat dissipation path of the light-emitting chip, and no specific limitation is made here.

[0047] Furthermore, the array substrate mentioned in the above embodiments can be sold separately or integrated into a display panel for sale. Please refer to [link / reference]. Figure 6 , Figure 6 This is a schematic diagram of one embodiment of the display panel of this application. This application also provides a display panel 300, including the array substrate 100 mentioned in the above embodiments and a plurality of light-emitting chips 200, wherein the light-emitting chips 200 are bonded to the backplane electrode 20 via metal solder (not shown). The display panel 300 provided in this application has advantages such as good heat dissipation performance, long service life, and high display quality.

[0048] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; Multiple backplate electrodes are located on one side of the first surface of the substrate; A protective layer is located on one side of the first surface and covers the backplate electrode; wherein the thermal conductivity of the protective layer is greater than or equal to 400W / (m*k), and the protective layer is provided with an opening corresponding to the position of each backplate electrode, and the area of ​​the backplate electrode exposed from the opening is used for bonding with the light-emitting chip; A thin-film transistor layer is located between the plurality of backplate electrodes and the first surface, and a blind hole extending toward the substrate is provided in the thin-film transistor layer adjacent to the backplate electrodes. The thin-film transistor layer includes a semiconductor layer, a patterned first metal layer, a patterned second metal layer and a patterned third metal layer sequentially disposed in the direction away from the substrate, and the third metal layer is electrically connected to the backplate electrodes. Wherein, one end of the blind hole is connected to the backplate electrode, and the other end extends from one side of the backplate electrode to the first surface; or, one end of the blind hole is located on the side of the third metal layer near the first surface and is connected to the third metal layer, and the other end extends from the side of the third metal layer away from the backplate electrode to the first surface.

2. The array substrate according to claim 1, characterized in that, The resistivity of the protective layer gradually increases along the direction from the substrate to the back electrode.

3. The array substrate according to claim 2, characterized in that, Along the direction from the substrate to the back electrode, the protective layer includes a doped protective layer and an undoped protective layer stacked sequentially; wherein, the doped protective layer includes a host material and a dopant material, and the thermal conductivity of the host material of the doped protective layer and the thermal conductivity of the undoped protective layer are greater than or equal to 400 W / (m*k).

4. The array substrate according to claim 3, characterized in that, The main material of the doped protective layer is the same as that of the undoped protective layer.

5. The array substrate according to claim 3, characterized in that, The material of the main body of the doped protective layer and the material of the undoped protective layer both include diamond-like carbon.

6. The array substrate according to claim 3, characterized in that, The doping protection layer includes a first doped sub-protection layer and a second doped sub-protection layer stacked sequentially, with the first doped sub-protection layer located between the first surface and the second doped sub-protection layer; The doping material in the first dopant protective layer includes a metal, and the doping material in the second dopant protective layer includes a non-metal.

7. The array substrate according to claim 6, characterized in that, The mass of the doped material in the first doped protective layer accounts for less than or equal to 10% of the total mass of the first doped protective layer; the mass of the doped material in the second doped protective layer accounts for less than or equal to 30% of the total mass of the second doped protective layer.

8. The array substrate according to claim 6, characterized in that, Along the direction from the substrate to the back electrode, the doping ratio of the metal in the first dopant protective layer gradually decreases; and / or, Along the direction from the substrate to the back electrode, the doping ratio of non-metals in the second dopant protective layer gradually decreases.

9. The array substrate according to claim 1, characterized in that, The semiconductor layer is located on one side of the first surface and includes multiple channel regions and a first conductor region and a second conductor region located on both sides of each channel region; The patterned first metal layer is located on the side of the semiconductor layer opposite to the first surface; The patterned second metal layer is located on the side of the first metal layer opposite to the first surface; The patterned third metal layer is located on the side of the second metal layer opposite to the first surface, and the third metal layer is provided with a first channel terminal electrically connected to the first conductive region and a second channel terminal electrically connected to the second conductive region; and the first channel terminal is electrically connected to the back plate electrode. Wherein, the blind hole extends from the side of the first passage end away from the back plate electrode to the first surface; or, the blind hole extends from the side of the back plate electrode facing the substrate to the first surface.

10. The array substrate according to claim 1, characterized in that, In the extension direction of the blind hole, the blind hole includes a first sub-blind hole and a second sub-blind hole, and a first metal layer and / or a second metal layer are disposed between the first sub-blind hole and the second sub-blind hole.

11. The array substrate according to claim 1, characterized in that, The surface of the area where the backplate electrode is exposed from the opening is provided with an uneven structure.

12. A display panel, characterized in that, include: The array substrate according to any one of claims 1-11; Multiple light-emitting chips are bonded to the backplate electrodes.

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