Signal gain adjustment circuit and method with adaptive mechanism

Abstract

This invention provides a signal gain adjustment circuit with an adaptive mechanism. An amplifier receives an analog signal and generates an adjustment analog signal, which is then sent to an analog-to-digital converter to generate an output digital signal. A gain control capacitor array and the amplifier jointly determine the gain of the adjustment analog signal relative to the analog signal. In operation, the control circuit receives the actual level of the output digital signal to determine and estimate the level offset, and generates an adjustment control signal accordingly. Each coarse-adjustment capacitor in the coarse-adjustment capacitor array has a first adjustment amount relative to the maximum gain value. Each fine-adjustment capacitor in the fine-adjustment capacitor array has a second adjustment amount, less than the first adjustment amount, relative to the maximum gain value. The coarse-adjustment and fine-adjustment capacitor arrays determine the capacitor enable combination based on the adjustment control signal, thereby adjusting the gain to reduce the offset.

Description

Technical Field

[0001] This invention relates to signal gain adjustment technology, and more particularly to a signal gain adjustment circuit and method with an adaptive mechanism. Background Technology

[0002] Analog-to-digital converters (ADCs) are crucial components that convert signals from analog to digital form. Within a certain signal range, ADCs can sample continuous signals and generate digital codes.

[0003] However, changes in ambient temperature or the generation of noise will alter the input analog signal level. For example, when the temperature rises, the input traces of the analog signal effectively become longer, causing signal attenuation. Conversely, when the temperature drops, the input traces of the analog signal effectively become shorter, amplifying the signal. Without appropriate compensation techniques, this may cause the signal to exceed the range that the analog-to-digital converter circuit can receive, leading to a decrease in system performance. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a signal gain adjustment circuit and method with an adaptive mechanism to improve the prior art.

[0005] This invention includes a signal gain adjustment circuit with an adaptive mechanism, comprising: an amplifier, a gain control capacitor array, a control circuit, a coarse adjustment capacitor array, and a fine adjustment capacitor array. The amplifier includes an input interface and an output interface to generate an adjustment analog signal at the output interface for an analog-to-digital converter circuit based on an analog signal received at the input interface. The gain control capacitor array is electrically coupled between the input and output interfaces and configured to work with the amplifier to determine the gain of the adjustment analog signal relative to the analog signal. The control circuit is configured to receive the actual level of the output digital signal of the analog-to-digital converter circuit in operating mode, determine the offset between the actual level and the estimated level, and then generate an adjustment control signal based on the offset. The coarse adjustment capacitor array includes a plurality of coarse adjustment capacitors connected in parallel with the gain control capacitor array, each having the same first adjustment amount relative to the maximum gain. The fine adjustment capacitor array includes a plurality of fine adjustment capacitors connected in parallel with the gain control capacitor array, each having the same second adjustment amount relative to the maximum gain and less than the first adjustment amount. The coarse adjustment capacitor array and the fine adjustment capacitor array determine the enable combination of the adjustment capacitors according to the adjustment control signal, thereby adjusting the gain to reduce the offset.

[0006] The present invention also includes a signal gain adjustment method with an adaptive mechanism, applied in a signal gain adjustment circuit, comprising: causing an amplifier to generate an adjustment analog signal at the output interface to the analog-to-digital converter circuit based on the analog signal received at the input interface; causing a gain control capacitor array electrically coupled between the input interface and the output interface to jointly determine the gain of the adjustment analog signal relative to the analog signal with the amplifier; causing a control circuit to receive the actual level of the output digital signal of the analog-to-digital converter circuit in the operating mode, to determine the offset between the actual level and the estimated level, and then generate an adjustment control signal based on the offset; causing a coarse adjustment capacitor array and a fine adjustment capacitor array to determine the adjustment capacitor enable combination according to the adjustment control signal, thereby adjusting the gain to reduce the offset, wherein the coarse adjustment capacitor array includes a plurality of coarse adjustment capacitors connected in parallel with the gain control capacitor array and having the same first adjustment amount relative to the maximum gain value, and the fine adjustment capacitor array includes a plurality of fine adjustment capacitors connected in parallel with the gain control capacitor array and having the same second adjustment amount relative to the maximum gain value and less than the first adjustment amount.

[0007] The features, implementation, and effects of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a signal gain adjustment circuit with an adaptive mechanism according to an embodiment of the present invention;

[0009] Figure 2 A more detailed circuit diagram of the gain control capacitor array according to an embodiment of the present invention is shown below;

[0010] Figure 3 This is a schematic diagram illustrating how a gain control capacitor, under the control of an operation control signal, generates different gain adjustment amounts, thereby causing the analog-to-digital converter circuit to generate output digital signals of different levels, according to an embodiment of the present invention.

[0011] Figure 4 A more detailed circuit diagram of the coarse-tuning capacitor array and the fine-tuning capacitor array is shown according to an embodiment of the present invention; and

[0012] Figure 5 This is a flowchart illustrating a signal gain adjustment method with an adaptive mechanism according to an embodiment of the present invention. Detailed Implementation

[0013] One object of the present invention is to provide a signal gain adjustment circuit and method with an adaptive mechanism, which, by setting coarse adjustment capacitor array and fine adjustment capacitor array, compensates for offsets caused by factors such as temperature or noise when adjusting the gain of analog signals, thereby avoiding erroneous conversion results from the analog-to-digital conversion circuit.

[0014] Please refer to Figure 1 . Figure 1 This is a block diagram of a signal gain adjustment circuit 100 with an adaptive mechanism and an analog-to-digital conversion circuit 110 according to an embodiment of the present invention.

[0015] Signal gain adjustment circuit 100 is configured to receive analog signal AN, adjust the gain of analog signal AN to generate adjusted analog signal ANA, and send it to analog-to-digital converter circuit 110. Analog-to-digital converter circuit 110 further performs analog-to-digital conversion on adjusted analog signal ANA to generate output digital signal DO.

[0016] In this embodiment, the signal gain adjustment circuit 100 has an adaptation mechanism to receive the output digital signal DO fed back by the analog-to-digital converter circuit 110 and adjust it when the actual level of the output digital signal DO deviates from the estimated level due to temperature, noise or other factors, so that the analog-to-digital converter circuit 110 can receive the adjusted analog signal ANA within the normal level range, without generating an erroneous output digital signal DO due to the deviation.

[0017] The signal gain adjustment circuit 100 includes: an amplifier 120, a gain control capacitor array 130, a control circuit 140, a coarse adjustment capacitor array 150, and a fine adjustment capacitor array 160.

[0018] Amplifier 120 includes an input interface and an output interface to generate an adjusted analog signal ANA at the output interface based on the analog signal AN received at the input interface.

[0019] In this embodiment, amplifier 120 is an operational amplifier with an input interface including a non-inverting input terminal (marked with a "+" sign in the figure) and an inverting input terminal (marked with a "-" sign in the figure), and an output interface including an output terminal (marked with a "0" sign in the figure). In one embodiment, amplifier 120 receives an analog signal AN through the non-inverting input terminal and generates an adjustment analog signal ANA at the output terminal.

[0020] A gain control capacitor array 130 is electrically coupled between the input and output interfaces and configured to work with amplifier 120 to determine the gain of analog signal ANA relative to analog signal AN. In this embodiment, the gain control capacitor array 130 is electrically coupled between the inverting input and the output. However, the invention is not limited thereto.

[0021] Please refer to Figure 2 . Figure 2 A more detailed circuit diagram of the gain control capacitor array 130 according to an embodiment of the present invention is shown below.

[0022] In one embodiment, the gain control capacitor array 130 includes a basic gain capacitor Cg0 connected in parallel and a plurality of gain control capacitors Cg1 to Cg4. The basic gain capacitor Cg0 is continuously enabled, while the gain control capacitors Cg2 to Cg42 are enabled or disabled by, for example, but not limited to, a switching circuit 200.

[0023] The capacitance values ​​of the gain control capacitors Cg1 to Cg4 can be configured to have multiple weighted binary adjustment amounts relative to the maximum gain. More specifically, the adjustment amounts of the gain control capacitors Cg2 to Cg4 relative to the maximum gain are 2 times, 4 times, and 8 times, respectively, the adjustment amount of the gain control capacitor Cg1 relative to the maximum gain.

[0024] In one embodiment, if 100% represents the maximum gain that the gain control capacitor array 130 can achieve, the adjustment amount of the basic gain capacitor Cg0 relative to the maximum gain can be configured to 25%, and the adjustment amounts of the gain control capacitors Cg1 to Cg4 relative to the maximum gain can be configured to 5%, 10%, 20%, and 40%, respectively.

[0025] The control circuit 140 is configured to generate an operation control signal OC, so that the gain control capacitor array 130 determines the gain capacitor enable combination according to the operation control signal OC.

[0026] Please refer to Figure 3 . Figure 3 This is a schematic diagram illustrating how gain control capacitors Cg1 to Cg4, under the control of the operation control signal OC, generate different gain adjustment amounts, thereby causing the analog-to-digital converter circuit 110 to generate output digital signals DO at different levels.

[0027] Since the number of gain control capacitors Cg1 to Cg4 is four, the operation control signal OC can be controlled in a four-bit form. Therefore, as Figure 3 As shown, the horizontal axis represents the operation control signal OC represented by four bits, and the vertical axis represents the corresponding gain.

[0028] When the basic gain capacitor Cg0 is continuously enabled, the gain control capacitors Cg1 to Cg4 can generate different enable combinations according to the operation control signal OC of (0000), (0001), (0010), ... (1111), and achieve 25% to 100% of the maximum relative gain, resulting in a total of 16 (24) different gain setting results.

[0029] It should be noted that the architecture of the gain control capacitor array 130 described above is only an example. In other embodiments, the gain control capacitor array 130 may also be implemented with other architectures.

[0030] In actual operation, the control circuit 140 is configured to generate an operation control signal OC based on the transmission line length between the signal gain adjustment circuit 100 and the analog-to-digital conversion circuit 110 in the initial mode of the system, so that the gain control capacitor array 130 determines the gain capacitor enable combination according to the operation control signal OC.

[0031] Furthermore, the gain control capacitor array 130 will operate in the operating mode according to the gain capacitor enable combination, and will not change thereafter. This gain capacitor enable combination will allow amplifier 120 to determine and adjust the gain of analog signal ANA relative to analog signal AN.

[0032] However, the capacitance values ​​of the gain control capacitor array 130 can change due to temperature or noise, thus affecting the adjustment amount of these capacitors relative to the maximum gain. Therefore, the control circuit 140 can determine the enable combination of the adjustment capacitors of the coarse adjustment capacitor array 150 and the fine adjustment capacitor array 160 through the feedback output digital signal DO to achieve the compensation effect.

[0033] Please refer to Figure 4 . Figure 4 A more detailed circuit diagram of the coarse adjustment capacitor array 150 and the fine adjustment capacitor array 160 according to an embodiment of the present invention is shown below.

[0034] The coarse adjustment capacitor array 150 includes a plurality of coarse adjustment capacitors Cc1 to Cc4 connected in parallel with the gain control capacitor array 130, and each has the same first adjustment amount relative to the maximum gain. In one embodiment, the first adjustment amount of each coarse adjustment capacitor Cc1 to Cc4 relative to the maximum gain may be equivalent to the adjustment amount of the gain control capacitor Cg1 relative to the maximum gain, which is 5% of the maximum gain.

[0035] The coarse adjustment capacitors Cc1 to Cc2 are configured to be enabled in the system initial mode, thereby reducing the gain when the capacitors are suppressed in the operating mode. On the other hand, the coarse adjustment capacitors Cc3 to Cc4 are configured to be preset to suppress the gain in the system initial mode, thereby increasing the gain when the capacitors are enabled in the operating mode. Therefore, in the operating mode, the coarse adjustment capacitors Cc1 to Cc4 can be configured to either increase or decrease the gain.

[0036] The fine-tuning capacitor array 160 includes a plurality of fine-tuning capacitors Cd1 to Cd12 connected in parallel with the gain control capacitor array, and each capacitor has a second adjustment amount that is the same as the first adjustment amount and is less than the maximum gain value. In one embodiment, the fine-tuning capacitor array 160 includes first fine-tuning capacitors Cd1 to Cd10 and second fine-tuning capacitors Cd11 to Cd12.

[0037] When all the first fine-tuning capacitors Cd1 to Cd10 are fully enabled, the first total adjustment amount is equivalent to the first adjustment amount of each coarse-tuning capacitor Cc1 to Cc4 relative to the maximum gain. In this embodiment, the second adjustment amount of each of the first fine-tuning capacitors Cd1 to Cd10 relative to the maximum gain will therefore be 1 / 10 of the first adjustment amount, that is, 0.5% of the maximum gain.

[0038] The second total adjustment amount of the second fine-tuning capacitors Cd11 to Cd12 when fully enabled is equivalent to the process offset adjustment amount of the first adjustment amount corresponding to each coarse-tuning capacitor Cc1 to Cc4. In one embodiment, if the effect of the process offset pair is 20%, the required process offset adjustment amount will be 1% of the maximum gain (20% of 5% of the maximum gain). Therefore, it is necessary to provide two second fine-tuning capacitors Cd11 to Cd12 with a second adjustment amount (0.5% of the maximum gain).

[0039] The coarse adjustment capacitors Cc1 to Cc4 and the fine adjustment capacitors Cd1 to Cd12 mentioned above can be enabled or disabled by, for example, but not limited to, switching circuit 300 and switching circuit 310. By different enabling combinations, the coarse adjustment capacitors Cc1 to Cc4 and the fine adjustment capacitors Cd1 to Cd12 can achieve different gain adjustment results.

[0040] It should be noted that, in order to achieve a linear cumulative adjustment result, the coarse adjustment capacitors Cc1 to Cc4 and the fine adjustment capacitors Cd1 to Cd12 need to be enabled sequentially to accumulate the adjustment amount, unlike the capacitors in the gain control capacitor array 130, which can be arbitrarily selected according to the requirements.

[0041] It should be noted that the architecture of the coarse-adjustment capacitor array 150 and the fine-adjustment capacitor array 160 described above is only an example. In other embodiments, adjusting the coarse-adjustment capacitor array 150 and the fine-adjustment capacitor array 160 can also be implemented using other architectures.

[0042] In actual operation, the control circuit 140 is configured to, in calibration mode, determine multiple enable combinations of multiple adjustment amounts within a preset adjustment range corresponding to the coarse adjustment capacitors Cc1 to Cc4 and the fine adjustment capacitors Cd1 to Cd12. For example, in calibration mode, the control circuit 140 can, for an adjustment range of -10% to +10%, control the coarse adjustment capacitor array 150 and the fine adjustment capacitor array 160 through the switching circuits 300 and 310 to find all enable combinations corresponding to the adjustment amounts within this range.

[0043] In one example, corresponding to the adjustment range (0-10%) that makes the gain unadjusted or increased, the control circuit 140 can find, for example, but not limited to, all of the coarse adjustment capacitors Cc1-Cc4 and the fine adjustment capacitors Cd1-Cd12 suppressed, the fine adjustment capacitors Cd1 to Cd9 enabled one by one, the coarse adjustment capacitor Cc3 enabled only, the coarse adjustment capacitor Cc3 enabled and the fine adjustment capacitors Cd1 to Cd10 enabled one by one, the coarse adjustment capacitors Cc3 and Cc4 enabled only, and the coarse adjustment capacitors Cc3 and Cc4 enabled and the fine adjustment capacitors Cd1 to Cd11 enabled one by one.

[0044] Corresponding to the adjustment range (-10% to 0%) that reduces the gain, the control circuit 140 can find, for example, but not limited to, enabling only the coarse adjustment capacitor Cc2, enabling the coarse adjustment capacitor Cc2 and enabling the fine adjustment capacitors Cd1 to Cd8 one by one, and enabling only the coarse adjustment capacitors Cc2 and Cc1.

[0045] In such an example, corresponding to an adjustment range of -10% to +10%, the control circuit 140 can identify 41 different combinations of enable values ​​for the adjustment amount.

[0046] It should be noted that the adjustment range described above is only an example; in other embodiments, the control circuit 140 may be set with different adjustment ranges as needed. Furthermore, the enable combination determined by the control circuit 140 is only an example. In other embodiments, the number and arrangement of enable combinations may vary depending on the size of the adjustment range and the actual adjustment amount caused by process deviations in the coarse and fine adjustment capacitors.

[0047] Control circuit 140 is configured to receive the actual level of the output digital signal DO of analog-to-digital converter circuit 110 in operating mode, determine the offset between the actual level and the estimated level, and then generate an adjustment control signal AC based on the offset. In one embodiment, control circuit 140 may determine the estimated level based on empirical values ​​of the magnitude of analog signal AN, and determine the offset based on the maximum value difference or average power difference between the actual level and the estimated level.

[0048] In one embodiment, the control circuit 140 can store the correspondence between adjustment amounts and enable combinations in a lookup table in a memory (not shown) included in the signal gain adjustment circuit 100. After obtaining the aforementioned offset information, it calculates the adjustment amount required to compensate for the offset, and retrieves the corresponding enable combination from the lookup table based on the adjustment amount to generate an adjustment control signal AC. Therefore, the coarse adjustment capacitor array 150 and the fine adjustment capacitor array 160 will determine the adjustment capacitor enable combination based on the adjustment control signal AC, thereby adjusting the gain to reduce the offset.

[0049] Therefore, the signal gain adjustment circuit of the present invention can compensate for offsets caused by factors such as temperature or noise when adjusting the gain of analog signals by setting coarse adjustment capacitor array and fine adjustment capacitor array, thereby avoiding erroneous conversion results from the analog-to-digital conversion circuit.

[0050] Please refer to the following at the same time Figure 5 . Figure 5 This is a flowchart illustrating a signal gain adjustment method 500 with an adaptive mechanism according to an embodiment of the present invention.

[0051] In addition to the aforementioned apparatus, the present invention also discloses a signal gain adjustment method 400, applicable to, for example, but not limited to, [various applications]. Figure 1 In the signal gain adjustment circuit 100. An embodiment of the signal gain adjustment method 500 is, for example... Figure 5 As shown, it includes the following steps:

[0052] Step S510: Amplifier 120 generates an adjustment analog signal ANA at the output interface based on the analog signal AN received at the input interface, and sends it to analog-to-digital converter circuit 110.

[0053] Step S520: The gain control capacitor array 130 electrically coupled between the input interface and the output interface and the amplifier 120 jointly determine the gain of the analog signal ANA relative to the analog signal AN.

[0054] Step S530: In the operating mode, the control circuit 140 receives the actual level of the output digital signal DO from the analog-to-digital converter circuit 110 to determine the offset between the actual level and the estimated level, and then generates an adjustment control signal AC based on the offset.

[0055] Step S540: The coarse adjustment capacitor array 150 and the fine adjustment capacitor array 160 determine the adjustment capacitor enable combination according to the adjustment control signal AC, thereby adjusting the gain to reduce the offset.

[0056] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications and variations without departing from the spirit of the invention.

[0057] In summary, the signal gain adjustment circuit and method with an adaptive mechanism in this invention can compensate for offsets caused by factors such as temperature or noise when adjusting the gain of analog signals by setting coarse adjustment capacitor arrays and fine adjustment capacitor arrays, thereby avoiding erroneous conversion results from the analog-to-digital conversion circuit.

[0058] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and these changes still fall within the scope of patent protection claimed by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of the present invention.

[0059] Explanation of reference numerals in the attached figures:

[0060] 100: Signal gain adjustment circuit

[0061] 110: Analog-to-digital converter circuit

[0062] 120: Amplifier

[0063] 130: Gain-controlled capacitor array

[0064] 140: Control Circuit

[0065] 150: Coarse-tuning capacitor array

[0066] 160: Fine-tuning capacitor array

[0067] 200: Switching circuit

[0068] 300, 310: Switching circuit

[0069] 500: Signal Gain Adjustment Method

[0070] S510~S540: Steps

[0071] AC: Adjust control signal

[0072] AN: Analog signal

[0073] ANA: Adjust analog signal

[0074] DO: Output digital signal

[0075] Cc1~Cc4: Coarse adjustment capacitors

[0076] Cd1~Cd12: Fine-tuning capacitors

[0077] Cg0: Basic gain capacitor

[0078] Cg1~Cg4: Gain control capacitors

[0079] OC: Operation control signal

Claims

1. A signal gain adjustment circuit with an adaptive mechanism, comprising: An amplifier includes an input interface and an output interface, for generating an adjustment analog signal at the output interface to an analog-to-digital converter circuit based on an analog signal received at the input interface. A gain control capacitor array, electrically coupled between the input interface and the output interface, is configured to work with the amplifier to determine a gain of the adjusted analog signal relative to the analog signal. A control circuit is configured to receive an actual level of an output digital signal of the analog-to-digital converter circuit in an operating mode, determine an offset of the actual level from an estimated level, and then generate an adjustment control signal based on the offset. A coarse adjustment capacitor array includes a plurality of coarse adjustment capacitors connected in parallel with the gain control capacitor array, and each has the same first adjustment amount relative to a maximum gain value of the gain. A fine-tuning capacitor array includes a plurality of fine-tuning capacitors connected in parallel with the gain control capacitor array, and has a second adjustment amount that is the same as each other and less than the first adjustment amount relative to the maximum gain value; The coarse-adjustment capacitor array and the fine-adjustment capacitor array determine an adjustment capacitor enable combination according to the adjustment control signal, thereby adjusting the gain to reduce the offset.

2. The signal gain adjustment circuit according to claim 1, characterized in that, The control circuit is further configured to, in a calibration mode, determine that the plurality of coarse adjustment capacitors and the plurality of fine adjustment capacitors correspond to a plurality of enable combinations of a plurality of adjustment amounts within a preset adjustment range, thereby further selecting one of the plurality of enable combinations based on the offset amount in the operating mode and generating the control signal accordingly.

3. The signal gain adjustment circuit according to claim 1, characterized in that, The gain control capacitor array includes multiple gain control capacitors connected in parallel and having multiple weighted binary adjustments relative to the maximum gain value; The control circuit is also configured to generate an operation control signal based on a transmission line length between the signal gain adjustment circuit and the analog-to-digital conversion circuit in a system initial mode, so that the gain control capacitor array determines a gain capacitor enable combination according to the operation control signal, and operates according to the gain capacitor enable combination in the operation mode.

4. The signal gain adjustment circuit according to claim 1, characterized in that, The offset is determined by a maximum difference or an average power difference between the actual level and the estimated level.

5. The signal gain adjustment circuit according to claim 1, characterized in that, The plurality of coarse adjustment capacitors further include: a plurality of first coarse adjustment capacitors configured to be enabled in a system initial mode to reduce the gain when the adjustment capacitors are enabled to suppress the operation mode; and Multiple second coarse adjustment capacitors are configured to be preset to suppress power in the initial mode of the system, and to increase the gain when the adjustment capacitors are enabled according to the combination of adjustment capacitors in the operating mode.

6. The signal gain adjustment circuit according to claim 1, characterized in that, The plurality of trimming capacitors further includes: a plurality of first trimming capacitors, wherein a first total adjustment amount when fully enabled is equivalent to the first adjustment amount; and Multiple second fine-tuning capacitors, when fully enabled, have a second total adjustment amount equivalent to a process offset adjustment amount corresponding to the first adjustment amount of each of the multiple coarse-tuning capacitors.

7. A signal gain adjustment method with an adaptive mechanism, applied to a signal gain adjustment circuit, comprising: An amplifier generates an adjustment analog signal at an output interface based on an analog signal received at an input interface, which is then sent to an analog-to-digital converter circuit. An array of gain-controlled capacitors electrically coupled between the input interface and the output interface, together with the amplifier, determines the gain of the adjusted analog signal relative to the analog signal. In an operating mode, a control circuit receives an actual level of an output digital signal from the analog-to-digital converter circuit, determines an offset between the actual level and an estimated level, and then generates an adjustment control signal based on the offset. A coarse-adjustment capacitor array and a fine-adjustment capacitor array determine an adjustment capacitor enable combination according to the adjustment control signal, thereby adjusting the gain to reduce the offset. The coarse-adjustment capacitor array includes a plurality of coarse-adjustment capacitors connected in parallel with the gain control capacitor array and has a first adjustment amount that is the same as each other relative to a maximum gain value of the gain. The fine-adjustment capacitor array includes a plurality of fine-adjustment capacitors connected in parallel with the gain control capacitor array and has a second adjustment amount that is the same as each other relative to the maximum gain value and is less than the first adjustment amount.

8. The signal gain adjustment method according to claim 7, characterized in that, Also includes: In a calibration mode, the control circuit determines that the plurality of coarse adjustment capacitors and the plurality of fine adjustment capacitors correspond to a plurality of enable combinations of a plurality of adjustment amounts within a preset adjustment range, and further selects one of the plurality of enable combinations based on the offset amount in the operating mode and generates the control signal accordingly.

9. The signal gain adjustment method according to claim 7, characterized in that, The gain control capacitor array includes multiple gain control capacitors connected in parallel and having multiple weighted binary adjustment values ​​relative to the maximum gain. The signal gain adjustment method further includes: In a system initial mode, the control circuit generates an operation control signal to the gain control capacitor array based on the transmission line length between the signal gain adjustment circuit and the analog-to-digital conversion circuit to determine a gain capacitor enable combination, and in the operation mode, the gain control capacitor array operates according to the gain capacitor enable combination.

10. The signal gain adjustment method according to claim 9, characterized in that, Also includes: The plurality of coarse adjustment capacitors, including a plurality of first coarse adjustment capacitors, are enabled in a system initial mode to reduce the gain when the adjustment capacitors are suppressed according to the enabled combination in the operating mode; and The plurality of coarse adjustment capacitors, including the plurality of second coarse adjustment capacitors, are preset to be suppressed in the initial mode of the system, so that when the adjustment capacitors are enabled in the operating mode, the gain is increased.

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