An AES key processing circuit and method

Abstract

The present invention discloses an AES key processing circuit and method. During the data encryption or decryption process, the AES key processing circuit performs one round of key refreshing and updates the key in the key register with the key after each refreshing until the key refreshing times reach a preset number; wherein, the key register only stores the current key. Compared with the prior art, in the process of one-round key refreshing of this technical solution, only the current key is stored, thus saving a large number of storage units, greatly reducing the area of the AES key processing circuit, and being beneficial to cost reduction.

Description

Technical Field

[0001] The present invention relates to the technical field of cryptographic circuits, and particularly to an AES key processing circuit and method. Background Art

[0002] As an encryption method, the AES (Advanced Encryption Standard) is widely used in general MCUs. Especially for MCUs that focus on cost performance, it is necessary to minimize the area of each module on the premise that the circuit can work at the required operating frequency, so as to control the cost price of the MCU and improve its market competitiveness.

[0003] In a traditional AES key processing circuit, storage units such as registers or SRAMs are used. Before data encryption and decryption, the corresponding keys for each round are pre-refreshed and then stored in the storage unit in sequence. During the subsequent encryption and decryption processes, the key corresponding to the current round is addressed and read from the storage unit. Taking the data bit width to be encrypted and decrypted as 128 bits and the key length also as 128 bits as an example, a total of 11 rounds of data encryption and 11 rounds of data decryption need to be performed, and 11 groups of keys with each group having a length of 128 bits are required. Therefore, before performing data encryption and decryption operations, the CPU will first send a key_start signal to notify the AES module to perform key operations and write the 11-round keys into the storage unit in sequence, which altogether requires 11×128 bits = 1408 bits of storage unit. Obviously, the traditional AES key processing circuit requires more storage units, which is not conducive to cost reduction. Summary of the Invention

[0004] To solve the above problems, the present invention provides an AES key processing circuit and method, which greatly reduces the area of the AES key processing circuit. The specific technical solutions of the present invention are as follows:

[0005] An AES key processing circuit, the AES key processing circuit comprising: a key pre-refresh control state machine module for generating a key pre-refresh enable to control a key transformation module to perform key pre-refresh and outputting a key pre-refresh completion interrupt signal after the key pre-refresh is completed; a first OR gate connected to the key pre-refresh control state machine module for performing an OR operation on the key pre-refresh enable and a key refresh enable configured by an external module; a key transformation module connected to the first OR gate for key refresh to update the key in the key register; a data selector connected to the key transformation module for selecting a corresponding key according to a data selection signal and transmitting it to the key register; and a key register connected to the data selector for storing the current key. Compared with the prior art, the present technical solution uses the key transformation module to refresh the key required in the encryption and decryption processes and updates the key in the key register with the refreshed key. Since only the current key is stored, a large number of storage units are saved, greatly reducing the area of the AES key processing circuit and facilitating cost reduction.

[0006] Further, the key transformation module includes a key forward transformation module and a key inverse transformation module. Among them, the key forward transformation module is connected to the first OR gate and is used to receive the key pre-refresh enable or the key refresh enable and perform one round of key forward transformation during the data encryption process and the key pre-refresh process; the key inverse transformation module is used to receive the key refresh enable to perform one round of key inverse transformation during the data decryption process. This enables the key to be refreshed back and forth in the same key register, saving redundant storage units.

[0007] Further, the data selector includes a first data selector and a second data selector. Among them, the first data selector is connected to the key forward transformation module and the key inverse transformation module and is used to receive the output of the key forward transformation module, the output of the key inverse transformation module, and the AES direction configured by the external module, and select the output of the key forward transformation module or the key inverse transformation module as the input of the second data selector according to the AES direction; the second data selector is connected to the first data selector and is used to receive the output of the first data selector, the initial key configured by the external module, and the initial key configuration completion signal configured by the external module, and select the output of the first selector or the initial key as the input of the key register according to the initial key configuration completion signal; wherein the AES direction includes a data encryption direction and a data decryption direction.

[0008] Further, the processing circuit further includes a second OR gate connected to the key pre-refresh control state machine module for receiving the initial key configuration completion signal input by the external module and the key pre-refresh completion interrupt signal output by the key pre-refresh control state machine module, and performing an OR operation on the initial key configuration completion signal and the key pre-refresh completion interrupt signal to generate a key register write enable to control the writing of the key register.

[0009] Further, the key pre - refresh control state machine module includes a state machine and a counter; the state machine is used to control the counter to count the number of pulses of the key pre - refresh enable.

[0010] An AES key processing method, the AES key processing method includes: during the data encryption or decryption process, the AES key processing circuit performs one round of key refresh on the key, and updates the key in the key register with the key after each refresh until the number of key refresh times reaches a preset number; wherein, the key register only stores the current key. Compared with the prior art, in the process of one - round key refresh of this technical solution, only the current key is stored, thus saving a large number of storage units, greatly reducing the area of the AES key processing circuit, and being beneficial to cost reduction.

[0011] Further, before the start of the data encryption or decryption process, the AES key processing circuit updates the key in the key register to the initial key according to the AES module enable and the initial key configuration completion signal.

[0012] Further, if the AES direction of the AES key processing circuit is configured as the data encryption direction, a forward key transformation is performed on the key, and the forward key transformation means sequentially refreshing the initial key in the key register to the final key; if the AES direction of the AES key processing circuit is configured as the data decryption direction, a reverse key transformation is performed on the key, and the reverse key transformation means sequentially refreshing the final key in the key register to the initial key. Based on the forward and reverse transformations of the key, the key can be refreshed back and forth in the same key register, saving redundant storage units.

[0013] Further, if the AES direction of the AES key processing circuit is configured as the data decryption direction, after refreshing the key in the key register to the initial key, the AES key processing circuit performs key pre - refresh according to the key pre - refresh enable signal generated by the key pre - refresh control state machine module; the key pre - refresh means performing a forward transformation on the key in the key register before the data decryption process to update the key in the key register to the final key. Description of the Drawings

[0014] Figure 1 Is the AES module.

[0015] Figure 2 Is the AES key processing circuit according to an embodiment of the present invention.

[0016] Figure 3 Is the flowchart of the AES key processing method according to an embodiment of the present invention. Detailed Embodiments

[0017] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described below are only used to explain the present invention and are not used to limit the present invention.

[0018] In the following description, specific details are given to provide a thorough understanding of the embodiments. However, those of ordinary skill in the art will understand that the embodiments can be implemented without these specific details. For example, the circuit can be shown in a block diagram so as not to obscure the embodiments with unnecessary details. In other cases, well-known circuits, structures, and technologies may not be shown in detail so as not to confuse the embodiments.

[0019] After each key refresh, the traditional AES key processing circuit stores each key in the storage unit, resulting in a large demand for storage units and high costs. Therefore, the present invention provides an AES key processing circuit to solve the above problems. Before introducing the circuit, the AES module will be introduced first to help understand the present invention.

[0020] As Figure 1 shown, the AES module includes a bus interface module, an input buffer FIFO module, an output buffer FIFO module, a data flow control module, a data encryption / decryption transformation module, and a key processing module. Among them, the bus interface module receives the data to be encrypted / decrypted, and through the input buffer FIFO module and the data flow control module, gives it to the data encryption / decryption transformation module for encryption or decryption. The encryption or decryption process of the data requires the key generated by the key processing module to be realized. The AES key processing circuit provided by the present invention is an optimization of the key processing module. The structure and function of the AES key processing circuit will be introduced below.

[0021] As Figure 2 shown, an AES key processing circuit provided by an embodiment of the present invention, the processing circuit includes:

[0022] A key pre-refresh control state machine module, which is used to generate a key pre-refresh enable to control the key transformation module to perform key pre-refresh, and output a key pre-refresh completion interrupt signal after the key pre-refresh is completed. The key pre-refresh control state machine module consists of a state machine and a counter. The state machine is a commonly used control center in digital circuits for completing specific operations. The state machine includes 3 states:

[0023] S0: Wait for the arrival of the key start pre-refresh signal configured by the CPU, and jump to S1 after the signal arrives;

[0024] S1: Send the key pre - refresh enable signal and control the counter to count its pulse number. When the pulse number of the key pre - refresh enable reaches the preset value (taking the AES process with the data bit - width to be encrypted / decrypted as 128 bits and the key length as 128 bits as an example, 10 key pre - refresh enable pulses need to be generated), stop sending the key pre - refresh enable signal and jump to S2;

[0025] S2: Send out the key pre - refresh completion interrupt signal, clear the counter value, and return to the S0 state. It should be noted that at this time, the key in the key register is refreshed to the final key, and only when the AES direction is configured as the data decryption direction, will the key start pre - refresh signal input from the external module be received.

[0026] The first OR gate is connected to the key pre - refresh control state machine module and performs an OR operation on the key pre - refresh enable signal and the key refresh enable signal configured by the external module. Among them, the key refresh enable signal comes from Figure 1 the data encryption / decryption transformation module shown in

[0027] The key transformation module includes a forward key transformation module and a reverse key transformation module; among them, the forward key transformation module is connected to the first OR gate and is used to receive the key pre - refresh enable signal or the key refresh enable signal and perform one - round forward key transformation during the data encryption process and the key pre - refresh process; the reverse key transformation module is used to receive the key refresh enable signal to perform one - round reverse key transformation during the data decryption process. Both the forward key transformation module and the reverse key transformation module are composed of an sbox transformation circuit, an XOR gate, and an rcon parameter transformation circuit, and these circuits are used to implement key operations and are prior arts.

[0028] The data selector includes a first data selector and a second data selector; among them, the first data selector is connected to the forward key transformation module and the reverse key transformation module and is used to receive the output of the forward key transformation module, the output of the reverse key transformation module, and the AES direction configured by the external module, and select the output of the forward key transformation module or the reverse key transformation module as the input of the second data selector according to the AES direction; the second data selector is connected to the first data selector and is used to receive the output of the first data selector, the initial key configured by the external module, and the initial key configuration completion signal configured by the external module, and select the output of the first selector or the initial key as the input of the key register according to the initial key configuration completion signal; among them, the AES direction includes the data encryption direction and the data decryption direction. Among them, both the initial key and the initial key configuration completion signal are configured by the CPU. After the CPU configures the initial key, an initial key configuration completion signal will be generated to notify the AES key processing circuit to perform corresponding operations.

[0029] The key register is connected to the second data selector and is used to store the current key. Each time the key register obtains a refreshed key, it transmits the key to Figure 1 the data encryption / decryption transformation module shown in Figure 1 to encrypt or decrypt the data. Additionally, when the key forward transformation module and the key reverse transformation module need to refresh the key, they also read the current key from the key register.

[0030] The second OR gate is connected to the key pre-refresh control state machine module and is used to receive the initial key configuration completion signal input by the external module and the key pre-refresh completion interrupt signal output by the key pre-refresh control state machine module, and perform an OR operation on the initial key configuration completion signal and the key pre-refresh completion interrupt signal to generate a key register write enable to control the writing of the key register. When the second OR gate receives the initial key configuration completion signal, the key register write enable controls the key register to write the initial key configured by the CPU. When the second OR gate receives the key pre-refresh completion interrupt signal, the key register write enable controls the key register to write the final key output by the key forward transformation module.

[0031] Compared with the prior art, the present AES key processing circuit uses a key transformation module to refresh the key required in the encryption / decryption process, and updates the key in the key register with the refreshed key. Since only the current key is stored, a large number of storage units are saved, greatly reducing the area of the AES key processing circuit and facilitating cost reduction.

[0032] As Figure 3 shown, an AES key processing method, the processing method includes: during the data encryption or decryption process, the AES key processing circuit performs one round of key refresh, and updates the key in the key register with the key after each refresh until the key refresh times reach the preset number; wherein, the key register only stores the current key.

[0033] It should be noted that one round of key refresh refers to one round of key forward transformation or one round of key reverse transformation. Taking the AES encryption / decryption process with the data bit width to be encrypted or decrypted being 128bit and the key length also being 128bit as an example, the encryption or decryption needs to go through 10 key transformations from round0 to round10, and there are 11 groups of keys from key0 to key10. Among them, key0 is called the initial key, and key10 is called the final key; assuming that the encryption or decryption is now in round3, then key3 is called the current key, and the current key is stored in the key register. In this example, one round of key transformation (one round of key forward transformation or one round of key reverse transformation) includes 10 key transformations, and the following will also be described by taking this as an example.

[0034] Before the start of the data encryption or decryption process, the AES key processing circuit updates the key in the key register to the initial key key0 according to the AES module enable (the operating enable of the AES module, not shown in the figure) and the initial key configuration completion signal. The initial key key0 is directly configured by the CPU. When the AES module enable is turned on and the initial key configuration completion signal arrives, the AES key processing circuit updates the key in the key register to the initial key value key0.

[0035] After making preparations for encryption and decryption, the AES key processing circuit needs to determine whether the current process is encryption or decryption to execute the corresponding method. If the AES direction of the AES key processing circuit is configured as the data encryption direction, a forward key transformation is performed on the key, and the value in the key register is dynamically refreshed. The forward key transformation refers to refreshing the initial key to the final key in sequence, that is, refreshing from key0 to key1, then to key2, until key10; if the AES direction of the AES key processing circuit is configured as the data decryption direction, an inverse key transformation is performed on the key. The inverse key transformation refers to refreshing the final key to the initial key in sequence, that is, refreshing from key10 to key9, then to key8, until key0.

[0036] Among them, the transformation method of the forward key transformation is as follows:

[0037] w0_nxt = sbox[rot(w3)] ^ w0 ^ rcon;

[0038] w1_nxt = w1 ^ w0_nxt;

[0039] w2_nxt = w2 ^ w1_nxt;

[0040] w3_nxt = w3 ^ w2_nxt;

[0041] Among them, w0, w1, w2, and w3 form the key key before the forward transformation. As can be seen from the foregoing, each key from key0 to key10 is 128-bit data. Therefore, w0, w1, w2, and w3 are all 32-bit, and w0[31:0]=key[127:96], w1[31:0]=key[95:64], w2[31:0]=key[63:32], w3[31:0]=key[31:0];

[0042] The sbox operation adopts the look-up table method or the transformation method. Preferably, the transformation method is adopted in this embodiment;

[0043] rot(w3) represents swapping the high 8 bits and the low 24 bits of w3, that is, rot(w3) = {w3[23:0], w3[31:24]};

[0044] The ^ symbol represents the exclusive OR operation;

[0045] rcon is a variable parameter used to generate w0_nxt. The AES specification stipulates that 10 forward transformations are required during the encryption process, and the rcon values are: 32’h100_0000, 32’h200_0000, 32’h400_0000, 32’h800_0000, 32’h1000_0000, 32’h2000_0000, 32’h4000_0000, 32’h8000_0000, 32’h1b00_0000, 32’h3600_0000;

[0046] w0_nxt, w1_nxt, w2_nxt, and w3_nxt form the key key_nxt after the forward transformation, and w0_nxt[31:0] = key_nxt[127:96], w1_nxt[31:0] = key_nxt[95:64], w2_nxt[31:0] = key_nxt[63:32], w3_nxt[31:0] = key_nxt[31:0].

[0047] The transformation method of the inverse transformation is as follows:

[0048] w0_nxt = sbox[rot(w3 ^ w2)] ^ w0 ^ rcon;

[0049] w1_nxt = w1 ^ w0;

[0050] w2_nxt = w2 ^ w1;

[0051] w3_nxt = w3 ^ w2;

[0052] Among them, w0, w1, w2, and w3 form the key key before the inverse transformation;

[0053] rcon is a variable parameter used to generate w0_nxt. The AES specification stipulates that 10 inverse transformations are required during the decryption process, and the rcon values are: 32’h3600_0000, 32’h1b00_0000, 32’h8000_0000, 32’h4000_0000, 32’h2000_0000, 32’h1000_0000, 32’h1000_0000, 32’h400_0000, 32’h200_0000, 32’h100_0000.

[0054] Based on the forward and inverse transformation of the key, the key can be refreshed back and forth in the same key register, saving redundant storage units. The size of the key register is equal to the size of a key key. In this embodiment, the size of the key register is 128 bits. It should be noted that after each key refresh, the key register transmits the latest key to Figure 1 the data encryption / decryption transformation module shown in it for data encryption or decryption, and then waits for the key refresh enable of the data encryption / decryption transformation module to continue the next refresh of the key until the key refresh count reaches the preset number of times. The key refresh count is obtained by the counter of the key pre-refresh control state machine module counting the key refresh enable.

[0055] It should be noted that if the AES direction of the AES key processing circuit is configured as the data decryption direction, after refreshing the key in the key register to the initial key, the AES key processing circuit performs key pre-refresh according to the key pre-refresh enable signal. The key pre-refresh refers to performing a round of forward transformation on the key before data decryption to update the key in the key register to the final key, otherwise the so-called key inverse transformation cannot be achieved. Preferably, during the key pre-refresh process, after completing a round of complete forward transformation, the key in the key register is directly updated to the final key without updating the key in the intermediate process. When the AES direction of the AES key processing circuit is configured as the data encryption direction, key pre-refresh is not required.

[0056] During the execution of a round of key transformation, the key is refreshed only when the key refresh enable is valid. If it is in the encryption direction, the key register is updated with the key after one forward transformation; if it is in the decryption direction, the key register is updated with the key after one key inverse transformation. After one key transformation, it is judged whether the current refresh count reaches the preset number of times (for example, when the key length is 128 bits, the preset number of times is 10). If the preset number of times is reached, it means that a round of complete data encryption or decryption has been completed, and a round of complete key forward transformation or inverse transformation has also been completed, and it returns to wait for the CPU to configure the initial key. If the current key refresh count does not reach the preset number of times, it waits for the key refresh enable of the data encryption / decryption transformation module to arrive.

[0057] Compared with the prior art, in a round of key refresh process of this AES key processing method, only the current key is stored, thus saving a large number of storage units, greatly reducing the area of the AES key processing circuit, and being beneficial to cost reduction.

[0058] Obviously, the above embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and the technical solutions between the various embodiments can be combined with each other. In addition, if terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear in the embodiments, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, so it cannot be understood as a limitation to the present invention. If terms such as "first", "second", "third", etc. appear in the embodiments, they are for the convenience of distinguishing related features and cannot be understood as indicating or implying their relative importance, the order of precedence, or the number of technical features.

[0059] In addition, in the description of the present invention, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0060] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. These programs can be stored in a computer-readable storage medium (such as various media that can store program codes, such as ROM, RAM, magnetic disks, or optical discs). When the program is executed, it executes the steps including the above method embodiments.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An AES key processing circuit, characterized in that, The AES key processing circuit includes: A key pre-refresh control state machine module, which is used to generate a key pre-refresh enable to control the key transformation module to perform key pre-refresh, and output a key pre-refresh completion interrupt signal after the key pre-refresh is completed; A first OR gate, connected to the key pre-refresh control state machine module, for performing an OR operation on the key pre-refresh enable and the key refresh enable configured by an external module; A key transformation module, connected to the first OR gate, which is used for key refresh to update the key in the key register; A data selector, connected to the key transformation module, which selects a corresponding key according to a data selection signal and transmits it to the key register; A key register, connected to the data selector, which is used to store the current key; Among them, the AES key processing circuit is used to run the AES key processing method; the AES key processing method includes: During data encryption or decryption, the AES key processing circuit performs a round of key refresh on the key, and uses the key after each refresh to update the key in the key register until the number of key refresh times reaches a preset number; among them, the key register only stores the current key; Before the start of data encryption or decryption, the AES key processing circuit updates the key in the key register to the initial key according to the AES module enable and the initial key configuration completion signal; If the AES direction of the AES key processing circuit is configured as the data encryption direction, a round of forward key transformation is performed on the key, and the forward key transformation refers to sequentially refreshing the initial key in the key register to the final key; if the AES direction of the AES key processing circuit is configured as the data decryption direction, a round of inverse key transformation is performed on the key, and the inverse key transformation refers to sequentially refreshing the final key in the key register to the initial key; If the AES direction of the AES key processing circuit is configured as the data decryption direction, after refreshing the key in the key register to the initial key, the AES key processing circuit performs key pre-refresh according to the key pre-refresh enable signal generated by the key pre-refresh control state machine module; the key pre-refresh means performing a round of forward transformation on the key in the key register before data decryption to update the key in the key register to the final key.

2. The AES key processing circuit according to claim 1, wherein, The key transformation module includes a forward key transformation module and an inverse key transformation module, where The forward key transformation module, connected to the first OR gate, is used to receive the key pre-refresh enable or the key refresh enable, and perform a round of forward key transformation during data encryption and key pre-refresh; The inverse key transformation module is used to receive the key refresh enable to perform a round of inverse key transformation during data decryption.

3. The AES key processing circuit according to claim 2, characterized in that, The data selector includes a first data selector and a second data selector, where The first data selector, connected to the forward key transformation module and the inverse key transformation module, is used to receive the output of the forward key transformation module, the output of the inverse key transformation module, and the AES direction configured by an external module, and select the output of the forward key transformation module or the inverse key transformation module as the input of the second data selector according to the AES direction; A second data selector, connected to the first data selector, is configured to receive the output of the first data selector, the initial key configured by an external module, and the initial key configuration completion signal configured by the external module, and select, according to the initial key configuration completion signal, either the output of the first selector or the initial key as the input to the key register; Wherein, the AES direction includes a data encryption direction and a data decryption direction.

4. The AES key processing circuit according to claim 1, wherein, The processing circuit further includes a second OR gate, connected to the key pre-refresh control state machine module, and configured to receive the initial key configuration completion signal input by the external module and the key pre-refresh completion interrupt signal output by the key pre-refresh control state machine module, and perform an OR operation on the initial key configuration completion signal and the key pre-refresh completion interrupt signal to generate a key register write enable to control the writing of the key register.

5. The AES key processing circuit according to claim 1, wherein The key pre-refresh control state machine module includes a state machine and a counter; the state machine is configured to control the counter to count the number of pulses of the key pre-refresh enable.

Images