A PCB layer offset detection device, method and related components

Abstract

This invention discloses a PCB layer misalignment detection device, method, and related components, relating to the field of PCB inspection technology. It includes a layer misalignment identification module and at least two detection modules on the PCB layer to be inspected. The detection modules are configured with positions between conductors and first preset via contacts, second preset via contacts, and preset through-hole locations. When the PCB board is drilled from the preset through-hole locations on the outermost PCB layer, if layer misalignment occurs in the PCB layer to be inspected, the conductors in the detection modules on the PCB layer to be inspected will be cut. Therefore, the layer misalignment identification module can determine the layer misalignment state of the PCB to be inspected by the conductivity state of the conductors. By setting multiple detection modules on the PCB layer to be inspected, the layer misalignment state of the PCB layer to be inspected can be determined based on the conductivity state of the conductors in the detection modules after drilling holes in the PCB board. This allows for timely detection of whether layer misalignment has occurred on the PCB board, reducing losses during PCB design.

Description

Technical Field

[0001] This invention relates to the field of PCB inspection technology, and in particular to a PCB layer offset detection device, method and related components. Background Technology

[0002] As the number of layers in PCBs (Printed Circuit Boards) increases, their precision also becomes higher, and the accuracy of alignment between different layers of the PCB becomes more and more stringent. The problem of PCB layer misalignment is receiving more and more attention. If the PCB layer misalignment exceeds the specification requirements, the PCB will be unusable and scrapped.

[0003] In summary, how to detect PCB layer misalignment after the PCB board is generated is an urgent problem to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a PCB layer misalignment detection device, method, and related components. By setting multiple detection modules on the PCB layer to be detected, and drilling holes in the PCB board, the layer misalignment state of the PCB layer to be detected can be determined based on the conductivity state of the wires in the detection modules. This enables timely detection of whether the PCB board has experienced layer misalignment, reducing losses during PCB board design.

[0005] To address the aforementioned technical problems, this invention provides a PCB layer offset detection device, comprising a layer offset identification module and at least two detection modules disposed on the PCB layer to be detected on a PCB board. A gap is provided between any two detection modules. Each detection module includes a first preset via contact, a second preset via contact, and a wire. Each detection module corresponds to a preset via position on the PCB layer to be detected. The relative positions between the first preset via contact and the corresponding preset via position in any two detection modules are different.

[0006] The first end of the wire is connected to the first preset through-hole contact, and the second end is connected to the second preset through-hole contact. A first gap is provided around the preset through-hole position and between the wire and the preset through-hole position, and a second gap is provided between the first preset through-hole contact and the second preset through-hole contact.

[0007] The first end of the layer offset identification module is connected to the first preset via contact of the detection module, and the second end is connected to the second preset via contact. It is used to determine the layer offset state of the PCB layer to be detected based on the conductivity state of the wires in each detection module after the PCB board is drilled from each preset via position of the outermost PCB layer.

[0008] In one alternative embodiment, the PCB board further includes a first via and a second via corresponding to each of the detection modules;

[0009] The first via is a via generated by drilling a hole on the outermost PCB layer at the position corresponding to the first preset via contact point of the PCB layer to be tested;

[0010] The second via is a via generated by drilling a hole on the outermost PCB layer at the position corresponding to the second preset via contact point of the PCB layer to be tested;

[0011] The first end of the layer offset recognition module is connected to the first preset via contact of the detection module through the first via, and the second end is connected to the second preset via contact of the detection module through the second via.

[0012] In one alternative approach, the outermost PCB layer of the PCB board is provided with a silkscreen marking of the PCB layer to be tested, corresponding to the position of the detection module on the PCB layer to be tested.

[0013] In one alternative embodiment, the PCB board includes a plurality of PCB layers to be tested, each of the PCB layers to be tested includes at least two testing modules, and the positions of the testing modules on each of the PCB layers to be tested are different.

[0014] According to another aspect of the present invention, a PCB layer offset detection method is provided, applied to the layer offset identification module in the PCB layer offset detection device as claimed in claim 1, comprising:

[0015] Current is passed through the first and second preset via contacts of each detection module to detect the conductivity of the wires in each detection module.

[0016] The layer offset state of the PCB layer to be detected is determined based on the conductivity state of the wires in each of the detection modules.

[0017] In one optional approach, determining the layer offset state of the PCB layer to be detected based on the conductivity state of the wires in each of the detection modules includes:

[0018] Determine whether all the wires in each of the detection modules are in a conductive state;

[0019] If not, then it is determined that the PCB layer to be tested has a layer offset.

[0020] In one alternative approach, after determining that the PCB layer to be detected has a layer offset, the method further includes:

[0021] Determine the cut position of the wire that is not in a conductive state;

[0022] The layer offset direction of the PCB layer to be tested is determined based on the cutting position.

[0023] According to another aspect of the present invention, a PCB layer offset detection system is provided, applied to the layer offset identification module in the PCB layer offset detection device as described above, the system comprising:

[0024] The current input unit is used to input current into the first preset via contact and the second preset via contact of each detection module to detect the conductivity state of the wires in each detection module.

[0025] The determining unit is used to determine the layer offset state of the PCB layer to be detected based on the conductivity state of the wires in each of the detection modules.

[0026] In one alternative approach, the determining unit is specifically used for:

[0027] Determine whether all the wires in each of the detection modules are in a conductive state;

[0028] If not, then it is determined that the PCB layer to be tested has a layer offset.

[0029] In an alternative embodiment, after the determining unit determines that the PCB layer to be detected has a layer misalignment, the PCB layer offset detection system is further configured to:

[0030] Determine the cut position of the wire that is not in a conductive state;

[0031] The layer offset direction of the PCB layer to be tested is determined based on the cutting position.

[0032] According to another aspect of the present invention, a PCB layer offset detection device is provided, comprising: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus;

[0033] The memory is used to store at least one executable instruction that causes the processor to perform the operation of the PCB layer offset detection method as described in any of the above.

[0034] According to another aspect of the present invention, a computer-readable storage medium is provided, the storage medium storing at least one executable instruction that causes a PCB layer offset detection device / system to perform the following operations:

[0035] Current is passed through the first and second preset via contacts of each detection module to detect the conductivity of the wires in each detection module.

[0036] The layer offset state of the PCB layer to be detected is determined based on the conductivity state of the wires in each of the detection modules.

[0037] In one optional approach, determining the layer offset state of the PCB layer to be detected based on the conductivity state of the wires in each of the detection modules includes:

[0038] Determine whether all the wires in each of the detection modules are in a conductive state;

[0039] If not, then it is determined that the PCB layer to be tested has a layer offset.

[0040] In one alternative approach, after determining that the PCB layer to be detected has a layer offset, the method further includes:

[0041] Determine the cut position of the wire that is not in a conductive state;

[0042] The layer offset direction of the PCB layer to be tested is determined based on the cutting position.

[0043] This invention discloses a PCB layer misalignment detection device, method, and related components, relating to the field of PCB inspection technology. It includes a layer misalignment identification module and at least two detection modules on the PCB layer to be inspected. The detection modules are configured with positions between conductors and first preset via contacts, second preset via contacts, and preset through-hole locations. When the PCB board is drilled through the preset through-hole locations on the outermost PCB layer, if layer misalignment occurs in the PCB layer to be inspected, the conductors in the detection modules on the PCB layer to be inspected will be cut. Therefore, the layer misalignment identification module can determine the layer misalignment state of the PCB to be inspected by the conductivity state of the conductors. By setting multiple detection modules on the PCB layer to be inspected, the layer misalignment state of the PCB layer to be inspected can be determined based on the conductivity state of the conductors in the detection modules after drilling holes in the PCB board. This allows for timely detection of whether layer misalignment has occurred on the PCB board, reducing losses during PCB design. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the structure of a PCB layer offset detection device provided by the present invention;

[0046] Figure 2 This is a flowchart illustrating a PCB layer offset detection method provided by the present invention.

[0047] Figure 3 This invention provides a schematic diagram of four detection modules set on a PCB layer to be detected.

[0048] Figure 4 This is a schematic diagram of a PCB layer misalignment to be detected, provided by the present invention.

[0049] Figure 5 This is a schematic diagram of the structure of a PCB layer offset detection system provided by the present invention;

[0050] Figure 6 This is a schematic diagram of the structure of a PCB layer offset detection device provided by the present invention. Detailed Implementation

[0051] The core of this invention is to provide a PCB layer misalignment detection device, method, and related components. By setting multiple detection modules on the PCB layer to be detected, the layer misalignment state of the PCB layer to be detected can be determined based on the conductivity state of the wires in the detection modules after drilling holes in the PCB board. This enables timely detection of whether the PCB board has experienced layer misalignment, reducing losses during PCB board design.

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a PCB layer offset detection device provided by the present invention. The device includes a layer offset identification module 2 and at least two detection modules 1 disposed on the PCB layer to be detected on the PCB board. There is a gap between any two detection modules 1. Detection module 1 includes a first preset via contact C1, a second preset via contact C2 and a wire L1. Each detection module 1 corresponds to a preset via position CT on the PCB layer to be detected. The relative positions between the first preset via contact C1 and the corresponding preset via position CT in any two detection modules 1 are different.

[0054] The first end of the wire L1 is connected to the first preset via contact C1, and the second end is connected to the second preset via contact C2. A first gap is provided around the preset through hole position CT and between the wire L1 and the preset through hole position CT, and a second gap is provided between the first preset via contact C1 and the second preset via contact C2.

[0055] The first end of the layer offset identification module 2 is connected to the first preset via contact C1 of the detection module 1, and the second end is connected to the second preset via contact C2. It is used to determine the layer offset state of the PCB layer to be detected based on the conductivity state of the conductor L1 in each detection module 1 after the PCB board is CT drilled from each preset via position of the outermost PCB layer.

[0056] Considering that in the existing technology, if layer misalignment occurs in the PCB board during the design process, the PCB board cannot be used, which leads to a waste of resources. Therefore, it is necessary to detect whether layer misalignment has occurred in the PCB board during the design process.

[0057] In this application, multiple detection modules 1 are set on the PCB layer to be tested. Because each detection module 1 has a conductor L1 surrounding a preset via position CT, and there is a gap between each detection module 1, and the relative positions between the first preset via contact C1 and the corresponding preset via position CT in each detection module 1 are different, no matter which direction the PCB layer to be tested is offset, after drilling holes from each preset via position CT of the outermost PCB layer of the PCB board, the conductor L1 in one detection module 1 will always be cut off and the circuit will be broken. However, if the PCB layer to be tested is not offset, after drilling holes from each preset via position CT of the outermost PCB layer of the PCB board, the drilling position of each PCB layer in the PCB board is the preset via position CT, and the conductor L1 in the PCB layer to be tested will not be cut off. After the offset identification module 2 is connected to the first preset via contact C1 and the second preset via contact C2 of the detection module 1, it can detect the conductivity state of the conductor L1, and thus determine the offset state of the PCB layer to be tested based on the conductivity state of the conductor L1.

[0058] It should be noted that by setting more than one detection module 1 on the PCB layer to be tested, and setting a gap between any two detection modules 1, it is ensured that any two detection modules 1 do not overlap. Furthermore, by setting a second gap between the first preset via contact C1 and the second preset via contact C2, the first end and the second end of the conductor L1 are not directly connected. Only after the first end and the second end of the layer offset identification module 2 are connected to the first preset via contact C1 and the second preset via contact C2 in the same detection module 1, respectively, can the first end and the second end of the conductor L1 be connected through the layer offset identification module 2. Based on this, the layer offset identification module 2 can determine whether the conductor L1 has been cut.

[0059] Furthermore, since the conductor L1 surrounds the preset via position CT and there is a first gap between it and the preset via position CT, it is permissible for the PCB layer to be tested to have a layer offset within a range with a length less than the first gap. At this time, after drilling holes from each preset via position CT of the outermost PCB layer of the PCB board, although the drilling position of the PCB layer to be tested is not exactly the preset via position CT, it will not cut off the conductor L1 of the detection module 1 in the PCB layer to be tested.

[0060] The length of the first interval may be, but is not limited to, 4 mil, the shape of the preset through-hole position CT may be, but is not limited to, a circle with a diameter of 10 mil, and the distance between any two preset through-hole positions CT may be, but is not limited to, 15 mil.

[0061] It should be noted that the layer offset identification module 2 in this application may be, but is not limited to, an electricity meter. If it is an electricity meter, after the layer offset identification module 2 is connected to the wire L1, the electricity meter applies voltage between its first and second terminals. If the wire L1 is not cut off, the first and second terminals of the electricity meter can be energized, that is, the wire L1 can conduct electricity. If the wire L1 is cut off, the first and second terminals of the electricity meter are not conductive, and it can be determined that the wire L1 is not conductive.

[0062] Furthermore, it should be noted that when the PCB board includes more than one PCB layer to be inspected, the position of the inspection module 1 is different for each PCB layer. This ensures that when drilling holes at the preset via positions CT corresponding to inspection modules 1 at different locations, the inspection module 1 containing the cut conductor L1 can be determined, thus directly identifying the PCB layer where the layer deviation occurs. Specifically, the exact position of each inspection module 1 can be determined using the coordinates on the PCB board.

[0063] It should be further explained that, with Figure 1 Taking two detection modules 1 on the PCB layer to be tested as an example, in one detection module 1, the first preset via contact C1 is located above the corresponding preset through hole position CT, and the first preset via contact C1 of the other detection module 1 is located to the left of the corresponding preset through hole position CT. Based on this, when the PCB layer to be tested is offset to the right, after drilling holes at the two preset through hole positions, the wire L1 in the detection module where the first preset via contact C1 is located to the left of the corresponding preset through hole position CT will not be cut off, but the wire L1 in the detection module where the first preset via contact C1 is located above the corresponding preset through hole position CT will be cut off and will not be able to conduct electricity.

[0064] Furthermore, the shape of the preset through-hole position CT can also be square, and the portion of the corresponding wire L1 surrounding the preset through-hole position CT can also be square; this application does not limit this.

[0065] In summary, this application incorporates a layer offset identification module 2 and at least two detection modules 1 on the PCB layer to be inspected. Detection modules 1 define the positions of conductor L1 with the first preset via contact C1, the second preset via contact C2, and the preset via position CT. When the PCB is drilled from the outermost PCB layer through the preset via positions CT, if layer offset occurs in the PCB layer to be inspected, the conductor L1 in detection module 1 on the PCB layer to be inspected will be cut off. Therefore, the layer offset identification module 2 can determine the layer offset state of the PCB to be inspected based on the conductivity of conductor L1. By setting multiple detection modules 1 on the PCB layer to be inspected, the layer offset state of the PCB layer to be inspected can be determined based on the conductivity of conductor L1 in detection module 1 after drilling holes in the PCB. This allows for timely detection of whether layer offset has occurred on the PCB, reducing losses during PCB design.

[0066] Based on the above embodiments:

[0067] In a preferred embodiment, the PCB board further includes a first via and a second via corresponding to each detection module 1;

[0068] The first via is a via generated by drilling a hole on the outermost PCB layer at the position corresponding to the first preset via contact C1 of the PCB layer to be tested.

[0069] The second via is a via generated by drilling a hole on the outermost PCB layer at the position corresponding to the second preset via contact C2 of the PCB layer to be tested.

[0070] The first end of the layer offset identification module 2 is connected to the first preset via contact C1 of the detection module 1 through the first via, and the second end is connected to the second preset via contact C2 of the detection module 1 through the second via.

[0071] In this embodiment, the PCB board also includes a first via generated by drilling a hole from the outermost PCB layer at the position of the first preset via contact C1 of the PCB layer to be detected, and a second via generated by drilling a hole from the outermost PCB layer at the position of the second preset via contact C2 of the PCB layer to be detected. That is, a hole can be drilled at the same position as the first preset via contact C1 of the PCB layer to be detected on the outermost PCB layer to generate the first via, and a hole can be drilled at the same position as the second preset via contact C2 of the PCB layer to be detected on the outermost PCB layer to generate the second via. When the PCB layer to be detected is in a relatively central position on the PCB board, the layer offset identification module 2 can connect to the first preset via contact C1 of the PCB layer to be detected from the first via, and connect to the second preset via contact C2 of the PCB layer to be detected from the second via.

[0072] The first preset via contact C1 and the second preset via contact C2 are surrounded by copper plating. This allows the layer misalignment identification module 2 to transmit current to the conductor L1 after connecting to the first preset via contact C1 and the second preset via contact C2. The distance between the copper plating edge around the first preset via contact C1 and the second preset via contact C2 and the first preset via contact C2 can be greater than the length of the first interval. This ensures that when layer misalignment occurs on the PCB to be detected, the first via is detected from the outermost PCB layer. After the first via and the second via, the first via and the second via can still be plated with copper around the first preset via contact C1 and the second preset via contact C2, respectively. This ensures that the layer offset identification module 2 can be connected to the first preset via contact C1 through the first via, and then connected to the first end of the wire L1 through the copper plating around the first preset via contact C1. After being connected to the second preset via contact C2 through the second via, it can be connected to the second end of the wire L1 through the copper plating around the second preset via contact C2, thereby determining the conductivity state of the wire L1.

[0073] As a preferred embodiment, the outermost PCB layer of the PCB board is provided with a silkscreen marking of the PCB layer to be tested, which corresponds to the position of the detection module 1 on the PCB layer to be tested.

[0074] In this embodiment, in order to determine the specific number of the PCB layer to be tested, a silkscreen marking of the PCB layer to be tested is also set on the outermost PCB layer, corresponding to the position of the detection module 1 on the PCB layer to be tested.

[0075] For example, the third and fourth layers of the PCB board are the PCB to be tested. Not only do the positions of the various detection modules 1 on the third layer not overlap, but the positions of the various detection modules 1 on the fourth layer also do not overlap. The positions of the various detection modules 1 on the third and fourth layers do not overlap. However, the positions of the detection modules 1 on the third layer and the detection modules 1 on the fourth layer can be determined from the outermost PCB layer. Therefore, an L3 identification silkscreen is added at the position corresponding to the detection module 1 on the third layer on the outermost layer, and an L4 identification silkscreen is added at the position corresponding to the detection module 1 on the fourth layer on the outermost layer. Of course, the specific setting of the identification silkscreen on the PCB layer to be tested is not limited in this application.

[0076] Based on this, when the user drills a hole at the preset via position using CT, the detection module 1 corresponding to the preset via position CT can be determined from the silkscreen on the outermost PCB layer, so that the layer offset identification module 2 can detect the specific location of the PCB layer where the layer offset has occurred.

[0077] In a preferred embodiment, the PCB board includes multiple PCB layers to be tested, each PCB layer to be tested includes at least two testing modules 1, and the positions of each testing module 1 on each PCB layer to be tested are different.

[0078] In this embodiment, when a PCB board includes multiple PCB layers to be tested, the detection module 1 on each PCB layer to be tested is set to a different position to ensure that the PCB layer with layer misalignment can be accurately determined after drilling a hole in the outermost PCB layer.

[0079] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a PCB layer misalignment detection method provided by the present invention. The method is applied to the layer misalignment identification module 2 in the PCB layer misalignment detection device described above, and includes:

[0080] S11: Current is supplied to the first preset via contact C1 and the second preset via contact C2 of each detection module 1 to detect the conductivity state of the wire L1 in each detection module 1.

[0081] In this embodiment, when the layer offset identification module 2 determines whether the PCB layer to be detected has experienced layer offset based on the detection module 1 on the PCB layer to be detected, specifically, after the first preset via contact C1 and the second preset via contact C2 are connected, current is passed through the first preset via contact C1 and the second preset via contact C2 of the detection module 1 to detect the conductivity state of the wire L1 in each detection module 1. Specifically, if current is passed through, the layer offset identification module 2 can determine whether the wire L1 is conductive by identifying whether there is a voltage difference between the two ends of the wire L1.

[0082] Based on this, it can be directly determined whether the conductor L1 has been cut, so as to determine whether the PCB layer under test has a layer offset.

[0083] Of course, when current is supplied to the first preset via contact C1 and the second preset via contact C2 of each detection module 1, the conductivity state of the wire L1 of each detection module 1 can be detected sequentially, or current can be supplied to the first preset via contact C1 and the second preset via contact C2 of each detection module 1 at the same time. This application does not limit this.

[0084] S12: Determine the layer offset state of the PCB layer to be detected based on the conductivity state of the conductor L1 in each detection module 1.

[0085] By determining the conductivity state of the wires L1 in each detection module 1, it can be determined whether the wires L1 in each detection module 1 have been cut. If they have been cut, then the PCB layer to be tested where the detection module 1 is located has a layer offset. Based on this, the layer offset state of the PCB layer to be tested can be determined.

[0086] For a description of the PCB layer offset detection method provided by the present invention, please refer to the above-described device embodiment; the present invention will not be described in detail here.

[0087] As a preferred embodiment, the layer offset state of the PCB layer to be detected is determined based on the conductivity state of the conductors L1 in each detection module 1, including:

[0088] Determine whether all wires L1 in each detection module 1 are in a conductive state;

[0089] If not, then the PCB layer to be tested is determined to have a layer misalignment.

[0090] In this embodiment, since each PCB layer to be tested includes multiple detection modules 1, and the layer offset direction of the PCB layer to be tested cannot be controlled, the detection modules 1 located at different positions and with different relative directions can be used to determine whether the PCB layer to be tested has experienced layer offset.

[0091] Of course, only when all the wires L1 in each detection module 1 are conductive can it be determined that the PCB layer under test has not been deflected. Based on this, it is possible to accurately determine whether the PCB layer under test has been deflected.

[0092] As a preferred embodiment, after determining that the PCB layer to be detected has a layer offset, the method further includes:

[0093] Determine the cut position of wire L1, which is not in a conductive state;

[0094] The layer offset direction of the PCB layer to be tested is determined based on the cutting position.

[0095] In this embodiment, considering that when the PCB layer to be detected has a layer deviation, after drilling a hole at the preset through-hole position of the outermost PCB layer, the position where the conductor L1 is cut can reflect the layer deviation direction of the PCB layer to be detected. Based on this, the PCB board generation device can be improved after determining the layer deviation direction of the PCB layer to be detected, so as to reduce the layer deviation problem of the PCB board.

[0096] Please refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of a PCB layer to be tested with four detection modules provided by the present invention. Figure 4 This is a schematic diagram of a PCB layer misalignment to be detected, provided by the present invention.

[0097] Figure 3 If a CT (Cut-Off-Cut) hole is drilled at the preset via location, and the PCB layer to be inspected shows layer misalignment, the following will occur: Figure 4 In the case where conductor L1 is cut, the layer offset direction can be determined, such as... Figure 4The PCB layer to be tested is offset to the left, resulting in the actual drilling position being to the right of the preset through-hole position CT.

[0098] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a PCB layer misalignment detection system provided by the present invention. The system is applied to the layer misalignment identification module 2 in the PCB layer misalignment detection device described above. The system includes:

[0099] The current-inlet unit 501 is used to supply current to the first preset via contact C1 and the second preset via contact C2 of each detection module 1 to detect the conductivity state of the wire L1 in each detection module 1.

[0100] The determining unit 502 is used to determine the layer offset state of the PCB layer to be detected based on the conductivity state of the conductor L1 in each detection module 1.

[0101] In one alternative approach, determining unit 502 is specifically used for:

[0102] Determine whether all wires in each detection module are in a conductive state;

[0103] If not, then the PCB layer to be tested is determined to have a layer misalignment.

[0104] In one alternative approach, after the determining unit 502 determines that a layer misalignment has occurred in the PCB layer to be detected, the PCB layer misalignment detection system further performs the following:

[0105] Determine the cut location for wires that are not in a conductive state;

[0106] The layer offset direction of the PCB layer to be tested is determined based on the cutting position.

[0107] For an introduction to the PCB layer offset detection system provided by the present invention, please refer to the above method embodiments; the present invention will not be described in detail here.

[0108] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a PCB layer offset detection device provided by the present invention. The specific embodiments of the present invention do not limit the specific implementation of the PCB layer offset detection device.

[0109] like Figure 6 As shown, the PCB layer offset detection device may include: a processor 602, a communication interface 604, a memory 606, and a communication bus 608.

[0110] The processor 602, communication interface 604, and memory 606 communicate with each other via communication bus 608. Communication interface 604 is used to communicate with other network elements, such as clients or other servers. Processor 602 executes program 610, specifically performing the relevant steps described in the embodiment of the PCB layer offset detection method.

[0111] Specifically, program 610 may include program code, which includes computer-executable instructions.

[0112] Processor 602 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. The PCB layer offset detection device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0113] Memory 606 is used to store program 610. Memory 606 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0114] Specifically, program 610 can be called by processor 602 to cause the PCB layer offset detection device to perform the following operations:

[0115] Current is passed through the first and second preset via contacts of each detection module to detect the conductivity of the wires in each detection module.

[0116] The layer offset state of the PCB layer to be detected is determined based on the conductivity state of the wires in each of the detection modules.

[0117] In an alternative embodiment, the program 410 is invoked by the processor 402 to cause the PCB layer offset detection device to perform the following operations:

[0118] Determining the layer offset state of the PCB layer to be tested based on the conductivity state of the conductors in each of the detection modules includes:

[0119] Determine whether all the wires in each of the detection modules are in a conductive state;

[0120] If not, then it is determined that the PCB layer to be tested has a layer offset.

[0121] In an alternative embodiment, the program 410 is invoked by the processor 402 to cause the PCB layer offset detection device to perform the following operations:

[0122] After determining that the PCB layer to be detected has a layer offset, the process further includes:

[0123] Determine the cut position of the wire that is not in a conductive state;

[0124] The layer offset direction of the PCB layer to be tested is determined based on the cutting position.

[0125] For an introduction to the PCB layer offset detection device provided by the present invention, please refer to the above method embodiments; the present invention will not be described in detail here.

[0126] This invention provides a computer-readable storage medium storing at least one executable instruction. When the executable instruction is run on a PCB layer offset detection device / system, the PCB layer offset detection device / system performs the PCB layer offset detection method in any of the above method embodiments.

[0127] Specifically, the executable instructions can be used to cause the PCB layer offset detection equipment / system to perform the following operations:

[0128] Current is passed through the first and second preset via contacts of each detection module to detect the conductivity of the wires in each detection module.

[0129] The layer offset state of the PCB layer to be detected is determined based on the conductivity state of the wires in each of the detection modules.

[0130] In an alternative approach, the executable instructions cause the PCB layer offset detection device / system to perform the following operations:

[0131] Determining the layer offset state of the PCB layer to be tested based on the conductivity state of the conductors in each of the detection modules includes:

[0132] Determine whether all the wires in each of the detection modules are in a conductive state;

[0133] If not, then it is determined that the PCB layer to be tested has a layer offset.

[0134] In an alternative approach, the executable instructions cause the PCB layer offset detection device / system to perform the following operations:

[0135] After determining that the PCB layer to be detected has a layer offset, the process further includes:

[0136] Determine the cut position of the wire that is not in a conductive state;

[0137] The layer offset direction of the PCB layer to be tested is determined based on the cutting position.

[0138] For a description of the storage medium provided by the present invention, please refer to the above method embodiments; the present invention will not be described again here.

[0139] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0140] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A PCB layer misalignment detection device, characterized in that, The system includes a layer offset identification module and at least two detection modules disposed on the PCB layer to be tested on the PCB board. There is a gap between any two detection modules. Each detection module includes a first preset via contact, a second preset via contact, and a continuous wire. Each detection module corresponds to a preset via position on the PCB layer to be tested. The relative positions between the first preset via contact and the corresponding preset via position in any two detection modules are different. The first end of the wire is connected to the first preset through-hole contact, and the second end is connected to the second preset through-hole contact. A first gap is provided around the preset through-hole position and between the wire and the preset through-hole position, and a second gap is provided between the first preset through-hole contact and the second preset through-hole contact. The first end of the layer offset identification module is connected to the first preset via contact of the detection module, and the second end is connected to the second preset via contact. It is used to determine the layer offset state of the PCB layer to be detected based on the conductivity state of the wires in each detection module after the PCB board is drilled from each preset via position of the outermost PCB layer. When it is determined that the PCB layer to be detected has a layer offset, the cutting position of the wire that is not in a conductive state is determined, and the layer offset direction of the PCB layer to be detected is determined based on the cutting position. The PCB board includes multiple PCB layers to be tested, each PCB layer to be tested includes at least two testing modules, and the positions of each testing module on each PCB layer to be tested are different. The PCB board also includes a first via and a second via corresponding to each of the detection modules; The first via is a via generated by drilling a hole on the outermost PCB layer at the position corresponding to the first preset via contact point of the PCB layer to be tested; The second via is a via generated by drilling a hole on the outermost PCB layer at the position corresponding to the second preset via contact point of the PCB layer to be tested; The first end of the layer offset recognition module is connected to the first preset via contact of the detection module through the first via, and the second end is connected to the second preset via contact of the detection module through the second via.

2. The PCB layer misalignment detection device as claimed in claim 1, characterized in that, The outermost PCB layer of the PCB board is provided with a silkscreen marking of the PCB layer to be tested, which corresponds to the position of the detection module on the PCB layer to be tested.

3. A method for detecting PCB layer misalignment, characterized in that, The layer offset identification module applied in the PCB layer offset detection device as described in any one of claims 1-2 includes: Current is passed through the first and second preset via contacts of each detection module to detect the conductivity of the wires in each detection module. The layer offset state of the PCB layer to be detected is determined based on the conductivity state of the wires in each of the detection modules. After determining that the PCB layer to be detected has a layer offset, the cut position of the conductor that is not in a conductive state is determined; The layer offset direction of the PCB layer to be tested is determined based on the cutting position; The PCB board also includes a first via and a second via corresponding to each of the detection modules; The first via is a via generated by drilling a hole on the outermost PCB layer at the position corresponding to the first preset via contact point of the PCB layer to be tested; The second via is a via generated by drilling a hole on the outermost PCB layer at the position corresponding to the second preset via contact point of the PCB layer to be tested; The first end of the layer offset recognition module is connected to the first preset via contact of the detection module through the first via, and the second end is connected to the second preset via contact of the detection module through the second via.

4. The PCB layer offset detection method as described in claim 3, characterized in that, Determining the layer offset state of the PCB layer to be detected based on the conductivity state of the conductors in each of the detection modules includes: Determine whether all the wires in each of the detection modules are in a conductive state; If not, then it is determined that the PCB layer to be tested has a layer offset.

5. A PCB layer misalignment detection system, characterized in that, The layer offset identification module is applied in the PCB layer offset detection device as described in any one of claims 1-2, and the system includes: The current input unit is used to input current into the first preset via contact and the second preset via contact of each detection module to detect the conductivity state of the wires in each detection module. The determining unit is used to determine the layer offset state of the PCB layer to be tested based on the conductivity state of the wires in each of the detection modules, and after determining that the PCB layer to be tested has a layer offset, determine the cutting position of the wire that is not in a conductive state, and determine the layer offset direction of the PCB layer to be tested based on the cutting position.

6. A PCB layer misalignment detection device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the operation of the PCB layer offset detection method as described in any one of claims 3-4.

7. A computer-readable storage medium, characterized in that, The storage medium stores at least one executable instruction, which, when executed on the PCB layer offset detection device / system, causes the PCB layer offset detection device / system to perform the operation of the PCB layer offset detection method as described in any one of claims 3-4.

Images