Temperature Delay Device and Temperature Control System

Abstract

A temperature delay device includes a first temperature sensor, a second temperature sensor, an inverter, and a latch circuit. The first temperature sensor is used to detect a first temperature of the chip, so as to output a first input signal. The second temperature sensor is used to detect a second temperature of the chip, so as to output a second input signal. The inverter is coupled to the first temperature sensor and is used to invert the first input signal, so as to output a third input signal. The latch circuit is coupled to the inverter and the second temperature sensor, and is used to generate an output signal according to the second input signal and the third input signal. The first temperature is different from the second temperature. This case provides a temperature delay device and a temperature control system, so as to construct a temperature delay range R1, so that the chip will not be turned off due to drastic temperature changes.

Description

Technical Field

[0001] This case relates to an electronic device and an electronic system. More specifically, this case relates to a temperature delay device and a temperature control system. Background Art

[0002] In existing devices, the temperature generated by the operation of the chip can cause communication chaos between the chip and the control circuit. Due to drastic temperature changes, it is easy to cause the chip to shut down, and then cause the device to shut down.

[0003] Therefore, there are still many defects in the above technology, and it is necessary for practitioners in this field to develop other suitable circuit designs. Summary of the Invention

[0004] One aspect of this case relates to a temperature delay device. The temperature delay device includes a first temperature sensor, a second temperature sensor, an inverter, and a latch circuit. The first temperature sensor is used to detect the first temperature of the chip, so as to output a first input signal. The second temperature sensor is used to detect the second temperature of the chip, so as to output a second input signal. The inverter is coupled to the first temperature sensor and is used to invert the first input signal to output a third input signal. The latch circuit is coupled to the inverter and the second temperature sensor and is used to generate an output signal according to the second input signal and the third input signal. The first temperature is different from the second temperature.

[0005] In some embodiments, when the measured temperature of the chip is higher than the first temperature but lower than the second temperature, the latch circuit is used to lock the first state of the chip.

[0006] In some embodiments, when the measured temperature of the chip is higher than the second temperature, the latch circuit is used to generate an output signal to change the first state of the chip to the second state.

[0007] In some embodiments, when the measured temperature of the chip is lower than the second temperature but higher than the first temperature, the latch circuit is used to lock the second state of the chip.

[0008] In some embodiments, when the measured temperature of the chip is lower than the first temperature, the latch circuit is used to generate an output signal to change the second state of the chip to the first state.

[0009] In some embodiments, the latch circuit includes a set terminal and a reset terminal. The set terminal of the latch circuit is coupled to the inverter, and the reset terminal of the latch circuit is coupled to the second temperature sensor.

[0010] In some embodiments, the latch circuit further includes two logic gates. One of the two logic gates is coupled to the set terminal. The other of the two logic gates is coupled to the reset terminal.

[0011] In some embodiments, both of the two logic gates include at least one of a NOR gate and a NAND gate.

[0012] Another aspect of the present case relates to a temperature control system. The temperature control system includes a first temperature delay device, a second temperature delay device, a third temperature delay device, and a control circuit. The first temperature delay device is used to detect a first temperature and a second temperature of the wafer, so as to output a first input signal. The second temperature delay device is used to detect a third temperature and a fourth temperature of the wafer, so as to output a second input signal. The third temperature delay device is used to detect a fifth temperature and a sixth temperature of the wafer, so as to output a third input signal. The control circuit is coupled to the first temperature delay device, the second temperature delay device, and the second temperature delay device. The control circuit is used to receive the first input signal, the second input signal, and the third input signal, so as to output two signals. The first temperature, the second temperature, the third temperature, the fourth temperature, the fifth temperature, and the sixth temperature are all different.

[0013] In some embodiments, the first temperature and the second temperature form a first temperature delay range. The third temperature and the fourth temperature form a second temperature delay range. The fifth temperature and the sixth temperature form a third temperature delay range. The first temperature delay range, the second temperature delay range, and the third temperature delay range do not overlap with each other.

[0014] In some embodiments, the first temperature delay device, the second temperature delay device, and the third temperature delay device all include at least one of two temperature sensors, an inverter, and a latch circuit.

[0015] In some embodiments, the control circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first temperature delay device, the second temperature delay device, and the third temperature delay device are respectively coupled to the first input terminal, the second input terminal, and the third input terminal.

[0016] In some embodiments, the control circuit includes a first logic gate. The first logic gate is coupled to the second temperature delay device, the first input terminal, and the first output terminal. The first logic gate includes an inverter.

[0017] In some embodiments, the control circuit includes a second logic gate. The second logic gate is coupled to the first temperature delay device, the second input terminal, and the first logic gate. The second logic gate includes an AND gate.

[0018] In some embodiments, the control circuit includes a third logic gate. The third logic gate is coupled to the second logic gate, the third temperature delay device, and the third input terminal. The third logic gate includes an OR gate. Description of the Drawings

[0019] Referring to the embodiments in the following paragraphs and the following drawings, the content of the present case can be better understood:

[0020] Figure 1 A circuit block diagram of a temperature control system illustrated according to some embodiments of the present case;

[0021] Figure 2 A circuit block diagram of a temperature delay device illustrated according to some embodiments of the present case;

[0022] Figure 3 A coordinate schematic diagram of the relationship between the signal of a temperature delay device and the measured temperature of a wafer illustrated according to some embodiments of the present case;

[0023] Figure 4 A coordinate schematic diagram of the relationship between the signal of a temperature delay device and the temperature of a wafer illustrated according to some embodiments of the present case;

[0024] Figure 5 A circuit block diagram of a temperature control system illustrated according to some embodiments of the present case;

[0025] Figure 6 A partial circuit block diagram of a temperature control system illustrated according to some embodiments of the present case;

[0026] Figure 7 A coordinate schematic diagram of the relationship between the measured temperature of a temperature control system illustrated according to some embodiments of the present case; and

[0027] Figure 8 A coordinate schematic diagram of the relationship between the signals of a temperature control system illustrated according to some embodiments of the present case. Detailed implementation manners

[0028] The spirit of the present case will be clearly described below with diagrams and detailed descriptions. After any person skilled in the art understands the embodiments of the present case, the techniques taught by the present case can be changed and modified without departing from the spirit and scope of the present case.

[0029] The terms used in this article are only for describing specific embodiments and are not intended to limit the present case. Singular forms such as "a", "this", "that", "the", and "this" as used herein also include plural forms.

[0030] Regarding the use of "including", "comprising", "having", "containing", etc. in this article, they are all open-ended terms, that is, they are meant to include but not be limited to.

[0031] Regarding the terms used in this article, unless otherwise specified, they generally have the ordinary meanings of each term used in this field, in the context of the present case, and in the context of the specific content. Some of the terms used to describe the present case will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the present case.

[0032] Figure 1 A circuit block diagram of the temperature control system 1 illustrated according to some embodiments of the present case. In some embodiments, please refer to Figure 1 , the temperature control system 1 includes a temperature delay device 10 and a control circuit 20. The control circuit 20 is coupled to the temperature delay device 10. The temperature delay device 10 is used to measure the first temperature T1 and the second temperature T2 of the wafer 9 so as to generate an output signal O1 to the control circuit 20. The control circuit 20 is used to control the wafer 9 according to the output signal O1 and through a control signal S1. The control circuit 20 includes a feedback circuit. The wafer 9 includes a flash memory, a hard disk drive (HDD), a solid state drive (SSD), a dynamic random access memory (DRAM), a static random access memory (SRAM), a central processing unit (CPU), and a graphic processing unit (GPU).

[0033] Figure 2 A circuit block diagram of the temperature delay device 10 illustrated according to some embodiments of the present case. In some embodiments, please refer to Figure 2 , as Figure 2 shown, the temperature delay device 10 is Figure 1 a detailed structure of the temperature delay device 10 of the embodiment of

[0034] In some embodiments, please refer to Figure 1 and Figure 2 , the temperature delay device 10 includes a first temperature sensor 110, a second temperature sensor 120, an inverter 130, and a latch circuit 140. The first temperature sensor 110 is used to detect the first temperature T1 of the wafer 9 so as to output a first input signal In1. The second temperature sensor 120 is used to detect the second temperature T2 of the wafer 9 so as to output a second input signal In2. The inverter 130 is coupled to the first temperature sensor 110 and is used to invert the first input signal In1 so as to output a third input signal In3. The latch circuit 140 is coupled to the inverter 130 and the second temperature sensor 120 and is used to generate an output signal O1 according to the second input signal In2 and the third input signal In3. The first temperature T1 is different from the second temperature T2.

[0035] In some embodiments, the latch circuit 140 includes a set terminal and a reset terminal. The set terminal of the latch circuit 140 is coupled to the inverter 130. The reset terminal of the latch circuit 140 is coupled to the second temperature sensor 120. The latch circuit 140 includes two logic gates (e.g., logic gate 141 and logic gate 142). One of the two logic gates (e.g., logic gate 141) is coupled to the set terminal. The other of the two logic gates (e.g., logic gate 142) is coupled to the reset terminal. Each of the two logic gates includes at least one of a NOR gate and a NAND gate.

[0036] Figure 3 It is a schematic coordinate diagram showing the relationship between the signals of the temperature delay device and the measured temperature of the wafer according to some embodiments of the present case. In some embodiments, to facilitate the understanding of the temperature delay device of the present case, please also refer to Figures 1 to 3 , the vertical axis of the coordinate diagram is the signal of the temperature delay device. The horizontal axis of the coordinate diagram is the temperature of the wafer. The conventional temperature TJ1 is specified by the memory standard of the JEDEC Solid State Technology Association. The design purpose of the present case is to construct a temperature delay range (e.g., temperature delay range R1) such that the wafer will not be turned off due to the drastic temperature change of the temperature delay device. In some embodiments, there is a difference D1 between the conventional temperature TJ1 and the first temperature T1. There is a difference D2 between the conventional temperature TJ1 and the second temperature T2. In some embodiments, the difference D1 is the same as or different from the difference D2. The difference D1 and the difference D1 can be designed according to actual requirements. In some embodiments, the conventional temperature TJ1 includes at least one of a temperature of 45 °C, a temperature of 85 °C, and a temperature of 105 °C.

[0037] In some embodiments, please refer to Figures 1 to 3 , when the measured temperature of the wafer 9 is higher than the first temperature T1 but lower than the second temperature T2, the latch circuit 140 is used to lock the first state of the wafer 9 along the path L1. It should be noted that the measured temperature is the actual temperature and the varying temperature of the wafer 9. The first temperature T1 and the second temperature T2 are both fixed temperatures to distinguish the actual temperature of the wafer 9.

[0038] Specifically, the first temperature T1 is measured by the first temperature sensor 110, such that the first temperature sensor 110 generates a first input signal In1 (for example, the first input signal In1 is 1). The inverter 130 inverts the first input signal In1 (for example, the first input signal In1 is 1), so as to output a third input signal In3 (for example, the third input signal In3 is 0). At the same time, the second temperature T2 is not measured by the second temperature sensor 120, such that the second temperature sensor 120 generates a second input signal In2 (for example, the second input signal In2 is 0). When the second input signal In2 is 0 and the third input signal In3 is 0, the latch circuit 140 is used to generate an output signal O1. The output signal O1 is 0. Therefore, the control circuit 20 does not control the wafer 9 to change states.

[0039] In some embodiments, when the measured temperature of the wafer 9 is higher than the second temperature T2, the latch circuit 140 is used to generate an output signal O1 (for example, the output signal O1 is 1), so as to change the first state of the wafer 9 to the second state of the wafer 9 along the path L2.

[0040] Specifically, the first temperature T1 is measured by the first temperature sensor 110, such that the first temperature sensor 110 generates a first input signal In1 (for example, the first input signal In1 is 1). The inverter 130 inverts the first input signal In1 (for example, the first input signal In1 is 1), so as to output a third input signal In3 (for example, the third input signal In3 is 0). At the same time, the second temperature T2 is measured by the second temperature sensor 120, such that the second temperature sensor 120 generates a second input signal In2 (for example, the second input signal In2 is 1). When the second input signal In2 is 1 and the third input signal In3 is 0, the latch circuit 140 is used to generate an output signal O1. The output signal O1 is 1. Therefore, the control circuit 20 controls the wafer 9 to change states. It should be noted that if the measured temperature of the wafer 9 suddenly drops but does not exceed the temperature delay range, the wafer 9 will not change states again. In other words, the state of the wafer 9 is locked.

[0041] In some embodiments, please also refer to Figures 1 to 3, when the measured temperature of the wafer 9 is lower than the second temperature T2 but higher than the first temperature T1, the latch circuit 140 is used to lock the second state of the wafer 9 along path L3. Specifically, the first temperature T1 is measured by the first temperature sensor 110, so that the first temperature sensor 110 generates a first input signal In1 (for example, the first input signal In1 is 1). The inverter 130 inverts the first input signal In1 (for example, the first input signal In1 is 1), thereby outputting a third input signal In3 (for example, the third input signal In3 is 0). At the same time, the second temperature T2 is not measured by the second temperature sensor 120, so that the second temperature sensor 120 generates a second input signal In2 (for example, the second input signal In2 is 0). When the second input signal In2 is 0 and the third input signal In3 is 0, the latch circuit 140 is used to generate an output signal O1. The output signal O1 is 1. Therefore, the control circuit 20 does not control the wafer 9 to change states. In other words, the state of the wafer 9 is locked.

[0042] In some embodiments, please also refer to Figures 1 to 3 , when the measured temperature of the wafer 9 is lower than the first temperature T1, the latch circuit 140 is used to generate an output signal to change the second state of the wafer 9 to the first state of the wafer 9 along path L4.

[0043] Specifically, the first temperature T1 is not measured by the first temperature sensor 110, so that the first temperature sensor 110 generates a first input signal In1 (for example, the first input signal In1 is 0). The inverter 130 inverts the first input signal In1 (for example, the first input signal In1 is 0), thereby outputting a third input signal In3 (for example, the third input signal In3 is 1). At the same time, the second temperature T2 is not measured by the second temperature sensor 120, so that the second temperature sensor 120 generates a second input signal In2 (for example, the second input signal In2 is 0). When the second input signal In2 is 0 and the third input signal In3 is 1, the latch circuit 140 is used to generate an output signal O1. The output signal O1 is 0. Therefore, the control circuit 20 controls the wafer 9 to change states.

[0044] In summary, the truth table of the temperature delay device 10 is listed as follows:

[0045]

[0046] Table 1

[0047] In Table 1, T is the measured temperature mentioned in the above embodiments.

[0048] Figure 4Schematic coordinate diagram of the relationship between the signal of the temperature delay device and the temperature of the wafer shown according to some embodiments of the present case. In some embodiments, to facilitate the understanding of the temperature delay device of the present case, please also refer to Figures 1 to 4 , Figure 4 The embodiment of Figure 3 is another expression of the embodiment. Figure 4 The upper half of Figure 4 is the temperature curve diagram of the wafer in the normal heating and cooling states, and

[0049] Figure 5 The lower half of Figure 1 is the signal timing diagram of the temperature delay device. It should be noted that in practice, the measured temperature T of the wafer changes complexly and violently. Furthermore, it should be noted that the wafer does not change states in stage I2 and stage I4. Since the detailed operation of the temperature delay device 10 has been described in the previous paragraphs, it will not be elaborated here. Figure 5 Figure 1 Figure 2 and Figure 1

[0050] Figure 6

[0051] Figure 5 Partial circuit block diagram of the temperature control system shown according to some embodiments of the present case.

[0051] In some embodiments, please refer to Figure 5 and Figure 6, the first temperature delay device 10A is used to measure the first temperature T1 and the second temperature T2 of the wafer 9 to output a first input signal O1. The second temperature delay device 30A is used to measure the third temperature T3 and the fourth temperature T4 of the wafer 9 to output a second input signal O2. The third temperature delay device 40A is used to measure the fifth temperature T5 and the sixth temperature T6 of the wafer 9 to output a third input signal O3. The control circuit 20A is coupled to the first temperature delay device 10A, the second temperature delay device 30A, and the third temperature delay device 40A. The control circuit 20A is used to receive the first input signal O1, the second input signal O2, and the third input signal O3, thereby outputting two signals (for example: output signal X and output signal Y). The first temperature T1, the second temperature T2, the third temperature T3, the fourth temperature T4, the fifth temperature T5, and the sixth temperature T6 are all different. The first temperature T1, the second temperature T2, the third temperature T3, the fourth temperature T4, the fifth temperature T5, and the sixth temperature T6 are all fixed temperatures to distinguish the actual temperature of the wafer 9.

[0052] In some embodiments, please refer to Figure 2 and Figure 6 , the first temperature delay device 10A, the second temperature delay device 30A, and the third temperature delay device 40A all include Figure 2 the two temperature sensors, inverters, and latch circuits shown.

[0053] In some embodiments, the control circuit 20A includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first temperature delay device 10A, the second temperature delay device 30A, and the third temperature delay device 40A are respectively coupled to the first input terminal, the second input terminal, and the third input terminal.

[0054] In some embodiments, the control circuit 20A includes a first logic gate 21A, a second logic gate 22A, and a third logic gate 23A. The first logic gate 21A is coupled to the second temperature delay device 30A, the first input terminal, and the first output terminal. In some embodiments, the first logic gate 21A includes an inverter. The second logic gate 22A is coupled to the first temperature delay device 10A, the second input terminal, and the first logic gate 21A. In some embodiments, the second logic gate 22A includes an AND gate. The third logic gate 23A is coupled to the second logic gate 22A, the third temperature delay device 40A, the third input terminal, and the second output terminal. In some embodiments, the third logic gate 23A includes an OR gate.

[0055] Figure 7 is a schematic relationship coordinate diagram of the measured temperatures of the temperature control system illustrated according to some embodiments of the present case. In some embodiments, compared with Figure 4 the embodiments of Figure 4and Figure 7 The difference lies in the number of temperature changes.

[0056] In some embodiments, the first temperature T1 and the second temperature T2 form a first temperature delay range R1. The third temperature T3 and the fourth temperature T4 form a second temperature delay range R2. The fifth temperature T5 and the sixth temperature T6 form a third temperature delay range R3. The first temperature delay range R1, the second temperature delay range R2, and the third temperature delay range R3 do not overlap with each other.

[0057] Figure 8 It is a schematic diagram of the relationship coordinates of the signals of the temperature control system shown according to some embodiments of this case. In some embodiments, compared with Figure 4 the embodiments of Figure 4 and Figure 8 the difference lies in the number of signals changed. Since the operations of the first temperature delay device 10A, the second temperature delay device 30A, and the third temperature delay device 40A are all the same as those of Figure 2 the temperature delay device 10 shown, they will not be elaborated here.

[0058] In summary, the truth table of the temperature control system 1A is listed as follows:

[0059]

[0060] Table 2

[0061] In Table 2, T is the measured temperature mentioned in the above embodiments.

[0062] In some embodiments, the Boolean algebraic expression of the temperature control system 1A is listed according to Table 2 and Figure 6 as follows:

[0063]

[0064] According to the foregoing embodiments, this case provides a temperature delay device and a temperature control system, thereby constructing a temperature delay range R1 so that the wafer will not shut down due to drastic temperature changes.

[0065] Although this case is disclosed in detail with the above embodiments, this case does not exclude other feasible implementation aspects. Therefore, the protection scope of this case shall be subject to the scope defined by the claims, rather than being limited by the foregoing embodiments.

[0066] For those skilled in the art, without departing from the spirit and scope of this case, various modifications and refinements can be made to this case. Based on the foregoing embodiments, all modifications and refinements made to this case are also covered by the protection scope of this case.

[0067]

Symbol Description

[0068] 1: Temperature control system

[0069] 10: Temperature delay device

[0070] 20: Control circuit

[0071] T1 to T2: Temperature

[0072] O1: Output signal

[0073] 9: Wafer

[0074] S1: Control signal

[0075] 110: First temperature sensor

[0076] 120: Second temperature sensor

[0077] 130: Inverter

[0078] 140: Latch circuit

[0079] In1: First input signal

[0080] In2: Second input signal

[0081] In3: Third input signal

[0082] 141: Logic gate

[0083] 142: Logic gate

[0084] R1: Temperature delay range

[0085] L1 to L4: Path

[0086] TJ1: Conventional temperature

[0087] T: Measured temperature

[0088] D1 to D2: Difference

[0089] I1 to I13: Stage

[0090] 1A: Temperature control system

[0091] 10A: Temperature delay device

[0092] 20A: Control circuit

[0093] 21A: Logic gate

[0094] 22A: Logic gate

[0095] 23A: Logic gate

[0096] 30A: Temperature delay device

[0097] 40A: Temperature delay device

[0098] T1 to T6: Temperature

[0099] O1 to O3: Input signal

[0100] XY: Output signal

[0101] R1 to R3: Temperature delay range.

Claims

1. A temperature delay device, characterized in that, Comprising: A first temperature sensor for detecting a first temperature of the chip and outputting a first input signal thereby; A second temperature sensor for detecting a second temperature of the chip and outputting a second input signal thereby; An inverter coupled to the first temperature sensor and for inverting the first input signal to output a third input signal thereby; And A latch circuit coupled to the inverter and the second temperature sensor and for generating an output signal based on the second input signal and the third input signal, wherein the first temperature is different from the second temperature.

2. The temperature delay device according to claim 1, wherein, When the measured temperature of the chip is higher than the first temperature but lower than the second temperature, the latch circuit is for locking a first state of the chip, wherein the measured temperature is an actual varying temperature, and wherein both the first temperature and the second temperature are fixed temperatures.

3. The temperature delay device according to claim 2, wherein When the measured temperature of the chip is higher than the second temperature, the latch circuit is for generating the output signal to change the first state of the chip to a second state thereby.

4. The temperature delay device according to claim 3, wherein When the measured temperature of the chip is lower than the second temperature but higher than the first temperature, the latch circuit is for locking the second state of the chip.

5. The temperature delay device according to claim 4, characterized in that, When the measured temperature of the chip is lower than the first temperature, the latch circuit is for generating the output signal to change the second state of the chip to the first state thereby.

6. The temperature delay device according to claim 1, wherein The latch circuit includes a set terminal and a reset terminal, wherein the set terminal of the latch circuit is coupled to the inverter, and wherein the reset terminal of the latch circuit is coupled to the second temperature sensor.

7. The temperature delay device according to claim 6, wherein The latch circuit further includes two logic gates, wherein one of the two logic gates is coupled to the set terminal, and wherein the other of the two logic gates is coupled to the reset terminal.

8. The temperature delay device according to claim 7, wherein Each of the two logic gates includes at least one of a NOR gate and a NAND gate.

9. A temperature control system, characterized in that, Comprising: A first temperature delay device for detecting a first temperature and a second temperature of the chip and outputting a first input signal thereby; A second temperature delay device for detecting a third temperature and a fourth temperature of the chip and outputting a second input signal thereby; A third temperature delay device for detecting a fifth temperature and a sixth temperature of the chip and outputting a third input signal thereby; And A control circuit coupled to the first temperature delay device, the second temperature delay device, and the third temperature delay device, wherein the control circuit is for receiving the first input signal, the second input signal, and the third input signal to output two signals for locking the state of the chip in a plurality of temperature delay ranges, wherein the first temperature, the second temperature, the third temperature, the fourth temperature, the fifth temperature, and the sixth temperature are all different, and wherein the temperature delay ranges are formed by a temperature range between the first temperature and the second temperature, a temperature range between the third temperature and the fourth temperature, and a temperature range between the fifth temperature and the sixth temperature.

10. The temperature control system according to claim 9, wherein, The temperature delay ranges include a first temperature delay range, a second temperature delay range, and a third temperature delay range. The first temperature and the second temperature form the first temperature delay range. The third temperature and the fourth temperature form the second temperature delay range. The fifth temperature and the sixth temperature form the third temperature delay range. The first temperature delay range, the second temperature delay range, and the third temperature delay range do not overlap with each other.

11. The temperature control system according to claim 9, wherein, The first temperature delay device, the second temperature delay device, and the third temperature delay device each include at least one of two temperature sensors, an inverter, and a latch circuit.

12. The temperature control system according to claim 9, wherein The control circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first temperature delay device, the second temperature delay device, and the third temperature delay device are respectively coupled to the first input terminal, the second input terminal, and the third input terminal.

13. The temperature control system according to claim 12, characterized in that, The control circuit includes a first logic gate. The first logic gate is coupled to the second temperature delay device, the first input terminal, and the first output terminal. The first logic gate includes an inverter gate.

14. The temperature control system according to claim 13, wherein, The control circuit includes a second logic gate. The second logic gate is coupled to the first temperature delay device, the second input terminal, and the first logic gate. The second logic gate includes an AND gate.

15. The temperature control system according to claim 14, wherein The control circuit includes a third logic gate. The third logic gate is coupled to the second logic gate, the third temperature delay device, and the third input terminal. The third logic gate includes an OR gate.

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