A data reading method and apparatus based on multi-channel DDR memory

Abstract

This application provides a data reading method and apparatus based on multi-channel DDR memory. The method includes: acquiring a read operation command from a read channel; determining the DDR memory group with the lowest memory occupancy rate among multiple DDR memory groups; wherein the DDR memory group includes two DDR memory channels; converting the read operation command into two read memory instructions; sending the two read memory instructions to the two DDR memory channels respectively; caching two read data obtained from the two DDR memory channels; distributing data based on the two read data to obtain return data; and feeding back the return data based on the read channel. It is evident that this method and apparatus can realize multi-channel DDR off-chip storage, thereby solving the existing performance bottleneck problem; it can also solve the arbitration problem of multi-user interface multi-channel DDR, thus greatly improving data read and write performance in various scenarios.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and more specifically, to a data reading method and apparatus based on multi-channel DDR memory. Background Technology

[0002] With the continuous increase in network bandwidth, CPUs can no longer meet the system's processing performance requirements, leading to the more widespread application of intelligent network accelerator cards. Among these applications, off-chip DDR memory access is a crucial component of the intelligent network accelerator card system.

[0003] Typically, accelerator card systems use only one set of DDR memory, accessed by multiple user interfaces. However, with the increase in network interface bandwidth, high-throughput network interfaces such as 40G and 100G are favored by users. But, in the process of accelerating service forwarding between multiple high-speed interfaces, the performance of off-chip DDR memory access limits the forwarding performance of the accelerator card system.

[0004] Therefore, how to solve the performance bottleneck problem of system access to off-chip DDR memory has become one of the technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a data reading method and apparatus based on multi-channel DDR memory, which can realize multi-channel DDR off-chip storage, thereby solving the existing performance bottleneck problem; it can also solve the arbitration problem of multi-user interface multi-channel DDR, thereby greatly improving the data read and write performance in various scenarios.

[0006] The first aspect of this application provides a data reading method based on multi-channel DDR memory, including:

[0007] Retrieve read operation commands from the read channel;

[0008] Among multiple DDR memory groups, the DDR memory group with the lowest memory utilization rate is determined; wherein, the DDR memory group includes two DDR memory channels;

[0009] The read operation command is converted into two memory read instructions;

[0010] Send the two memory read commands to the two DDR memory channels respectively;

[0011] The cache retrieves two read data entries from the two DDR memory paths.

[0012] Based on the two read data, data is distributed to obtain the returned data;

[0013] Based on the read channel, the returned data is fed back.

[0014] In the above implementation process, this method can prioritize acquiring read operation commands from the read channels. Therefore, this method can acquire user-input read operation commands from multiple read channels, thereby achieving fast and orderly processing of multiple commands across multiple channels. This allows the method to be applied to high-throughput systems, resulting in more stable and efficient data reading. Next, the method determines the DDR memory group with the lowest memory utilization among multiple DDR memory groups. Each DDR memory group includes two DDR memory modules. This method can select the DDR memory group with the lowest current utilization, thereby improving access performance through multiple DDR memory modules. Simultaneously, this mechanism can balance the access commands across multiple DDR memory modules, avoiding access congestion and improving data reading efficiency. Finally, the method converts the read operation commands into two memory read instructions. This method can automatically convert user-input read operation commands into memory read instructions usable by DDR memory, facilitating data reading operations on DDR memory based on these instructions. After receiving two memory read commands, this method sends them to two separate DDR memory channels. This allows the read operations to be executed automatically, meaning the method only needs to wait for the data return without affecting other read commands. This enables parallel processing, ensuring stability under heavy data loads. Next, upon receiving the two read data from the two DDR memory channels, the method caches them. This caches the received read data, even if it's incomplete, and iterates through iterative updates to ensure data acquisition and prevent direct processing, thus guaranteeing read validity and preventing errors. After caching the two read data, the method distributes the returned data. This allows the method to select the accurate read data corresponding to the read command, ensuring both stability and accuracy. Finally, the method returns data based on the read channel. It can be seen that the method can complete the data reading and feedback based on this step, thereby completing the feedback of the read operation command. This can solve the arbitration problem of multi-user interface multi-channel DDR and greatly improve the data reading performance in various scenarios.

[0015] Furthermore, the step of obtaining the read operation command in the read channel includes:

[0016] The system uses a polling method to receive read operation commands from multiple read channels; wherein the read operation command includes at least the address to be read and the length to be read.

[0017] In the above implementation process, this method can use a polling approach to receive read operation commands from multiple read channels, including the address to be read and the length to be read. It is evident that this method can order read operation commands based on polling, thereby addressing application scenarios with multiple data channels and ensuring the input efficiency and stability of read operation commands. Simultaneously, the address to be read and the length to be read determine the location of the data to be read, thus ensuring successful data reading.

[0018] Furthermore, the step of determining the DDR memory group with the lowest memory utilization rate among multiple DDR memory groups includes:

[0019] Identify multiple available depths that correspond one-to-one with multiple DDR memory groups;

[0020] The DDR memory group with the largest available depth is determined as the DDR memory group with the lowest memory utilization.

[0021] In the above implementation process, when determining the DDR memory group with the lowest memory utilization among multiple DDR memory groups, this method can first identify multiple available depths corresponding one-to-one with the multiple DDR memory groups; then, the DDR memory group with the largest available depth is determined as the DDR memory group with the lowest memory utilization. It can be seen that this method can determine the busy status of each DDR based on the available depth of the DDR memory (where a smaller depth indicates more incomplete commands in the DDR memory), and select the most idle DDR memory accordingly, thereby improving data reading efficiency and avoiding access congestion.

[0022] Furthermore, after the step of determining the DDR memory group with the lowest memory utilization rate among multiple DDR memory groups, the method further includes:

[0023] The cache contains read information corresponding to the read operation command; wherein the read information includes at least the read command tag, the read channel ID, and the DDR memory group information.

[0024] In the above implementation process, the method can also cache the read command tag, read channel ID and DDR memory group information corresponding to the read operation command, thereby recording the sorting position of this read operation command, which facilitates the management of a large number of read operations and also facilitates the evidence collection and query of other steps.

[0025] Furthermore, the step of distributing data based on the two read data to obtain the returned data includes:

[0026] The two read data are distinguished as first read data and second read data; wherein the first read data is obtained before the second read data.

[0027] Obtain the FIFO cache information corresponding to the first read data;

[0028] When the FIFO cache information matches the read information, the first read data is determined to be the return data;

[0029] When the FIFO cache information does not match the read information, the second read data is determined as the return data.

[0030] In the above implementation process, when distributing data based on two read data points and obtaining the returned data, this method can prioritize distinguishing the two read data points into the first read data obtained earlier and the second read data obtained later. Simultaneously, it acquires the FIFO cache information corresponding to the first read data. It is evident that this method can prioritize acquiring a complete read data point, then obtain the corresponding data read information, and use this as a basis to determine whether the acquired data matches the current read operation command, thereby ensuring the consistency between the command and the data, and thus guaranteeing the accuracy of data reading under a large number of read operations. Specifically, this method can determine the first read data as the returned data when the FIFO cache information matches the read information; or determine the second read data as the returned data when the FIFO cache information does not match the read information. As can be seen, when the complete read data obtained by this method matches the read operation command, it returns the correct read data, thus ensuring the data reading effect. When there is a mismatch, another set of read data is used as a backup to ensure that the corresponding read data is obtained, avoiding the absolute failure of the entire process due to a single mismatch. Simultaneously, this method also considers the case where two matches fail, using the second set of read data as a backup strategy. This prevents the data reading process from stalling at that step and allows for timely notification to relevant personnel for handling. In summary, this method ensures both the accuracy and stability of the read data.

[0031] Furthermore, prior to the step of obtaining the read operation command in the read channel, the method further includes:

[0032] Write operation commands are received using a polling method; wherein, the write operation command includes at least the address to be written, the length to be written, and the data to be written;

[0033] Convert the write operation command into a memory write instruction;

[0034] The write memory command is sent to all DDR memory locations to write the data to be written into all DDR memory locations.

[0035] In the above implementation process, before obtaining the read operation command from the read channel, this method can also use a polling method to receive write operation commands including the address to be written, the length to be written, and the data to be written; then, the write operation command is converted into a write memory instruction; and then the write memory instruction is sent to all DDR memory to write the data to be written into all DDR memory. It can be seen that this method writes data in a corresponding manner before reading data, thereby enabling the method to achieve both read and write operations, further improving the application scenarios of this method.

[0036] A second aspect of this application provides a data reading device based on multi-channel DDR memory, the data reading device based on multi-channel DDR memory comprising:

[0037] The acquisition unit is used to acquire read operation commands from the read channel;

[0038] A determining unit is used to determine the DDR memory group with the lowest memory utilization rate among multiple DDR memory groups; wherein the DDR memory group includes two DDR memory channels;

[0039] The conversion unit is used to convert the read operation command into two memory read instructions;

[0040] The sending unit is used to send the two memory read commands to the two DDR memory channels respectively;

[0041] A cache unit is used to cache two read data obtained from the two DDR memory paths;

[0042] A distribution unit is used to distribute data based on the two read data sets to obtain return data.

[0043] A feedback unit is used to provide feedback on the returned data based on the read channel.

[0044] In the above implementation process, the device can acquire read operation commands from the read channel through the acquisition unit; determine the DDR memory group with the lowest memory occupancy among multiple DDR memory groups through the determination unit; wherein the DDR memory group includes two DDR memory channels; convert the read operation commands into two read memory instructions through the conversion unit; send the two read memory instructions to the two DDR memory channels respectively through the sending unit; cache the two read data acquired from the two DDR memory channels through the caching unit; distribute the data based on the two read data through the distribution unit to obtain return data; and then feed back the return data based on the read channel through the feedback unit. It is evident that this device can implement multi-channel DDR off-chip storage, thereby solving the existing performance bottleneck problem; it can also solve the arbitration problem of multi-user interface multi-channel DDR, thus greatly improving data read and write performance in various scenarios.

[0045] Furthermore, the acquisition unit is specifically used to receive read operation commands from multiple read channels using a polling method; wherein the read operation command includes at least the address to be read and the length to be read.

[0046] Furthermore, the determining unit includes:

[0047] The identification subunit is used to identify multiple available depths that correspond one-to-one with multiple DDR memory groups;

[0048] The first determining subunit is used to determine the DDR memory group with the largest available depth as the DDR memory group with the lowest memory occupancy rate.

[0049] Furthermore, the cache unit is also used to cache read information corresponding to the read operation command after determining the DDR memory group with the lowest memory occupancy rate among multiple DDR memory groups; wherein the read information includes at least the read command tag, the read channel ID, and the DDR memory group information.

[0050] Furthermore, the distribution unit includes:

[0051] A molecular unit is used to distinguish the two read data into first read data and second read data; wherein the first read data is acquired before the second read data.

[0052] The acquisition subunit is used to acquire FIFO cache information corresponding to the first read data;

[0053] The second determining subunit is used to determine the first read data as the return data when the FIFO cache information matches the read information;

[0054] The second determining subunit is further configured to determine the second read data as return data when the FIFO cache information does not match the read information.

[0055] Furthermore, the acquisition unit is also used to acquire write operation commands using a polling method; wherein the write operation command includes at least the address to be written, the length to be written, and the data to be written;

[0056] The conversion unit is also used to convert the write operation command into a write memory instruction;

[0057] The sending unit is further configured to send the write memory instruction to all DDR memory, so as to write the data to be written into all DDR memory.

[0058] A third aspect of this application provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor runs the computer program to cause the electronic device to perform the data reading method based on multi-channel DDR memory as described in any one of the first aspects of this application.

[0059] A fourth aspect of this application provides a computer-readable storage medium storing computer program instructions, which, when read and executed by a processor, perform the data reading method based on multi-channel DDR memory as described in any one of the first aspects of this application. Attached Figure Description

[0060] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 A flowchart illustrating a data reading method based on multi-channel DDR memory provided in this application embodiment;

[0062] Figure 2 A flowchart illustrating a data reading method based on multi-channel DDR memory provided in this application embodiment;

[0063] Figure 3 A schematic diagram of a data reading device based on multi-channel DDR memory provided in this application embodiment;

[0064] Figure 4 A schematic diagram of a data reading device based on multi-channel DDR memory provided in this application embodiment;

[0065] Figure 5 This is an example diagram illustrating FIFO cache information for a channel read command tag, provided in an embodiment of this application.

[0066] Figure 6 This is an example schematic diagram illustrating FIFO cache information for a DDR memory read channel provided in an embodiment of this application.

[0067] Figure 7 This is a schematic diagram of a data read / write architecture based on multi-channel DDR memory, provided as an embodiment of this application. Detailed Implementation

[0068] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0069] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0070] Example 1

[0071] Please refer to Figure 1 , Figure 1 This embodiment provides a flowchart illustrating a data reading method based on multi-channel DDR memory. The data reading method based on multi-channel DDR memory includes:

[0072] S101. Obtain the read operation command from the read channel.

[0073] In this embodiment, the method can arbitrate read commands.

[0074] In this embodiment, the method can cache the read operation command.

[0075] S102. Among multiple DDR memory groups, determine the DDR memory group with the lowest memory utilization rate; wherein, the DDR memory group includes two DDR memory channels.

[0076] In this embodiment, the method can perform arbitration by reading memory.

[0077] S103. Convert the read operation command into two memory read instructions.

[0078] In this embodiment, the method can control DDR0 and DDR1 through memory read instructions.

[0079] S104. Send the two memory read commands to the two DDR memory channels respectively.

[0080] S105 caches two read data obtained from two DDR memory paths.

[0081] In this embodiment, the method can cache the read data returned by DDR0 and DDR1.

[0082] S106. Distribute data based on the two read data to obtain the returned data.

[0083] In this embodiment, the method can distribute read data.

[0084] S107. Based on the read channel, feedback and return data.

[0085] In this embodiment, the method provided is an FPGA-based multi-user interface multi-channel DDR memory access arbitration method. This method employs dual-channel DDR memory, with both channels storing identical data, making it suitable for systems with frequent read command access. Specifically, it can be applied to intelligent network acceleration cards, intelligent encryption cards, etc.

[0086] In this embodiment, the method can focus on high-performance multi-user interface off-chip DDR memory access scenarios, especially systems with frequent read access. The key technical points involved in this method are as follows:

[0087] (1) Using multiple DDR memory, the multi-user interface read command arbitration mechanism balances the arbitration of read access to each DDR memory through multiple user interfaces according to the busy status of each DDR memory read command, which greatly improves the access performance of the off-chip DDR memory of the user interface.

[0088] (2) Each user interface is set with an ID number, and each read command of each user interface is set with a tag number. The return data frame distribution mechanism realizes the distribution of DDR memory return data frames by judging and matching information such as the return data frame ID and tag. This distribution mechanism effectively solves the problem of disordered order of return data frames received by user interfaces caused by multiple DDR memory accesses.

[0089] For example, this method can be applied to network security firewall products. Specifically, its application can solve the problem of low table lookup performance of intelligent network acceleration cards in network security firewall products, thereby improving the capabilities of network security firewall devices.

[0090] In this example, the security firewall product can use a smart network acceleration card to offload some services in the application environment to the smart network acceleration card, thereby freeing up CPU core resources and improving the CPU's service processing capabilities. The specific process in this example is as follows:

[0091] (1) During system operation, the CPU processes services from the device interface. Based on the service type or forwarding requirements, the CPU activates the acceleration forwarding function of the intelligent network acceleration card and sends the connection forwarding information to the intelligent network acceleration card through connection table entries. The intelligent network acceleration card receives the connection table entries and writes them into its off-chip dual-channel DDR memory according to the memory address specified by the CPU. Typically, the CPU calculates the memory address of the connection table entry based on the connection's quintuple or triplet information using a specific hash algorithm. After successfully storing the connection table entry information, the acceleration card informs the CPU that the connection table entry has been successfully sent.

[0092] (2) After the acceleration function of the smart network acceleration card is enabled, all traffic received by it needs to perform the function of querying the connection table entry. The smart network acceleration card also calculates the memory address of the connection table entry information according to the connection quintuple or triplet information and the hash algorithm specified by the CPU. Based on the calculated memory address result, it calls the multi-channel DDR storage access arbitration device to perform the query of the connection table entry information.

[0093] (3) In intelligent network acceleration card systems, especially high-performance intelligent network acceleration cards, there are usually multiple service processing channels. These channels access off-chip storage through a multi-user interface multi-channel DDR storage access arbitration device. This device arbitrates read commands based on the busy level of each DDR access command, evenly distributes read commands across user interfaces, avoids command blocking, and efficiently queries connection table entries. After each DDR storage returns read data, the read channel return data distribution module distributes the return data frames according to the ID and tag information corresponding to each data channel and the return data frame. The data frames are sent in the order of the original read commands of each user interface, thereby ensuring the correct order of the read data frames received by each user interface.

[0094] (4) During the process of the intelligent network acceleration card performing accelerated forwarding of services, it is necessary to collect some information of the accelerated forwarding services and write the service statistics and other information into the corresponding connection information at intervals. The multi-channel DDR storage access arbitration device updates the corresponding connection information in all DDR memory according to the write command information to ensure that the connection table information stored in all DDR memory is the same.

[0095] In this embodiment, the subject executing the method can be a computing device such as a computer or server, and no limitation is made in this embodiment.

[0096] In this embodiment, the subject executing the method can also be a smart device such as a smartphone or tablet, and no limitation is made in this embodiment.

[0097] As can be seen, implementing the data reading method based on multi-channel DDR memory described in this embodiment can achieve balanced access to multi-channel DDR storage across multiple user interfaces, thereby improving the memory access bandwidth of the user interface; at the same time, it can also provide the function of returning data frame distribution, thus effectively solving the data frame return order problem caused by multiple DDR channels in multiple user interfaces.

[0098] Example 2

[0099] Please refer to Figure 2 , Figure 2 This embodiment provides a flowchart illustrating a data reading method based on multi-channel DDR memory. The data reading method based on multi-channel DDR memory includes:

[0100] S201. Receive write operation commands using a polling method; wherein, the write operation command includes at least the address to be written, the length to be written, and the data to be written.

[0101] In this embodiment, this step can arbitrate write commands.

[0102] In this embodiment, the method can prune multiple write channel commands, use a polling method to receive write channel operation commands, and return a success response signal after the command is successfully received and written to the next level buffer.

[0103] In this embodiment, the method can store command data for the write channel, including information such as write address, write length, and write data.

[0104] S202. Convert the write operation command into a write memory instruction.

[0105] In this embodiment, this step can cache write commands.

[0106] S203. Send the write memory command to all DDR memory to write the data to be written into all DDR memory.

[0107] In this embodiment, this step enables control over memory writes.

[0108] In this embodiment, the method can convert command data in the write command cache into DDR memory write control instructions and write the data into all mounted DDR memory.

[0109] S204. Receive read operation commands from multiple read channels using a polling method; wherein, the read operation command includes at least the address to be read and the length to be read.

[0110] In this embodiment, the method can prune multiple read channel commands, receive read channel operation commands in a polling manner, and return a response success signal after the command is successfully received and written to the next level buffer.

[0111] In this embodiment, the method can cache command data for the read channel, including information such as read address, read length, and read channel ID.

[0112] S205 identifies multiple available depths that correspond one-to-one with multiple DDR memory groups.

[0113] S206. The DDR memory group with the largest available depth is determined as the DDR memory group with the lowest memory utilization rate; wherein, the DDR memory group includes two DDR memory channels.

[0114] In this embodiment, since the read channel bandwidth is large, accessing only one set of DDR memory cannot meet the performance requirements of the read channel. Therefore, this method can use two sets of DDR memory to improve access performance.

[0115] In this embodiment, the method can arbitrate and select one group of DDR memory with a lower current occupancy rate based on the read occupancy status of each DDR memory. After the DDR memory successfully responds to the read command, the read memory arbitration module sends and stores the user's read information.

[0116] In this embodiment, the method can mainly determine the busy status of each DDR by the available depth of the read channel information cache in the DDR memory. The smaller the depth, the more incomplete commands there are in the DDR memory, and the busier it is relative to the other DDR memory. The arbitration mechanism automatically selects to access the relatively less busy DDR memory. This mechanism can balance the access commands of the two DDRs to avoid access congestion.

[0117] S207, cache and read information corresponding to read operation commands; wherein, the read information includes at least the read command tag, read channel ID and DDR memory group information.

[0118] In this embodiment, the method can cache the information read by the user.

[0119] In this embodiment, the read command tag is used to refer to the tag value of each read channel. Each read command has a corresponding tag value, which indicates the order of read commands in the channel (the tag is incremented by 1 for each successful read command). The tag peak value should be set according to the system cache depth; generally, the peak value should be slightly larger than the FIFO depth value for safety. Please refer to [link / reference] for details. Figure 5 .

[0120] In this embodiment, the read channel ID is used to refer to the sequence number of the read channel.

[0121] In this embodiment, the read information can store the channel ID and read command tag for accessing the DDR memory, and is used to represent the channel number of this read command and the tag value corresponding to the read command under this channel. Please refer to [link / reference] for details. Figure 6 .in, Figure 6 The FIFO cache information for the DDR memory read channel is shown.

[0122] In this embodiment, read commands can be input through different read channel IDs, but regardless of which read channel is used, the tag value will increment accordingly. Based on this, it is easy to see... Figure 6 The input channels and input order of read commands in DDR0 and DDR1 are shown, thereby determining the overall order of read data operations and ensuring the stable execution of read data operations.

[0123] S208. Convert the read operation command into two memory read instructions.

[0124] In this embodiment, the method can convert the command data of the memory arbitration into DDR0 memory read control instructions and DDR1 memory read control instructions, and send the read command to the off-chip memory.

[0125] S209: Send the two memory read commands to the two DDR memory channels respectively.

[0126] S210 caches two read data obtained from two DDR memory channels.

[0127] In this embodiment, the method can cache read data returned by DDR0 memory and DDR1 memory. This cache must use the same cache type and have the same depth as the user read information cache.

[0128] S211. Divide the two read data into first read data and second read data; wherein the first read data is obtained before the second read data.

[0129] S212. Obtain the FIFO cache information corresponding to the first read data.

[0130] S213. When the FIFO cache information matches the read information, the first read data is determined as the return data.

[0131] S214. When the FIFO cache information does not match the read information, the second read data is determined as the return data.

[0132] In this embodiment, the method can use a polling mechanism to monitor whether the data returned by DDR0 and DDR1 are empty, and enter the distribution state when at least one frame of complete returned data is detected.

[0133] For example, if DDR0 returns a non-empty data buffer, then the FIFO buffer information of the corresponding DDR0 memory read channel is retrieved, and the read command information (id and tag) corresponding to the current frame data (i.e., the first read data) is obtained. The id information is used to confirm which read channel the current data frame belongs to, and its tag value is locked. Then, the FIFO buffer information of the read command tag of the corresponding channel is retrieved and matched with the tag value locked in the previous step. If they are the same, it means that the current data frame belongs to that channel (the id value represents the channel number), the current data frame is read out, and it is sent out through its channel number; if they are different, the next DDR1 that returns an empty data state is polled. When it returns a non-empty data buffer, the distribution operation is performed according to the above DDR0 distribution mechanism, and the data frame returned by DDR1 (i.e., the second read data) can definitely be sent out successfully.

[0134] S215, based on the read channel, returns feedback data.

[0135] Please refer to Figure 7 , Figure 7 A schematic diagram of a data read / write architecture based on multi-channel DDR memory is shown.

[0136] For example, a specific example of this method's process can be as follows:

[0137] (1) During system operation, the CPU sends key policy and other information to the connection with encryption requirements. The smart network encryption card receives the key policy and other information of the connection and writes it into its off-chip dual-channel DDR memory according to the memory address specified by the CPU. Usually, the CPU calculates the memory address of the connection key policy information through a specific hash algorithm based on the quintuple or triplet information of the connection. After successfully storing the connection key policy information, it informs the CPU that the connection table entry policy information has been successfully sent.

[0138] (2) The smart network encryption card calculates the memory address of the key policy information of the connection according to the connection quintuple or triplet information and the hash algorithm specified by the CPU. Based on the calculated memory address result, it calls the multi-channel DDR storage access arbitration device to perform the query of the connection key policy information and implements the encryption function according to the key policy information.

[0139] (3) During the process of encrypting services by the smart network encryption card, it is necessary to query information such as the key required by the encryption algorithm. The encryption algorithm interface calls the DDR storage access arbitration mechanism to realize key query.

[0140] (4) In a high-performance intelligent network encryption card system, in order to meet the encryption performance requirements, there are usually multiple encryption channels and a multi-user interface multi-channel DDR memory access arbitration mechanism to realize the sharing of multi-channel DDR memory resources. The device arbitrates the commands of all access channels according to the busy level of each DDR access command, realizes connection key policy query and key information query, and avoids memory access congestion.

[0141] (5) Channel read return data distribution mechanism: Based on the ID and tag information corresponding to the data returned by DDR memory, the key policy information and key information are distributed. This mechanism returns the corresponding connection key policy information and key information in the original read order to avoid information return disorder causing encryption errors.

[0142] In this embodiment, the subject executing the method can be a computing device such as a computer or server, and no limitation is made in this embodiment.

[0143] In this embodiment, the subject executing the method can also be a smart device such as a smartphone or tablet, and no limitation is made in this embodiment.

[0144] As can be seen, implementing the data reading method based on multi-channel DDR memory described in this embodiment can achieve balanced access to multi-channel DDR storage across multiple user interfaces, thereby improving the memory access bandwidth of the user interface; at the same time, it can also provide the function of returning data frame distribution, thus effectively solving the data frame return order problem caused by multiple DDR channels in multiple user interfaces.

[0145] Example 3

[0146] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a data reading device based on multi-channel DDR memory provided in this embodiment. Figure 3 As shown, the data reading device based on multi-channel DDR memory includes:

[0147] Acquisition unit 310 is used to acquire read operation commands in the read channel;

[0148] The determining unit 320 is used to determine the DDR memory group with the lowest memory utilization rate among multiple DDR memory groups; wherein the DDR memory group includes two DDR memory channels;

[0149] Conversion unit 330 is used to convert read operation commands into two memory read instructions;

[0150] The sending unit 340 is used to send two memory read commands to two DDR memory channels respectively;

[0151] Cache unit 350 is used to cache two read data obtained from two DDR memory channels;

[0152] Distribution unit 360 is used to distribute data based on two read data and obtain returned data;

[0153] Feedback unit 370 is used to return data based on the read channel.

[0154] In this embodiment, the explanation of the data reading device based on multi-channel DDR memory can be referred to the description in Embodiment 1 or Embodiment 2, and will not be repeated here.

[0155] As can be seen, the data reading device based on multi-channel DDR memory described in this embodiment can achieve balanced access to multi-channel DDR storage by multiple user interfaces, thereby improving the memory access bandwidth of the user interface; at the same time, it can also provide the function of returning data frame distribution, thereby effectively solving the data frame return order problem caused by multiple user interfaces and multiple DDR.

[0156] Example 4

[0157] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a data reading device based on multi-channel DDR memory provided in this embodiment. Figure 4 As shown, the data reading device based on multi-channel DDR memory includes:

[0158] Acquisition unit 310 is used to acquire read operation commands in the read channel;

[0159] The determining unit 320 is used to determine the DDR memory group with the lowest memory utilization rate among multiple DDR memory groups; wherein the DDR memory group includes two DDR memory channels;

[0160] Conversion unit 330 is used to convert read operation commands into two memory read instructions;

[0161] The sending unit 340 is used to send two memory read commands to two DDR memory channels respectively;

[0162] Cache unit 350 is used to cache two read data obtained from two DDR memory channels;

[0163] Distribution unit 360 is used to distribute data based on two read data and obtain returned data;

[0164] Feedback unit 370 is used to return data based on the read channel.

[0165] As an optional implementation, the acquisition unit 310 is specifically used to receive read operation commands from multiple read channels in a polling manner; wherein the read operation command includes at least the address to be read and the length to be read.

[0166] As an optional implementation, the determining unit 320 includes:

[0167] Identification subunit 321 is used to identify multiple available depths that correspond one-to-one with multiple DDR memory groups;

[0168] The first determining subunit 322 is used to determine the DDR memory group with the largest available depth as the DDR memory group with the lowest memory occupancy.

[0169] As an optional implementation, the cache unit 350 is also used to cache read information corresponding to the read operation command after determining the DDR memory group with the lowest memory occupancy rate among multiple DDR memory groups; wherein the read information includes at least the read command tag, read channel ID and DDR memory group information.

[0170] As an optional implementation, the distribution unit 360 includes:

[0171] The partition unit 361 is used to distinguish two read data into first read data and second read data; wherein the first read data is obtained before the second read data.

[0172] Acquisition subunit 362 is used to acquire FIFO cache information corresponding to the first read data;

[0173] The second determining subunit 363 is used to determine the first read data as the return data when the FIFO buffer information matches the read information;

[0174] The second determining subunit 363 is also used to determine the second read data as the return data when the FIFO buffer information does not match the read information.

[0175] As an optional implementation, the acquisition unit 310 is also used to acquire write operation commands using a polling method; wherein the write operation command includes at least the address to be written, the length to be written, and the data to be written;

[0176] The conversion unit 330 is also used to convert write operation commands into write memory instructions;

[0177] The sending unit 340 is also used to send write memory instructions to all DDR memory to write the data to be written into all DDR memory.

[0178] In this embodiment, the explanation of the data reading device based on multi-channel DDR memory can be referred to the description in Embodiment 1 or Embodiment 2, and will not be repeated here.

[0179] As can be seen, the data reading device based on multi-channel DDR memory described in this embodiment can achieve balanced access to multi-channel DDR storage by multiple user interfaces, thereby improving the memory access bandwidth of the user interface; at the same time, it can also provide the function of returning data frame distribution, thereby effectively solving the data frame return order problem caused by multiple user interfaces and multiple DDR.

[0180] This application provides an electronic device, including a memory and a processor. The memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to perform the data reading method based on multi-channel DDR memory in embodiment 1 or embodiment 2 of this application.

[0181] This application provides a computer-readable storage medium storing computer program instructions. When these computer program instructions are read and executed by a processor, they perform the data reading method based on multi-channel DDR memory as described in Embodiment 1 or Embodiment 2 of this application.

[0182] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0183] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0184] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0185] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0186] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0187] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A data reading method based on multi-channel DDR memory, characterized in that, include: Retrieve read operation commands from the read channel; Among multiple DDR memory groups, the DDR memory group with the lowest memory utilization rate is determined; wherein, the DDR memory group includes two DDR memory channels; The read operation command is converted into two memory read instructions; Send the two memory read commands to the two DDR memory channels respectively; The cache retrieves two read data entries from the two DDR memory paths. Based on the two read data, data is distributed to obtain the returned data; Based on the read channel, the returned data is fed back; Prior to the step of obtaining the read operation command in the read channel, the method further includes: Write operation commands are received using a polling method; wherein, the write operation command includes at least the address to be written, the length to be written, and the data to be written; Convert the write operation command into a memory write instruction; The write memory command is sent to all DDR memory locations to write the data to be written into all DDR memory locations.

2. The data reading method based on multi-channel DDR memory according to claim 1, characterized in that, The steps for obtaining the read operation command in the read channel include: The system uses a polling method to receive read operation commands from multiple read channels; wherein the read operation command includes at least the address to be read and the length to be read.

3. The data reading method based on multi-channel DDR memory according to claim 1, characterized in that, The step of determining the DDR memory group with the lowest memory utilization rate among multiple DDR memory groups includes: Identify multiple available depths that correspond one-to-one with multiple DDR memory groups; The DDR memory group with the largest available depth is determined as the DDR memory group with the lowest memory utilization.

4. The data reading method based on multi-channel DDR memory according to claim 1, characterized in that, After the step of determining the DDR memory group with the lowest memory utilization rate among multiple DDR memory groups, the method further includes: The cache contains read information corresponding to the read operation command; wherein the read information includes at least the read command tag, the read channel ID, and the DDR memory group information.

5. The data reading method based on multi-channel DDR memory according to claim 4, characterized in that, The step of distributing data based on the two read data to obtain the returned data includes: The two read data are distinguished as first read data and second read data; wherein the first read data is obtained before the second read data. Obtain the FIFO cache information corresponding to the first read data; When the FIFO cache information matches the read information, the first read data is determined to be the return data; When the FIFO cache information does not match the read information, the second read data is determined as the return data.

6. A data reading device based on multi-channel DDR memory, characterized in that, The data reading device based on multi-channel DDR memory includes: The acquisition unit is used to acquire read operation commands from the read channel; A determining unit is used to determine the DDR memory group with the lowest memory utilization rate among multiple DDR memory groups; wherein the DDR memory group includes two DDR memory channels; The conversion unit is used to convert the read operation command into two memory read instructions; The sending unit is used to send the two memory read commands to the two DDR memory channels respectively; A cache unit is used to cache two read data obtained from the two DDR memory paths; A distribution unit is used to distribute data based on the two read data sets to obtain return data. A feedback unit is used to provide feedback on the returned data based on the read channel; The acquisition unit is further configured to acquire write operation commands using a polling method; wherein the write operation command includes at least the address to be written, the length to be written, and the data to be written; The conversion unit is also used to convert the write operation command into a write memory instruction; The sending unit is further configured to send the write memory instruction to all DDR memory, so as to write the data to be written into all DDR memory.

7. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory being used to store a computer program, and the processor running the computer program to cause the electronic device to perform the data reading method based on multiple DDR memory as described in any one of claims 1 to 5.

8. A readable storage medium, characterized in that, The readable storage medium stores computer program instructions, which are read and executed by a processor to perform the data reading method based on multi-channel DDR memory as described in any one of claims 1 to 5.

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