Method for implementing a predetermined timing control circuit design for a memory asynchronous interface
By using a STA-based approach, synchronous control logic and blocking clock signal attributes are set to guide routing tools in selecting devices under optimal and worst-case process parameters. This solves the problems of excessive iterations and poor portability in asynchronous interface timing analysis in existing technologies, and achieves efficient placement and routing as well as process adaptability.
Patent Information
- Application Number
- CN202110956658.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-08-19
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2041-08-19
AI Technical Summary
Existing static timing analysis tools cannot effectively constrain and analyze the asynchronous timing interfaces embedded in the chip, resulting in a large number of iterations, which is time-consuming, labor-intensive, and not conducive to process portability.
By using a STA-based method, it is possible to determine whether there is an asynchronous relationship in the timing of the memory interface, set synchronous control logic, block clock signal attributes, and calculate timing differences under preset process parameters. This guides the routing tool to select devices under optimal and worst-case conditions to meet the timing requirements of the asynchronous interface.
Reduce the number of placement and routing iterations, improve design portability, enhance process adaptability, and achieve effective constraints and analysis of asynchronous interfaces.
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Figure CN115906729B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of timing analysis in circuit layout and routing, in particular to the field of layout and routing timing analysis of asynchronous interface timing circuit, and more particularly to a method for realizing predetermined timing control circuit design for memory asynchronous interface based on STA system and in combination with timing analysis tool STA and front-end circuit design. BACKGROUND
[0002] In the process of integrated circuit design and development, generally speaking, synchronous timing requirements are guaranteed by static timing analysis tool STA analysis, but for some chip-embedded asynchronous timing interface, such as OTP memory interface, static timing analysis tool generally cannot constrain them, so that the timing of this part of the asynchronous interface mostly needs to be verified by dynamic timing, that is, post-simulation, which has a long verification period. The existing timing analysis STA generally does not constrain and analyze asynchronous interface circuit, but after layout and routing, dynamic timing analysis method is used to gate simulate the timing under the worst and best conditions of the provided environment. If the asynchronous interface cannot work normally under these two conditions, the design must be analyzed for this problem, and the correct modification trend is constantly pointed out, and the layout and gate simulation are constantly performed, and such iteration is continued until the best solution is found. This method is time-consuming and laborious, and is not conducive to the process transplantation of chip design. SUMMARY
[0003] The present application aims to overcome the above-mentioned shortcomings of the prior art, and provides a method for realizing predetermined timing control circuit design for memory asynchronous interface based on STA system, which has fewer iteration times and high portability.
[0004] In order to achieve the above-mentioned purpose, the method for realizing predetermined timing control circuit design for memory asynchronous interface based on STA system of the present application is as follows:
[0005] The method for realizing predetermined timing control circuit design for memory asynchronous interface based on STA system, which mainly comprises the following steps:
[0006] (1) The designer judges whether there is an asynchronous timing relationship in the interface timing of the memory according to the interface timing requirements of the memory, and if there is, step (2) is executed; otherwise, the process is not continued;
[0007] (2) The designer performs output signal generation processing of the address change control register and storage read control logic output signal generation processing of the memory for the memory, and calculates the timing difference between the clock signal, the addressing signal, the memory read control logic output signal and the memory data output signal under the condition of the preset process parameters.
[0008] (3) The STA system sets the synchronization control logic related to the clock signal according to the input operation of the designer, blocks the clock attribute of the clock signal to generate a normal output signal, and sets the optimal layout timing interval;
[0009] (4) The STA system performs layout and routing synthesis according to the input operation of the designer, and returns the STA system interface for back-visit netlist to verify the predetermined timing.
[0010] Preferably, the asynchronous timing relationship in step (1) is specifically:
[0011] The timing relationship not subject to static timing constraints of the clock signal.
[0012] Preferably, the output signal generation process of the address change control register and the memory read control logic output signal generation process in step (2) specifically include the following steps:
[0013] (2.1) The designer performs input operation on the memory, compares the addressing signals in the current address register group and the next address register group of the memory, and generates the output signal of the address change control register.
[0014] (2.2) The designer performs logical AND operation on the clock signal and the output signal of the address change control register through a blocking buffer to generate the memory read control logic output signal.
[0015] More preferably, the step (2) of calculating the timing difference between the clock signal, the addressing signal, the memory read control logic output signal and the memory data output signal under the preset process parameter conditions specifically includes:
[0016] The designer calculates the timing difference between the clock signal, the addressing signal, the memory read control logic output signal and the memory data output signal under the optimal and worst process parameter conditions, respectively.
[0017] Preferably, the step of calculating the timing difference between the clock signal, the addressing signal, the memory read control logic output signal and the memory data output signal under the preset process parameter conditions specifically includes the following steps:
[0018] (2.3.1) Set the period of the clock signal as Tread;
[0019] (2.3.2) Set the minimum timing difference between the memory read control logic output signal and the addressing signal in the address register group as a first preset time interval Ta;
[0020] (2.3.3) setting the timing difference between the slowest memory data output signal PDOUT and the memory read control logic output signal to a second preset time interval Tb, under the premise that the memory read control logic output signal is valid;
[0021] (2.3.4) using a static timing analysis tool to analyze the memory read control logic output signal to obtain process parameter analysis;
[0022] (2.3.5) obtaining the timing difference between the same memory read control logic output signal under optimal and worst process parameter conditions.
[0023] Preferably, the setting of the clock signal related synchronization control logic in step (3) is specifically:
[0024] The STA system sets the address register group and the data register group as the clock signal related synchronization control logic according to the input operation of the designer.
[0025] Preferably, the blocking of the clock attribute of the clock signal to generate a normal output signal in step (3) is specifically:
[0026] The STA system blocks the clock attribute of the clock signal at the output end of the blocking buffer to generate a normal output signal according to the input operation of the designer.
[0027] Preferably, the setting of the optimal routing timing interval in step (3) is specifically:
[0028] The STA system sets the optimal routing timing interval from the output of the blocking buffer to the current memory read control logic output signal according to the input operation of the designer.
[0029] More preferably, the setting of the optimal routing timing interval specifically includes the following steps:
[0030] (i) setting the worst routing delay TAmax and the optimal routing delay TAmin in the total delay of the blocking buffer self delay (i.e. the delay required from the input to the output of the blocking buffer) plus the delay required from the input of the blocking buffer to the memory read control logic output signal;
[0031] (ii) and setting the optimal routing delay threshold value as TAmax+Ta, and setting the worst routing delay threshold value as a value less than Tread-Tb-Tc, wherein Tc is a third preset time interval.
[0032] More preferably, the third preset time interval Tc is set by the following way:
[0033] The maximum value of the delay between the data signal DOUT outputted outwards by the memory data output signal PDOUT as the starting point and the DOUT register group as the ending point is set as the third preset time interval Tc.
[0034] The STA-based system adopting the method for realizing the predetermined timing control circuit design for the memory asynchronous interface can reduce the layout and wiring iteration times, reduce the requirement for the back-end personnel, and enhance the process portability of the design method. BRIEF DESCRIPTION OF DRAWINGS
[0035] Figure 1 The logic circuit structure schematic diagram of the method for realizing the predetermined timing control circuit design for the memory asynchronous interface of the STA-based system in an embodiment of the present application.
[0036] Figure 2 The timing relationship schematic diagram of the method for realizing the predetermined timing control circuit design for the memory asynchronous interface of the STA-based system in an embodiment of the present application. DETAILED DESCRIPTION
[0037] In order to more clearly describe the technical content of the present application, the following further describes in combination with specific embodiments.
[0038] Before explaining the embodiments of the application in detail, it should be noted that in the following description, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include these elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices.
[0039] The method for realizing the predetermined timing control circuit design for the memory asynchronous interface of the STA-based system, wherein the method comprises the following steps:
[0040] (1) The designer judges whether the interface timing of the current memory has an asynchronous timing relationship according to the interface timing requirement of the memory, and if yes, executes step (2); otherwise, does not continue to process;
[0041] (2) the designer generates output signal of the address change control register and memory read control logic output signal for the memory, and calculates the timing difference between the clock signal, addressing signal, memory read control logic output signal and memory data output signal under the preset process parameter condition;
[0042] (3) the STA system sets the synchronization control logic related to the clock signal according to the input operation of the designer, blocks the clock attribute of the clock signal to generate a normal output signal, and sets the optimal wiring timing interval;
[0043] (4) the STA system synthesizes the layout and wiring according to the input operation of the designer, and returns the back-visited netlist (GATE NETLIST) of the STA system interface for the scheduled timing verification.
[0044] In a specific embodiment of the present application, the designer performs the following scheduled timing verification process in actual operation in the above step (4):
[0045] The timing analysis tool STA checks whether the joint design of the circuit design and the constraint meets the scheduled timing according to the input of the designer, determines the synthesized netlist, and then returns the back-visited netlist (GATE NETLIST) of the STA system interface for the scheduled timing dynamic simulation verification.
[0046] As a preferred embodiment of the present application, the asynchronous timing relationship in the above step (1) is specifically:
[0047] The timing relationship not subject to the static timing constraint of the clock signal.
[0048] Preferably, the output signal generation process of the address change control register and the memory read control logic output signal generation process in the above step (2) specifically include the following steps:
[0049] (2.1) the designer performs input operation for the memory, compares the addressing signal in the current address register group of the memory with the next address register group, and generates the output signal of the address change control register.
[0050] (2.2) the designer performs logical AND operation on the clock signal and the output signal of the address change control register through the blocking buffer to generate the memory read control logic output signal.
[0051] Preferably, the timing difference between the clock signal, addressing signal, memory read control logic output signal and memory data output signal under the preset process parameter condition in the above step (2) is specifically:
[0052] The designer calculates the timing difference between the clock signal, the addressing signal, the memory read control logic output signal and the memory data output signal under the optimal and worst process parameter conditions respectively.
[0053] As a preferred embodiment of the present application, the step of calculating the timing difference between the clock signal, the addressing signal, the memory read control logic output signal and the memory data output signal under the preset process parameter conditions specifically comprises the following steps:
[0054] (2.3.1) setting the period of the clock signal as Tread;
[0055] (2.3.2) setting the minimum timing difference between the memory read control logic output signal and the addressing signal in the address register group as a first preset time interval Ta;
[0056] (2.3.3) setting the timing difference between the slowest memory data output signal PDOUT and the memory read control logic output signal as a second preset time interval Tb under the premise that the memory read control logic output signal is valid;
[0057] (2.3.4) using a static timing analysis tool to analyze the process library for process parameter analysis on the memory read control logic output signal;
[0058] (2.3.5) obtaining the timing difference between the same memory read control logic output signal under the optimal and worst process parameter conditions.
[0059] As a preferred embodiment of the present application, the step (3) of setting the synchronization control logic related to the clock signal specifically comprises:
[0060] The STA system sets the address register group and the data register group as the synchronization control logic related to the clock signal according to the input operation of the designer.
[0061] As a preferred embodiment of the present application, the step (3) of blocking the clock attribute of the clock signal to generate a normal output signal specifically comprises:
[0062] The STA system blocks the clock attribute of the clock signal at the output end of the blocking buffer to generate a normal output signal according to the input operation of the designer.
[0063] As a preferred embodiment of the present application, the step (3) of setting the optimal routing timing interval specifically comprises:
[0064] The STA system operates according to the input of the designer, and sets an optimal routing time interval of the read control logic output signal from the barrier buffer to the current memory.
[0065] As a preferred embodiment of the present application, the step of setting the optimal routing time interval specifically comprises the following steps:
[0066] (i) setting the worst routing delay TAmax and the optimal routing delay TAmin in the total delay of the delay of the barrier buffer itself (i.e. the delay required from the input to the output of the barrier buffer) and the delay required from the input of the barrier buffer to the read control logic output signal of the memory;
[0067] (ii) setting the optimal routing delay threshold value as TAmax+Ta, and setting the worst routing delay threshold value as a value less than Tread-Tb-Tc, wherein Tc is the third preset time interval.
[0068] As a preferred embodiment of the present application, the third preset time interval Tc is set by the following method:
[0069] Setting the data signal DOUT output from the memory data output signal PDOUT as the starting point, the DOUT register group as the ending point, and the maximum delay between the two points as the third preset time interval Tc.
[0070] A specific embodiment of the present technical solution applied in the OTP asynchronous timing is given below:
[0071] Step 1: The designer determines whether the asynchronous design requirement needs to be added in the design according to the OTP interface timing requirement. For example, Figure 2 As shown in the figure, CLK1 represents the clock signal, A represents the addressing signal, CTRL represents the control logic, and PDOUT represents the memory read control logic output signal. In the actual process of handling the OTP read timing, it is hoped that the controller can throw the instruction address A1 at T1, sample the data D1 corresponding to A1 at T2, throw the instruction address A2 at the same time, sample the data D2 corresponding to A2 at T3, and sample the instruction address A3, and so on. The static constraint on the clock signal CLK1 cycle can only control the period of CLK1, but cannot control the timing requirement between the addressing signal A and the control signal CTRL, and the timing relationship between the memory read control logic output signal PDOUT controlled by the control signal CTRL.
[0072] Step 2: The designer analyzes the data and control signals in the OTP controller, and determines which uses the traditional synchronous timing design and which uses the asynchronous timing design of the present application. For example, Figure 1As shown, the OTP controller address register group generation logic, data register group generation logic, and write control logic register generation logic can all be attributed to the clock signal CLK1 clock domain, and they are considered as synchronous logic, which are implemented using conventional synchronous timing design. When generating the read control signal output logic, the current address register group and the next address register group need to be compared to generate address change generation logic register, and the clock signal CLK1 is passed through a blocking buffer and logically ANDed with the address change generation logic register to serve as the read control logic of the OTP controller. In this way, an asynchronous control read signal can be converted into a clock-related signal, which is indirectly controlled by static timing.
[0073] Step 3: The designed OTP in step 2 cannot meet the timing requirements such as Figure 2 at the same time under optimal and worst process parameter conditions. At this time, we also need to make an agreement on these control signals in the design. The specific agreement conditions are as follows:
[0074] Assuming that the period of the clock signal CLK1 is Tread, the minimum difference between the read control logic signal Read and the address register group A0 must satisfy Ta, and the slowest time for the OTP memory output signal PDOUT to appear is Tb under the condition that the read control logic Read is valid.
[0075] Using a static timing analysis tool to analyze the process library, the difference between the same logic unit (such as DELY, BUF) under optimal and worst process parameter conditions is obtained, which is generally several times the delay of the same logic unit in the worst environment.
[0076] Step 4: In the STA system, the DFF group (i.e., the register) of the address register group A0 and the data register group DIN0 is related to the clock signal CLK1 and is considered as synchronous logic.
[0077] In the STA system, these logics are synchronously constrained, and the specific constraint script is as follows:
[0078] create_clock -period Tread -name CLK1 [get_ports CLK1]
[0079] Step 5: In the STA system, the output end of the blocking buffer is used to block the clock attribute of the clock signal CLK1, so that it only serves as a normal signal transmission. Assuming that the blocking buffer is named BUF1, the specific constraint script is as follows:
[0080] set_clock_sense -logical_stop_propagation -clocks CLK1 [get_pins BUF1 / Z]
[0081] Step 6: Agree on the respective worst and best routing delays from the output of the address register group A0 to the address port A of the memory OTP IP, the relationship of which cannot violate the results obtained in step 2, and record the worst routing delay as TAmax and the best routing delay as TAmin; wherein the delay between the address register group A0 and the memory OTP IP needs to be as short as possible, TAmax = 1, TAmin = 0; and make the following constraints to ensure that the delay between the address register group A0 and the memory OTP IP address port A is less than TAmax, the specific constraint script is as follows:
[0082] set_output_delay (Tread-TAmax) -clock CLK1 -max [get_pins otp_top / otp_ip_wrp_otp_ip / A]
[0083] Step 7: Agree on the worst and best routing delays of the blocking buffer itself and from the blocking buffer input to the OTP read control logic Read in the STA system, take TAmax+Ta as the best delay threshold of the blocking buffer, and take a number slightly smaller than Tread-Tb-Tc as the worst routing delay threshold; Make the following constraints so that TAmax+Ta+Tb+Tc < Tread, and A and Read satisfy the minimum value Ta, the specific constraint script is as follows:
[0084] set_max_delay (Tread-Tb-Tc-2) -rise_from [get_clocks CLK1] -to [get_pins otp_top / otp_ip_wrp_otp_ip / Read]
[0085] set_min_delay (TAmax+Ta) -rise_from [get_clocks CLK1] -to [get_pins otp_top / otp_ip_wrp_otp_ip / Read]
[0086] sef_false_path -fall_from [get_clocks CLK1] -to [get_pins otp_top / otp_ip_wrp_otp_ip / Read]
[0087] Step 8: In the STA system, it is agreed that the OTP IP's DOUT is the starting point and the DOUT DFF group is the ending point, with the maximum delay between them being Tc. The specific constraint script is as follows:
[0088] set_input_delay(Tread-Tc)–clock CLK1–max[get_pins otp_top / otp_ip_wrp_otp_ip / PDOUT]
[0089] set_input_delay 0–clock CLK1–min[get_pins otp_top / otp_ip_wrp_otp_ip / PDOUT]
[0090] Step 9: After synthesis and placement and routing, return to the GATE NETLIST (i.e., the back-visit netlist) for verification.
[0091] Please see Figure 1 As shown, in a specific embodiment of the present invention, when there is no asynchronous timing relationship in the register interface timing, the clock signal directly enters the synchronous processing area and performs combinational logic processing with the address register group, data register group, and write control logic register to directly complete the writing of the output data signal. After the output data signal is combined with the clock signal CLK1 to form a data output register group, it can be used as the register logic for the next access address.
[0092] When there is an asynchronous timing relationship in the register interface, the clock signal needs to be blocked by the output of the blocking buffer. After the clock signal is treated as a normal signal and ANDed with the address change generator register, the final read signal of the OTP register can be obtained at the data output.
[0093] Please see Figure 2 As shown, the method for designing a predetermined timing control circuit for an asynchronous memory interface based on the STA system, which adopts this technical solution, can effectively control the timing relationship between the addressing signal A and the control signal CTRL. This ensures that the data corresponding to each timing of the data output signal PDOUT can fall within the range corresponding to the addressing signal A. In the process of integrated circuit design and development, asynchronous signals can be effectively constrained indirectly to achieve the desired timing requirements.
[0094] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution device.
[0095] Those skilled in the art can understand that all or part of the steps carried out by the above-mentioned embodiment method can be instructed by a program to relevant hardware, and the program can be stored in a computer readable storage medium, and the program includes one of the steps of the method embodiment or a combination thereof when executed.
[0096] In the description of the specification, the description of the terms "an embodiment", "some embodiments", "an example", "a specific example", "an implementation" or "embodiments" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0097] Although the embodiments of the present application have been shown and described above, it is understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present application.
[0098] The STA-based system adopting the method for designing a predetermined timing control circuit for a memory asynchronous interface can convert the asynchronous interface of the memory into a method associated with a synchronous signal, guide the layout tool to automatically select a device under the conditions of optimal and worst process parameters to meet the timing requirements of the asynchronous interface, thereby reducing the number of layout and wiring iterations, reducing the requirements for back-end personnel, and enhancing the portability of the design method in the process.
[0099] In this specification, the present application has been described with reference to its specific embodiments. However, it is obvious that various modifications and changes can be made without departing from the spirit and scope of the present application. Therefore, the specification and drawings should be considered as illustrative rather than limiting.
Claims
1. A method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system, characterized in that, The method includes the following steps: (1) The designer determines whether there is an asynchronous timing relationship between the interface timing of the current memory according to the interface timing requirements of the memory. If there is, step (2) is executed; otherwise, no further processing is performed. (2) The designer performs address change control register output signal generation processing and memory read control logic output signal generation processing for the memory, and calculates the timing differences between the clock signal, addressing signal, memory read control logic output signal and memory data output signal under preset process parameters; wherein, the address change control register output signal generation processing and memory read control logic output signal generation processing in step (2) specifically includes the following steps: (2.1) The designer performs an input operation on the memory, compares the current address register group of the memory with the addressing signal in the next address register group, and generates the output signal of the address change control register; (2.2) The designer performs a logical AND operation between the clock signal and the output signal of the address change control register through a blocking buffer to generate a memory read control logic output signal; (3) The STA system sets up synchronization control logic related to the clock signal according to the designer's input operation, blocks the clock attribute of the clock signal to generate a normal output signal, and sets the optimal wiring timing interval. (4) The STA system performs comprehensive layout and routing based on the designer's input operations and returns the back-visit netlist in the STA system interface for verification of the predetermined timing.
2. The method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system according to claim 1, characterized in that, The asynchronous timing relationship described in step (1) is specifically as follows: Timing relationships that are not subject to static timing constraints by the aforementioned clock signal.
3. The method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system according to claim 1, characterized in that, The step (2) mentioned above, which calculates the timing differences between the clock signal, addressing signal, memory read control logic output signal, and memory data output signal under preset process parameters, specifically involves: The designer calculated the timing differences between the clock signal, addressing signal, memory read control logic output signal, and memory data output signal under optimal and worst process parameter conditions, respectively.
4. The method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system according to claim 3, characterized in that, The calculation of timing differences between clock signals, addressing signals, memory read control logic output signals, and memory data output signals under preset process parameters specifically includes the following steps: (2.3.1) Set the period of the clock signal to Tread; (2.3.2) Set the minimum timing difference between the memory read control logic output signal and the addressing signal in the address register group to the first preset time interval Ta; (2.3.3) Provided that the memory read control logic output signal is valid, the timing difference between the slowest memory data output signal PDOUT and the memory read control logic output signal is set as the second preset time interval Tb. (2.3.4) The process parameters of the memory read control logic output signal are analyzed using a static timing analysis tool and a process library. (2.3.5) Obtain the timing difference between the output signals of the same memory read control logic under the optimal and worst process parameter conditions.
5. The method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system according to claim 1, characterized in that, The synchronization control logic set in step (3) related to the clock signal is specifically as follows: Based on the designer's input, the STA system sets the address register group and data register group to the synchronization control logic related to the clock signal.
6. The method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system according to claim 1, characterized in that, The step (3) of blocking the clock attribute of the clock signal to generate a normal output signal specifically involves: The STA system, based on the designer's input, blocks the clock attribute of the clock signal at the output of the blocking buffer, generating a normal output signal.
7. The method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system according to claim 1, characterized in that, The step (3) of setting the optimal routing timing interval specifically refers to: The STA system sets the optimal routing timing interval from the output of the blocking buffer to the current read control logic output signal of the memory, based on the input operation of the designer.
8. The method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system according to claim 7, characterized in that, The process of setting the optimal routing timing interval specifically includes the following steps: (i) Set the worst-case wiring delay TAmax to the total delay of the blocking buffer itself plus the delay required from the input of the blocking buffer to the output signal of the memory read control logic, and the best-case wiring delay TAmin. (ii) Set the optimal routing delay threshold to TAmax+Ta and the worst routing delay threshold to a value less than Tread-Tb-Tc, where Tc is the third preset time interval.
9. The method for designing a predetermined timing control circuit for an asynchronous memory interface based on a STA system according to claim 8, characterized in that, The third preset time interval Tc is specifically set in the following way: The starting point is set as the data signal DOUT output by the memory data output signal PDOUT, and the ending point is set as the DOUT register group. The maximum value of the delay between the two points is set as the third preset time interval Tc.
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