A fully analog vector-matrix multiplication in-memory calculation circuit and its application

Abstract

The present invention proposes a fully analog vector-matrix multiplication in-memory computing circuit and its application, belonging to the field of in-memory computing technology in semiconductors and CMOS ultra-large-scale integrated circuits. The circuit includes an input circuit, an array, an output clamping circuit, and an analog shift-and-add unit. The input circuit samples and holds the analog input, and then inputs it into the array. The array uses resistive devices to store weights in the form of conductance. According to Kirchhoff's law and Ohm's law, the analog input and conductance are multiplied to complete the vector-matrix multiplication of the input and the weight. The output clamping circuit clamps the array output point to zero level and converts the calculation result in current form into voltage form for output. The analog shift-and-add unit circuit is used to shift and add the calculation results of each column to complete the carry calculation. Unlike traditional in-memory computing circuits that work in a mixed digital-analog computing mode, the present invention works completely in the analog domain, and the area and power consumption problems of the in-memory computing circuit are effectively improved.

Description

Technical Field

[0001] The present invention belongs to the field of process-in-memory (PIM) technology in semiconductors and CMOS ultra-large-scale integrated circuits (ULSI), and in particular relates to a process-in-memory (PIM) circuit that uses full analog computing to perform vector-matrix multiplication operations. Background Art

[0002] With the development of artificial intelligence and deep learning technologies, artificial neural networks have been widely used in fields such as natural language processing, image recognition, autonomous driving, and graph neural networks. However, the increasing size of networks has led to a significant energy consumption in transferring data between memory and traditional computing devices such as CPUs and GPUs, a phenomenon known as the von Neumann bottleneck. The most important computation in artificial neural network algorithms is vector-matrix multiplication (VMM). In-memory computing, which stores weights in memory array cells and performs vector-matrix multiplication within the array, avoids the frequent transfer of data between memory and computing cells and is considered a promising approach to breaking through the von Neumann bottleneck.

[0003] like Figure 1 As shown in Figure 1, in-memory computing typically uses a hybrid digital-analog approach. Memory cells can be volatile memories such as SRAM and DRAM, or non-volatile memories such as Flash, RRAM, PCRAM, and MRAM. Figure 2 This is a traditional vector-matrix multiplication for mixed digital-analog computing. The weights are represented by the device conductance values in the memory array, and the input characteristic map is a digital quantity stored in the digital memory. When implementing vector-matrix multiplication, the characteristic map stored in the digital memory is converted into an analog voltage input array via a DAC. The vector multiplication is performed in the analog domain on the array. The result is represented by the sum of the currents on the bit lines, which is then converted into a digital quantity via an ADC and transferred back to the digital memory for storage.

[0004] However, the area and power consumption of high-precision DACs and ADCs increase exponentially with accuracy. Neural networks typically consist of dozens or even hundreds of layers, and data undergoes analog-to-digital and digital-to-analog (A / D) conversion between each layer, consuming a significant amount of energy. Some work uses pure analog computing, meaning that the analog voltage output of the previous layer is directly used as the input to the next layer without A / D conversion between neural network layers, such as Figure 3 However, in this method, in addition to the analog input and output, analog devices are also required to express high-precision weights.

[0005] The multi-valued manufacturing process for existing resistive devices such as RRAM, PCRAM, and MRAM is still immature. Therefore, in high-precision in-memory computing systems for neural networks, multiple low-precision devices (such as binary devices) are often used to represent each digit of a high-precision weight. However, existing purely analog vector-matrix multiplication solutions still require the use of analog devices and cannot directly utilize more mature low-precision devices (such as binary devices). Furthermore, they do not address how to implement carry and maintain computational accuracy in analog circuits when using low-precision devices. Summary of the Invention

[0006] The present invention aims to use low-precision devices (such as binary devices) to achieve high-precision full-analog vector matrix multiplication, and provides an in-memory computing circuit in a full analog domain. Unlike the traditional in-memory computing that works in a mixed digital-analog computing mode, the circuit works completely in the analog domain, which avoids the frequent digital-to-analog and analog-to-digital conversions in the in-memory computing of complex neural networks. The input no longer needs to be converted into analog quantities through DAC, and the array output no longer needs to be converted into digital quantities using ADC. The area and power consumption problems of the in-memory computing circuit are effectively improved. At the same time, an array composed of low-precision devices with more mature technology is used to achieve high-precision vector matrix multiplication, and each base digit of the high-precision weight is stored in multiple low-precision devices. After completing the vector matrix multiplication in the array, the carry calculation is directly implemented in the analog domain. Compared with the use of analog devices in the traditional pure analog in-memory computing design, the low-precision devices have higher reliability and improve the calculation accuracy.

[0007] Based on this, the technical solution adopted by the present invention is as follows:

[0008] A fully analog vector-matrix multiplication in-memory calculation circuit is characterized in that the circuit includes an input circuit, an array, an output clamping circuit and an analog shift-and-add unit, wherein the input circuit samples and holds analog input data and then inputs the data into the array; the array uses resistive devices to store weights in the form of conductance to complete vector-matrix multiplication of the input and weights; the output clamping circuit clamps the array output point to zero level and converts the calculation result in current form into voltage form for output; the analog shift-and-add unit circuit shifts and adds the calculation results of each column to complete the carry calculation.

[0009] Furthermore, the input circuit is a sample and hold circuit S / H.

[0010] Furthermore, the analog shift-and-add unit includes a column capacitor corresponding to each column in the array, a redundant capacitor, and a voltage follower. The column capacitor is used to temporarily store the calculation results of each column. The redundant capacitor performs weighted summation on the calculation results of each column. The voltage follower is used to output the final shift-and-add result. The column capacitor corresponding to each column in the array is the same size; and the redundant capacitor and the column capacitor are also the same size.

[0011] The present invention also provides a method for calculating a fully analog vector-matrix multiplication in-memory calculation circuit, the steps of which include:

[0012] 1) Analog input data is input into the array through the input circuit;

[0013] 2) According to Kirchhoff's law and Ohm's law, the analog input data completes vector-matrix multiplication with the stored weight values in the array. The output clamp circuit clamps the array output point to zero level and converts the calculation result in current form into voltage form for output;

[0014] 3) The analog shift-add unit includes a column capacitor C corresponding to each column in the array col , and a redundant capacitor C R and the voltage follower, C R With each C col Connect and disconnect to distribute the charge, perform weighted summation on the calculation results of each column, and the voltage follower outputs the final shifted summation result n is the number of column capacitors.

[0015] For N-bit weight calculation, the analog input in step 1) and the array vector matrix multiplication in step 2) can be performed alternately. In step 3), N / 2+1 analog shift-and-add units are used to complete the shift-and-add operation, realizing the pipeline operation of the circuit.

[0016] The fully analog vector-matrix multiplication in-memory calculation circuit proposed by the present invention has the following advantages:

[0017] The fully analog vector-matrix multiplication in-memory calculation circuit operates in the analog domain, eliminating the ADC and DAC included in common in-memory calculation designs. Without frequent A / D conversions, it has significant advantages in terms of energy efficiency and area. By using low-precision devices with more mature processes instead of analog devices, and using multiple low-precision devices to represent a single digit of the weight in the neural network, the calculation accuracy is improved. The proposed analog shift-and-add unit solves the carry calculation problem of low-precision devices in the analog domain during in-memory calculations, maintaining calculation accuracy. The proposed fully analog in-memory calculation circuit, by using multiple analog shift-and-add units, implements a pipelined operation mode, effectively improving calculation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of vector-matrix multiplication based on mixed digital-analog in-memory computing;

[0019] Figure 2 This is a schematic diagram of traditional vector-matrix multiplication based on mixed digital-analog in-memory computing;

[0020] Figure 3Schematic diagram of vector-matrix multiplication using traditional analog devices to achieve pure analog computing;

[0021] Figure 4 A schematic diagram of a circuit for performing full analog vector-matrix multiplication using low-precision devices according to a specific embodiment of the present invention;

[0022] Figure 5 Schematic diagram of the calculation process of the analog shift-and-add unit in a specific embodiment of the present invention;

[0023] Figure 6 Schematic diagram of the pipeline operation of the fully analog vector-matrix multiplication circuit in a specific embodiment of the present invention.

[0024] How it works

[0025] The present invention will be further clearly and completely described below through specific embodiments in conjunction with the accompanying drawings.

[0026] The fully analog vector matrix multiplication in-memory calculation circuit of the present invention includes an input circuit, an array, an output clamping circuit, and an analog shift and addition unit. Among them, the core of the input circuit is a sampling and holding circuit (S / H), which samples and holds the analog input data and then inputs it into the array. The array uses resistive devices and is composed of low-precision devices. The weights are stored in the form of conductance. According to Kirchhoff's law and Ohm's law, the analog input and conductance are multiplied to complete the vector matrix multiplication of the input and the weight. The output clamping circuit (VG) clamps the array output point to zero level and converts the calculation result in the current form into a voltage form for output. Since low-precision devices are used to represent the individual base digits of the weight to improve the calculation accuracy, it is necessary to shift and add the calculation results of each column to complete the carry calculation. In order to solve the carry calculation in the analog domain, an analog shift and addition unit circuit is designed. The analog shift and addition unit includes a column capacitor corresponding to each column in the array, a redundant capacitor and a voltage follower. Column capacitors temporarily store the calculation results of each column, redundant capacitors perform a weighted summation of the results for each column, and voltage followers output the final shift-addition result. The analog shift-add unit performs shift-add on the output calculation results. This circuit eliminates the need for A / D conversion during in-memory calculations and instead utilizes the principles of capacitor charging and charge distribution to perform shift-addition, achieving fully analog, high-precision vector-matrix multiplication.

[0027] The fully analog vector-matrix multiplication in-memory calculation circuit of the present invention can realize the pipeline operation of the circuit. When using a single analog shift-add unit, after the output clamp circuit outputs the array calculation result to the analog shift-add unit for shift-add calculation, there is no new analog input at this time, and no new vector-matrix multiplication is performed in the array, and the input circuit and array are idle. By using (N / 2+1) (N is the number of weight bits) analog shift-add units simultaneously, the analog input and the vector-matrix multiplication in the array can be performed alternately to realize the pipeline operation of the circuit and maximize the circuit calculation efficiency.

[0028] Figure 4 Schematic diagram of a circuit for full analog vector-matrix multiplication in a specific embodiment of the present invention. Figure 4 In the example, four binary devices are used to represent 4-bit weights, W[i] (i＝0-3) For each binary bit of the 4-bit weight, the array has four inputs and four outputs. In the first clock cycle, the analog input is input into the sample-and-hold circuit through the bus. In the second clock cycle, according to Kirchhoff's law and Ohm's law, the analog input completes the vector-matrix multiplication with the stored weight value in the array, and the calculation result is converted from current to voltage through the VG circuit. From the third clock cycle to the sixth clock cycle, the shift addition of the calculation result is completed by the analog shift-add unit. That is, in the analog shift-add unit, C i(i＝0-3) The column capacitors are of the same size and are responsible for temporarily storing the calculation results of each column; C R It is a redundant capacitor with the same capacitance as the capacitors of each column, and is responsible for the weighted sum of the calculation results.

[0029] Figure 5 This is the calculation process of the analog shift-add unit in a specific embodiment of the present invention. First, the first clock cycle performs analog input, and the analog shift-add unit is initialized and all capacitors are reset. The second clock cycle performs vector-matrix multiplication within the array, and the calculation results in current form are converted to voltage form and stored in the column capacitor. In the third clock cycle, C R Connected to C0 for charge redistribution, since the capacitance is the same, the voltage follower output The fourth clock cycle, C R Disconnect from C0 and connect to C1, the voltage follower output In this way, C R Connect and disconnect C0-C3 in turn to distribute the charge. By the sixth clock cycle, the shift addition of the calculation results can be completed. When only one analog shift-and-add unit is used, no new analog input and vector-matrix multiplication is performed from the third clock cycle to the sixth clock cycle.

[0030] To improve computational efficiency, the circuit can implement a pipeline operation mode by using multiple analog shift-and-add units simultaneously, so that the analog input of the first clock cycle and the vector-matrix multiplication of the second clock cycle can be performed alternately. Figure 6 This figure illustrates the pipeline operation of the proposed all-analog vector-matrix multiplication circuit. Again, using 4-bit weights, pipeline operation can be achieved by using three analog shift-and-add units simultaneously. For ease of description, the three analog shift-and-add units are referred to as unit 1, unit 2, and unit 3. When unit 1 enters its third clock cycle, unit 2 simultaneously begins its first clock cycle, and the circuit performs analog input. When unit 1 enters its fourth clock cycle, unit 2 begins its second clock cycle, performing vector-matrix multiplication within the array. Similarly, unit 3 begins its first clock cycle when unit 2 enters its third clock cycle, and its second clock cycle when unit 2 enters its fourth clock cycle. Thus, after unit 1 completes its sixth clock cycle, it can resume its first clock cycle task, i.e., analog input. This cycle repeats, achieving pipeline operation. Furthermore, for applications with N-bit weights, using (N / 2+1) analog shift-and-add units simultaneously can achieve pipeline operation, maximizing computational efficiency.

[0031] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Those skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be based on the claims.

Claims

1. A fully analog vector-matrix multiplication in-memory calculation circuit, characterized in that: The circuit includes an input circuit, an array, an output clamp circuit and an analog shift-addition unit, wherein the input circuit samples and holds analog input data and then inputs the data into the array. The array uses resistive devices to store weights in the form of conductance to complete array vector matrix multiplication of input and weight. The output clamp circuit clamps the array output point to zero level and converts the calculation result in the form of current into voltage for output. The analog shift-addition unit circuit shifts and adds the calculation results of each column to complete the carry calculation. The analog shift-addition unit includes a column capacitor C corresponding to each column in the array. col , and a redundant capacitor C R And the voltage follower, the column capacitor is used to temporarily store the calculation results of each column, the redundant capacitor performs weighted summation on the calculation results of each column, and the voltage follower is used to output the final shift addition result, C R With each C col Connect and disconnect to distribute the charge, perform weighted summation on the calculation results of each column, and the voltage follower outputs the final shifted summation result n is the number of column capacitors. For N-bit weight calculation, the input array and array vector matrix multiplication are performed alternately, and N / 2+1 analog shift-add units are used to complete the shift-add, thereby realizing the pipeline operation of the circuit.

2. The fully analog vector-matrix multiplication in-memory calculation circuit according to claim 1, wherein: The input circuit is a sample-and-hold circuit S / H.

3. The fully analog vector-matrix multiplication in-memory calculation circuit according to claim 1, wherein: The column capacitors corresponding to each column in the array have the same size; and the redundant capacitors and the column capacitors also have the same size.

4. A method for operating the fully analog vector-matrix multiplication in-memory calculation circuit according to claim 1, comprising the steps of: 1) Analog input data is input into the array through the input circuit; 2) According to Kirchhoff's law and Ohm's law, the analog input data completes vector-matrix multiplication with the stored weight values in the array. The output clamp circuit clamps the array output point to zero level and converts the calculation result in current form into voltage form for output; 3) The analog shift-add unit includes a column capacitor C corresponding to each column in the array col , and a redundant capacitor C R and the voltage follower, C R With each C col Connect and disconnect to distribute the charge, perform weighted summation on the calculation results of each column, and the voltage follower outputs the final shifted summation result n is the number of column capacitors; 4) For the N-bit weight calculation, the analog input of step 1) and the array vector matrix multiplication of step 2) are performed alternately, and step 3) uses N / 2+1 analog shift-add units to complete the shift-add, realizing the pipeline operation of the circuit.

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