Circuit module with improved connection loads

Abstract

A circuit module with improved line loading includes a first line, a first switch, a second line, a second switch, and a second driver. The first switch is openable and closable to turn on and off between the first line and a first node. The second switch is openable and closable to turn on and off between the second line and the first node. The second driver is coupled to the second line and is enableable and disableable to drive the second line and stop driving the second line, respectively, in accordance with a voltage of a second node. The voltage of the second node is controlled by a voltage of the first node. When the first switch is open, the second switch is closed. When the second switch is closed, the second driver is enabled.

Description

TECHNICAL FIELD

[0001] The present application relates to a circuit module with improved load on the short lines, and more particularly to a circuit module including an intermediate circuit and organizing a plurality of internal circuit blocks into different groups by different short lines, when there is a signal transmission on one of the short lines, the intermediate circuit can latch and drive the signal to other short lines. BACKGROUND

[0002] Various circuit modules, such as memory modules, are important building blocks of integrated circuits (semiconductor chips).

[0003] Figure 1a With Figure 1b A prior art memory module 100 and the waveforms of the related signals are shown respectively. As shown in Figure 1a The prior art memory module 100 includes memory banks bk1 to bk4, a long line L0 and a control and input / output circuit gctrl_io_0. The line L0 extends across the memory banks bk1 to bk4 to couple the memory banks bk1 to bk4, and is coupled to the control and input / output circuit gctrl_io_0 at a node QBI_M0. Through the line L0, each memory bank bk1 to bk4 can transmit the data stored therein to the control and input / output circuit gctrl_io_0. The control and input / output circuit gctrl_io_0 controls the operation timing of the circuit module 100 according to a clock CK0, and the timing control includes providing a signal SAT0 to the memory banks bk1 to bk4 to control the timing of the memory banks bk1 to bk4 to transmit data.

[0004] In Figure 1bIn the above-mentioned prior art, the period T0 represents one period of the clock CK0, and the waveform vL0 represents the voltage waveform of the line L0 at the node QBI_M0. When one of the memory banks bk1 to bk4 is to transmit a data to the control and input / output circuit gctrl_io_0 via the line L0, the line L0 is driven according to the data content when the signal SAT0 is at the voltage v_on, and the driving of the line L0 is stopped when the signal SAT0 is switched to the other voltage v_off. For example, in a period from time point tp1 to tp2, the signal SAT0 is switched from the voltage v_off to the voltage v_on at time point t11, and switched back to the voltage v_off at time point t13. Correspondingly, assuming that the memory bank bk2 is to transmit a bit of data of digital 0 to the control and input / output circuit gctrl_io_0 in this period, the memory bank bk2 starts to drive the line L0 after time point t11, and pulls the voltage of the line L0 to the voltage v0 representing digital 0 at time point t12, as shown in the waveform vL0. According to the voltage of the line L0, the control and input / output circuit gctrl_io_0 can determine the data transmitted by the memory bank bk2. After time point t13, the signal SAT0 returns to the voltage v_off, and the memory bank bk2 (as well as the other memory banks bk1, bk3 and bk4) stops driving the line L0.

[0005] Similarly, in a next period from time point tp2 to tp3, the signal SAT0 is switched from the voltage v_off to the voltage v_on at time point t21, and switched back to the voltage v_off at time point t23. Assuming that the memory bank bk3 is to transmit a bit of data of digital 1 to the control and input / output circuit gctrl_io_0 in this period, the memory bank bk3 starts to drive the line L0 after time point t21, and pulls the voltage of the line L0 to the voltage v1 representing digital 1 at time point t22. After time point t23, the memory bank bk3 (as well as the other memory banks bk1, bk2 and bk4) stops driving the line L0.

[0006] The disadvantages of the above-mentioned prior art can be summarized as follows. First, because the line L0 needs to extend across all the four memory banks bk1 to bk4, its length is relatively long. For example, if each of the memory banks bk1 to bk4 contains a memory array of 512 word lines, the line L0 needs to extend across 512*4 = 2048 word lines in total. Because the line L0 is relatively long, its equivalent load is also relatively high, and the time taken for one of the memory banks bk1 to bk4 to drive the line L0 to the desired voltage (e.g. time points t11 to t12 or t21 to t22) is also relatively long; as a result, the speed (frequency) of accessing data is difficult to increase. Furthermore, the driving circuit in each of the memory banks bk1 to bk4 for driving the line L0 also occupies a relatively large layout area to provide sufficient driving force.

[0007] Furthermore, when signal SAT0 switches from voltage v_off to voltage v_on (e.g., at times t11 and t21), causing one of the storage units bk1 to bk4 to begin driving connection L0, once signal SAT0 switches back from voltage v_on to voltage v_off (e.g., at times t13 and t23), the voltage of connection L0 is no longer driven and begins to float, neither the voltage v0 of digital 0 nor the voltage v1 of digital 1. Figure 1b As shown, between time points t13 and t21, since signal SAT0 is voltage v_off, storage libraries bk1 to bk4 do not drive connection L0. Therefore, the voltage of connection L0 will drift to an uncertain voltage vf0 between voltage v0 and v1, and cannot be maintained at voltage v0 or v1. Consequently, the data hold-time of node QBI_M0 will also be insufficient. Summary of the Invention

[0008] One object of the present invention is to provide a circuit module (e.g., 200) with improved interconnect load. Figure 2 The circuit module may include a first connection and a second connection (e.g., L1 and L2). Figure 2 and Figure 4 The system comprises a first switch, a second switch (e.g., s1 and s2), and a second driver (e.g., d2). The first switch is coupled between the first connection and a first node (e.g., QBI), and can be turned on and off to conduct or de-conduct between the first connection and the first node. The second switch is coupled between the second connection and the first node, and can be turned on and off to conduct or de-conduct between the second connection and the first node. The second driver may include a second driver input (e.g., i2) and a second driver output (e.g., o2), respectively coupled to a second node (e.g., QBII) and the second connection. The second driver can be enabled and disabled to drive or stop driving the second connection based on the voltage of the second node. The voltage of the second node is controlled by the voltage of the first node. When the first switch is on, the second switch can be off; when the second switch is on, the first switch can be off. The second driver is enabled when the second switch is closed; the second driver is disabled when the second switch is open.

[0009] In one embodiment, the circuit module may further include a buffer (e.g., b1, Figure 2 and Figure 4 The buffer may include a buffer input (e.g., i3) and a buffer output (e.g., o3), respectively coupled to the first node and the second node. In one embodiment, the buffer may further include a first inverter (e.g., iv1, ...). Figure 4 ), which is coupled between the input and output of the buffer.

[0010] In one embodiment, the circuit module may further include one or more first circuit blocks (e.g., BK[M0+1] to BK[M], Figure 2 The first connection is coupled to the first circuit block. When one of the one or more first circuit blocks needs to transmit data, the first switch is turned on (e.g., at time tu1). Figure 5 Then, the first connection is driven based on this data (e.g., at time ta1), and the driving of the first connection is stopped before the first switch is switched off (e.g., at time tu2) (e.g., at time ta3). In one embodiment, each of the first circuit blocks may be a memory bank. In one embodiment, the circuit module may also include a latch (e.g., h1, Figure 2 and Figure 4 ), coupled to the first node. When one of the one or more first circuit blocks stops driving the first connection (e.g., at time point ta3, Figure 5 After that, the latch will maintain the voltage of the first node, so that the voltage of the first node does not fluctuate.

[0011] In one embodiment, the latch may include a third inverter and a fourth inverter (e.g., IV3 and IV4). Figure 4 The third inverter may include a third inverter input and a third inverter output, respectively coupled to the first node and an internal node (e.g., n0). The fourth inverter may include a fourth inverter input and a fourth inverter output, respectively coupled to the internal node and the first node.

[0012] In one embodiment, during a time period (e.g., from time point tu2 to t2), Figure 5 Both the first switch and the second switch are closed.

[0013] In one embodiment, the circuit module may further include one or more second circuit blocks (e.g., BK[1] to BK[M0], Figure 2 The second connection is coupled to the second circuit block. When one of the one or more second circuit blocks needs to transmit data, the second switch is turned on (e.g., at time td1). Figure 5 The second connection is then driven based on this data (e.g., at time tb1), and the driving of the second connection is stopped before the second switch is switched off (e.g., at time td2) (e.g., at time tb3). In one embodiment, each of the second circuit blocks may be a repository.

[0014] In one embodiment, the circuit module may further include a first driver (e.g., d1, Figure 2 and Figure 4The first driver may include a first driver input (e.g., i1) and a first driver output (e.g., o1), respectively coupled to the second node and the first connection. The first driver can be enabled and disabled to drive and stop driving the first connection according to the voltage of the second node. Specifically, the first driver is enabled when the first switch is closed and disabled when the first switch is open.

[0015] In one embodiment (e.g.) Figure 4 The first driver may further include a first transistor, a second transistor, a seventh transistor, and an eighth transistor (e.g., N1, N2, P1, and P2). Figure 4 The first transistor may include a first controlled terminal (e.g., a gate terminal) and a first channel terminal (e.g., n1). The second transistor may include a second controlled terminal and two second channel terminals (e.g., a source terminal and a drain terminal), the two second channel terminals being respectively coupled to the first channel terminal and the first driver output terminal. The eighth transistor may include an eighth controlled terminal and an eighth channel terminal (e.g., n2). The seventh transistor may include a seventh controlled terminal and two seventh channel terminals, the two seventh channel terminals being respectively coupled to the eighth channel terminal and the first driver output terminal. One of the first controlled terminal and the second controlled terminal is coupled to the first driver input terminal, and the other of the first controlled terminal and the second controlled terminal is coupled to a first inverting selection signal (e.g., LC34b). One of the seventh controlled terminal and the eighth controlled terminal is coupled to the first driver input terminal, and the other of the seventh controlled terminal and the eighth controlled terminal is coupled to a first selection signal (e.g., LC34); the first selection signal and the first inverting selection signal are inverted.

[0016] In one embodiment (e.g.) Figure 4 The first switch may include a fifth transistor (e.g., N5). Figure 4 The fifth transistor may include a fifth controlled terminal and two fifth channel terminals, respectively coupled to the first selection signal, the first node, and the first connection. The eleventh transistor may include an eleventh controlled terminal and two eleventh channel terminals, respectively coupled to the first inverting selection signal, the first node, and the first connection.

[0017] In one embodiment (e.g.) Figure 4 The second driver may also include a third transistor, a fourth transistor, a ninth transistor, and a tenth transistor (e.g., N3, N4, P3, and P4). Figure 4The third transistor may include a third controlled terminal and a third channel terminal (e.g., n3). The fourth transistor may include a fourth controlled terminal and two fourth channel terminals, the two fourth channel terminals being coupled to the third channel terminal and the second driver output terminal, respectively. The tenth transistor may include a tenth controlled terminal and a tenth channel terminal (e.g., n4). The ninth transistor may include a ninth controlled terminal and two ninth channel terminals, the two ninth channel terminals being coupled to the tenth channel terminal and the second driver output terminal, respectively. One of the third and fourth controlled terminals is coupled to the second driver input terminal, and the other of the third and fourth controlled terminals is coupled to a second inverting selection signal (e.g., LC12b). One of the ninth and tenth controlled terminals is coupled to the second driver input terminal, and the other of the ninth and tenth controlled terminals is coupled to a second selection signal (e.g., LC12); the second selection signal and the second inverting selection signal are inverted.

[0018] In one embodiment (e.g.) Figure 4 The second switch may include a sixth transistor (e.g., N6). Figure 4 The sixth transistor may include a sixth controlled terminal and two sixth channel terminals, respectively coupled to the second selection signal, the first node, and the second connection. The twelfth transistor may include a twelfth controlled terminal and two twelfth channel terminals, respectively coupled to the second inverting selection signal, the first node, and the second connection.

[0019] To provide a preferred understanding of the above and other aspects of the present invention, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0020] (Prior art) Figure 1a and Figure 1b The waveform timing of an existing storage module and related signals are illustrated respectively.

[0021] Figure 2 The diagram shows a circuit module according to an embodiment of the present invention, which may include an intermediate circuit.

[0022] Figures 3a to 3e Indication Figure 2 An example of the operation of the circuit module.

[0023] Figure 4 It means Figure 2 A circuit embodiment of the intermediate circuit in the example.

[0024] Figure 5 It means Figure 2 and Figure 4 The waveform timing of the relevant signals.

[0025] Symbol Explanation

[0026] 100: Storage Module

[0027] 200: Circuit Module

[0028] 210: Intermediate Circuit

[0029] b1-b2: Buffer

[0030] d1-d2: Drivers

[0031] s1-s2: Switches

[0032] h1: latch

[0033] bk1-bk4: Repository

[0034] BK[1]-BK[M], BK[m'], BK[M0], BK[M0+1], BK[m]: Circuit blocks

[0035] L0-L2: Connection

[0036] SAT0, SAT: Signals

[0037] LC12, LC34: Selection signals

[0038] LC12b, LC34b: Inverting selection signals

[0039] CK0, CK: Clock

[0040] gctrl_io_0, gctrl_io: Control and input / output circuits

[0041] P1-P6, N1-N6: Transistors

[0042] iv1-iv4: Inverters

[0043] v_on, v_off, v0, v1, vf0, VCCAPI, VG: Voltage

[0044] vQBI_U, vQBI_D, vQBI: waveform

[0045] tp1-tp3, t11-t13, t21-t23, t1-t3, ta1-ta3, tu1-tu2, tb1-tb3, td1-td2: time point

[0046] T0, T1: Period

[0047] QBI_M0, QBI_M, QBI_U, QBI_D, QBI, QBII, n0-n6, n5b-n6b: nodes

[0048] i1 - i4: Input terminals

[0049] o1 - o4: Output terminals Detailed implementation manners

[0050] Figure 2 FIG. schematically shows a circuit module 200 according to an embodiment of the present invention, which may include M circuit blocks BK[1] to BK[M] and a control and input / output circuit gctrl_io; to implement the technology of the present invention, the circuit module 200 further includes an intermediate circuit 210 and two connections L1 and L2. For example, the circuit module 200 may be a storage module, and each of the circuit blocks BK[1] to BK[M] in the circuit blocks may be a storage bank, including a storage array (not shown), such as a static random access storage array of 512 word lines. The circuit blocks BK[1] to BK[M] can be organized into two groups, where the circuit blocks BK[M0 + 1] to BK[M] ((M0 + 1) < M) are a first group, and are coupled to the node QBI_U of the intermediate circuit 210 via the connection L1; the circuit blocks BK[1] to BK[M0] are a second group, and are coupled to the node QBI_D of the intermediate circuit 210 via the connection L2. Herein, the numbers M0 and M may be two preset integers; in one implementation, the number M may be twice the number M0 (M = 2 * M0). For example, the numbers M0 and M may be 2 and 4 respectively; that is, the circuit module 200 may include four circuit blocks BK[1] to BK[4], where the circuit blocks BK[3] and BK[4] are a group and are coupled to the connection L1; the circuit blocks BK[1] and BK[2] are another group and are coupled to the connection L2.

[0051] The intermediate circuit 210 is coupled to the control and input / output circuit gctrl_io at the node QBI_M. The circuit blocks BK[1] to BK[M0] can transmit data to the control and input / output circuit gctrl_io via the connection L2 and the intermediate circuit 210; the circuit blocks BK[M0 + 1] to BK[M] can transmit data to the control and input / output circuit gctrl_io via the connection L1 and the intermediate circuit 210. The control and input / output circuit gctrl_io controls the operation timing of the circuit module 200 according to a clock CK, and this timing control may include: providing a signal SAT to the circuit blocks BK[1] to BK[M] to control the timing of data transmission of each of the circuit blocks BK[1] to BK[M].

[0052] As Figure 2As shown, the intermediate circuit 210 may include two switches s1 and s2, two drivers d1 and d2, a latch h1, and two buffers b1 and b2. Switch s1 is coupled between node QBI_U and node QBI of line L1 and can be turned on and off; when on, switch s1 conducts between line L1 and node QBI, and when off, switch s1 deconducts between line L1 and node QBI. Switch s2 is coupled between node QBI_D and node QBI of line L2 and can be turned on and off; when on, switch s2 conducts between line L2 and node QBI, and when off, switch s2 deconducts between line L2 and node QBI.

[0053] Driver d1 includes an input terminal i1 and an output terminal o1, which are coupled to node QBII and node QBI_U of line L1, respectively. Driver d1 can be enabled and disabled; when enabled, driver d1 can drive the voltage of line L1 according to the voltage of node QBII; when disabled, driver d1 can stop driving the voltage of line L1. Driver d2 includes an input terminal i2 and an output terminal o2, which are coupled to node QBII and node QBI_D of line L2, respectively. Driver d2 can be enabled and disabled; when enabled, driver d2 can drive the voltage of line L2 according to the voltage of node QBII; when disabled, driver d2 can stop driving the voltage of line L2.

[0054] Buffer b1 includes an input terminal i3 and an output terminal o3, coupled to nodes QBI and QBII respectively. It can drive the voltage of node QBII according to the voltage of node QBI, so that the voltage of node QBII is controlled by the voltage of node QBI. Buffer b2 includes an input terminal i4 and an output terminal o4, coupled to nodes QBII and QBI_M respectively. It can drive the voltage of node QBI_M according to the voltage of node QBII. Latch h1 is coupled to node QBI.

[0055] continue Figure 2 , Figures 3a to 3e This illustration shows an operational embodiment of circuit module 200. For example... Figure 3aAs shown, when the control and input circuit gctrl_io requests one of the circuit blocks BK[m] from BK[M0+1] to BK[M] to transmit a first data (not shown) to the control and input circuit gctrl_io, switch s1 will open, switch s2 will close, driver d1 will be disabled, and driver d2 will be enabled. After switch s1 is opened, circuit block BK[m] can drive the voltage of connection L1 (and node QBI_U) according to the content of the first data; the opened switch s1 will conduct the voltage of node QBI_U to node QBI, latch h1 will latch the voltage of node QBI, buffer b1 will drive the voltage of node QBII according to the voltage of node QBI, and buffer b2 will drive the voltage of node QBI_M according to the voltage of node QBII, so that the control and input circuit gctrl_io can determine and receive the first data transmitted by circuit block BK[m] according to the voltage of node QBI_M. At the same time, the enabled driver d2 will also drive the voltage of connection L2 according to the voltage of node QBII, so that the voltage of connection L2 is controlled by the voltage of connection L1 (for example, making the voltage of connection L2 consistent with the voltage of connection L1).

[0056] like Figure 3b As shown, when circuit block BK[m] stops driving connection L1 and other circuit blocks also do not drive connections L1 and L2, switch s1 can be open, switch s2 can be closed, driver d1 is disabled, and driver d2 is enabled. Through node QBI and the open switch s1, the voltage of node QBI_U and connection L1 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffer b1 and the enabled driver d2, the voltage of node QBI_D and connection L2 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffers b1 and b2, the voltage of node QBI_M is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same).

[0057] like Figure 3c As shown, when all circuit blocks BK[1] to BK[M] are not driving connections L1 and L2, switches s1 and s2 can also be closed, while drivers d1 and d2 can be enabled. Through buffer b1 and the enabled driver d1, the voltage of node QBI_U and connection L1 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffer b1 and the enabled driver d2, the voltage of node QBI_D and connection L2 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffers b1 and b2, the voltage of node QBI_M is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same).

[0058] like Figure 3dAs shown, when the control and input circuit gctrl_io requests one of the circuit blocks BK[m'] from BK[1] to BK[M0] to transmit a second data (not shown) to the control and input circuit gctrl_io, switch s2 will be turned on, switch s1 will be turned off, driver d1 will be enabled, and driver d2 will be disabled. After switch s2 is turned on, circuit block BK[m'] can drive the voltage of connection L2 (and node QBI_D) according to the content of the second data. The turned-on switch s2 will conduct the voltage of node QBI_D to node QBI, latch h1 will latch the voltage of node QBI, buffer b1 will drive the voltage of node QBII according to the voltage of node QBI, and buffer b2 will drive the voltage of node QBI_M according to the voltage of node QBII, so that the control and input circuit gctrl_io can judge and receive the second data transmitted by circuit block BK[m'] according to the voltage of node QBI_M. At the same time, the enabled driver d1 will also drive the voltage of connection L1 according to the voltage of node QBII, so that the voltage of connection L1 is controlled by the voltage of connection L2 (for example, make the voltage of connection L1 consistent with the voltage of connection L2).

[0059] like Figure 3e As shown, when circuit block BK[m'] stops driving connection L2 and other circuit blocks also do not drive connections L1 and L2, switch s1 can be closed, switch s2 can be open, driver d1 is enabled, and driver d2 is disabled. Through node QBI and the open switch s2, the voltage of node QBI_D and connection L2 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffer b1 and the enabled driver d1, the voltage of node QBI_U and connection L1 is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same). Through buffers b1 and b2, the voltage of node QBI_M is controlled by the latch voltage of latch h1 (e.g., the two voltages are the same).

[0060] continue Figure 2 , Figure 4 The diagram illustrates a circuit embodiment of intermediate circuit 210. Driver d1 may include transistors P1, P2, N1, and N2; driver d2 may include transistors P3, P4, N3, and N4; switch s1 may include transistors P5 and N5; and switch s2 may include transistors P6 and N6. Transistors P1 to P6 may be p-type metal-oxide-semiconductor transistors, and transistors N1 to N6 may be n-type metal-oxide-semiconductor transistors. Buffer b1 may include one (or an odd number) of inverters iv1; buffer b2 may include one (or an odd number) of inverters iv2; and latch h1 may include two inverters iv3 and iv4.

[0061] In driver d1, transistor N1 may include a controlled terminal (e.g., a gate terminal) and two channel terminals (e.g., a source terminal and a drain terminal), respectively coupled to input terminal i1, a voltage VG (e.g., a ground voltage), and node n1. Transistor N2 may include a controlled terminal and two channel terminals; the controlled terminal is coupled to an inverting selection signal LC34b at node n5b, and the two channel terminals are respectively coupled to node n1 and output terminal o1. Transistor P1 may include a controlled terminal and two channel terminals; the controlled terminal is coupled to a selection signal LC34 at node n5, and the two channel terminals are respectively coupled to node n2 and output terminal o1. Transistor P2 may include a controlled terminal and two channel terminals, respectively coupled to input terminal i1, a voltage VCCAPI (e.g., a supply voltage), and node n2. The selection signal LC34 and the inverting selection signal LC34b are inverted.

[0062] In driver d2, transistor N3 may include a controlled terminal and two channel terminals, respectively coupled to input terminal i2, voltage VG, and node n3. Transistor N4 may include a controlled terminal and two channel terminals; the controlled terminal is coupled to an inverting selection signal LC12b at node n6b, and the two channel terminals are respectively coupled to node n3 and output terminal o2. Transistor P3 may include a controlled terminal and two channel terminals; the controlled terminal is coupled to a selection signal LC12 at node n6, and the two channel terminals are respectively coupled to node n4 and output terminal o2. Transistor P4 may include a controlled terminal and two channel terminals, respectively coupled to input terminal i2, voltage VCCAPI, and node n4. The selection signal LC12 and the inverting selection signal LC12b are inverted.

[0063] In switch s1, transistor N5 may include a controlled terminal and two channel terminals, respectively coupled to the selection signal LC34, node QBI, and node QBI_U of connection L1. Transistor P5 may include a controlled terminal and two channel terminals, respectively coupled to the inverting selection signal LC34b, node QBI, and node QBI_U of connection L1. In switch s2, transistor N6 may include a controlled terminal and two channel terminals, respectively coupled to the selection signal LC12, node QBI, and node QBI_D of connection L2. Transistor P6 may include a controlled terminal and two channel terminals, respectively coupled to the inverting selection signal LC12b, node QBI, and node QBI_D of connection L2. When the control and input / output circuit gctrl_io( Figure 2 When data is required to be transmitted in one of the circuit blocks BK[1] to BK[M], the selection signal LC34 can reflect whether the circuit block belongs to the first group (i.e., circuit blocks BK[M0+1] to BK[M]) and the selection signal LC12 can reflect whether the circuit block belongs to the second group (i.e., circuit blocks BK[1] to BK[M0]).

[0064] In buffer b1, inverter iv1 may include an input terminal and an output terminal, coupled to input terminal i3 and output terminal o3, respectively. In buffer b2, inverter iv2 may include an input terminal and an output terminal, coupled to input terminal i4 and output terminal o4, respectively. In latch h1, inverter iv3 may include an input terminal and an output terminal, coupled to node QBI and node n0, respectively; inverter iv4 may include an input terminal and an output terminal, coupled to node n0 and QBI, respectively.

[0065] continue Figure 2 , Figures 3a to 3e and Figure 4 , Figure 5 This diagram illustrates the waveform timing of relevant signals in circuit module 200. Figure 5 In this context, period T1 represents clock CK. Figure 2 In one cycle of ), the waveforms vQBI_U, vQBI_D, and vQBI are the voltage waveforms of nodes QBI_U, QBI_D, and QBI, respectively. In one cycle T1 from time t1 to t2, if the control and input / output circuit gctrl_io requires one of the circuit blocks BK[M0+1] to BK[M], then BK[m](… Figure 2 Transmit data, select the voltage of signal LC34 ( Figure 5 At time tu1, the voltage will switch from v_off to v_on, indicating that the circuit block BK[m] belongs to the first group; the selection signal LC12 will be v_off, indicating that the circuit block BK[m] does not belong to the second group.

[0066] When the selection signal LC34 is the voltage v_off, transistor N5 ( Figure 4 When transistors P5 and P6 are off (not conducting), transistors P1 and N2 are on (conducting), so switch S1 is off and driver D1 is enabled. Similarly, when the selection signal LC12 is voltage v_off, transistors N6 and P6 are off, while transistors P3 and N4 are on, so switch S2 is off and driver D2 is enabled. On the other hand, when the selection signal LC34 switches to voltage v_on at time tu1, transistors N5 and P5 are on, while transistors P1 and N2 are off, so switch S1 is on and driver D1 is disabled.

[0067] like Figure 5As shown, after the selection signal LC34 switches to voltage v_on at time tu1, the signal SAT will switch from voltage v_off to v_on at time ta1, causing circuit block BK[m] to start driving the voltage of connection L1 according to the data it wants to transmit. For example, if the data that circuit block BK[m] wants to transmit is the number 0, circuit block BK[m] can start driving the voltage of connection L1 (and node QBI_U) towards the voltage v0 representing the number 0 at time ta1, and make the voltage of node QBI_U reach voltage v0 at time ta2, as shown in the waveform vQBI_U.

[0068] After time point tu1, switch s1 is turned on, switch s2 is turned off, driver d1 is disabled, and driver d2 is enabled, as follows: Figure 3a As shown. Therefore, the voltage of node QBI_U will be conducted to node QBI via the open switch s1, causing the voltage of node QBI to reflect the voltage of node QBI_U, as shown in the waveform vQBI( Figure 5 As shown in the diagram. Furthermore, buffer b1 and the enabled driver d2 cause the voltage of node QBI_D and connection L2 to reflect the voltage of node QBI, as shown by the waveform vQBI_D; and buffers b1 and b2 also cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, when connection L1 and node QBI_U are driven to voltage v0 at time ta2, the voltages of nodes QBI, QBI_D, QBI_M, and connection L2 will also become voltage v0. Thus, the digital 0 data transmitted by circuit block BK[m] on connection L1 will be transmitted to the control and input / output circuit gctrl_io via node QBI_M, and to connection L2 via node QBI_D. At time ta2, as nodes QBI_U and QBI are driven to voltage v0, the voltage v0 of node QBI will also be latched to latch h1.

[0069] At time ta3, after time ta2, the signal SAT switches from voltage v_on back to voltage v_off, therefore circuit block BK[m] stops driving connection L1. However, as Figure 3b As shown, since latch h1 has latched voltage v0, the voltage of node QBI will remain at voltage v0. The open switch s1 causes the voltage of node QBI_U and connection L1 to reflect the voltage of node QBI. Buffer b1 and the enabled driver d2 cause the voltage of node QBI_D and connection L2 to reflect the voltage of node QBI. Buffers b1 and b2 cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, even if circuit block BK[m] no longer drives connection L1 after time point ta3, the voltages of connections L1, L2, and node QBI_M will remain at voltage v0 and will not fluctuate.

[0070] At time tu2, following time ta3, the selection signal LC34 switches from voltage v_on back to voltage v_off. After time tu2, since both selection signals LC12 and LC34 are at voltage v_off, switches s1 and s2 are both off, and both drivers d1 and d2 are enabled. Figure 3c As shown. Buffer b1 and enable driver d1 cause the voltage between node QBI_U and connection L1 to reflect the voltage latched by latch h1 on node QBI. Buffer b1 and enable driver d2 cause the voltage between node QBI_D and connection L2 to reflect the voltage of node QBI. Buffers b1 and b2 cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, after time point tu2, the voltage between connections L1 and L2 and node QBI_M remains at voltage v0 and does not fluctuate.

[0071] In another cycle T1 between time points t2 and t3, if the control and input / output circuit gctrl_io requires one of the circuit blocks BK[1] to BK[M0], BK[m']( Figure 2 Transmit data, select the voltage of signal LC12 ( Figure 5 At time td1, the voltage V_off will switch to V_on, indicating that circuit block BK[m'] belongs to the second group; the selection signal LC34 will be at voltage V_off, indicating that circuit block BK[m'] does not belong to the first group. When the selection signal LC12 switches to voltage V_on at time td1, transistors N6 and P6 ( Figure 4 When s2 is turned on, transistors P3 and N4 are turned off, so switch s2 is turned on and driver d2 is disabled.

[0072] After time point td1, the signal SAT will switch from voltage v_off to v_on at time point tb1, causing circuit block BK[m'] to begin driving the voltage of connection L2 according to the data it wants to transmit. For example, if the data that circuit block BK[m'] wants to transmit is the number 1, circuit block BK[m'] can start driving the voltage of connection L2 (and node QBI_D) towards the voltage v1 representing the number 1 after time point tb1, and make the voltage of node QBI_D reach voltage v1 at time point tb2, as shown in the waveform vQBI_D.

[0073] After time point td1, switch S1 is closed, switch S2 is opened, driver D1 is enabled, and driver D2 is disabled. Figure 3d As shown. Therefore, the voltage of node QBI_D will be conducted to node QBI via the open switch s2, causing the voltage of node QBI to reflect the voltage of node QBI_D, as shown in the waveform vQBI( Figure 5As shown in the diagram. Furthermore, buffer b1 and the enabled driver d1 cause the voltage of node QBI_U and connection L1 to reflect the voltage of node QBI, as shown by the waveform vQBI_U; and buffers b1 and b2 also cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, when connection L2 and node QBI_D are driven to voltage v1 at time tb2, the voltages of nodes QBI, QBI_U, QBI_M, and connection L1 will also become voltage v1. Thus, the digital 1 data transmitted by circuit block BK[m'] on connection L2 will be transmitted to the control and input / output circuit gctrl_io via node QBI_M, and to connection L1 via node QBI_U. At time tb2, as nodes QBI_D and QBI are driven to voltage v1, the voltage v1 of node QBI will also be latched to latch h1.

[0074] At time tb3, after time tb2, the signal SAT switches from voltage v_on back to voltage v_off, therefore circuit block BK[m'] stops driving connection L2. However, as Figure 3e As shown, since latch h1 has latched voltage v1, the voltage of node QBI will remain at voltage v1. The open switch s2 causes the voltage of node QBI_D and connection L2 to reflect the voltage of node QBI. Buffer b1 and the enabled driver d1 cause the voltage of node QBI_U and connection L1 to reflect the voltage of node QBI. Buffers b1 and b2 cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, even if circuit block BK[m'] no longer drives connection L2 after time point tb3, the voltages of connections L1, L2, and node QBI_M will still remain at voltage v1 and will not fluctuate.

[0075] At time td2, after time tb3, the selection signal LC12 switches from voltage v_on back to voltage v_off. After time td2, since both selection signals LC12 and LC34 are at voltage v_off, switches s1 and s2 are both off, and both drivers d1 and d2 are enabled. Figure 3c As shown. Buffer b1 and the enabling driver d1 cause the voltage between node QBI_U and connection L1 to reflect the voltage latched by latch h1 on node QBI. Buffer b1 and the enabling driver d2 cause the voltage between node QBI_D and connection L2 to reflect the voltage of node QBI. Buffers b1 and b2 cause the voltage of node QBI_M to reflect the voltage of node QBI. Therefore, after time point td2, the voltage between connections L1 and L2 and node QBI_M remains at voltage v1 and does not fluctuate.

[0076] In summary, the advantages of the present invention compared to the prior art can be described as follows. In the circuit module 200 of the present invention, although circuit blocks BK[1] to BK[M] are all coupled to the control and input circuit gctrl_io, the circuit blocks BK[1] to BK[M] are not coupled to the control and input circuit gctrl_io with a long connecting line that spans all circuit blocks BK[1] to BK[M]. Instead, the circuit blocks BK[1] to BK[M] are divided into a first group (circuit blocks BK[M0+1] to BK[M]) and a second group (circuit blocks BK[1] to BK[M0]), which are respectively coupled to the intermediate circuit 210 via short connecting lines L1 and L2, and then coupled to the control and input circuit gctrl_io from the intermediate circuit 210. Under this architecture, the connections L1 and L2 do not need to span all circuit blocks BK[1] to BK[M], but only some of the circuit blocks. Therefore, the lengths of the connections L1 and L2 are shorter, and their equivalent loads are also lower. The time required for one of the circuit blocks BK[1] to BK[M] to drive the corresponding connection L1 or L2 can also be shortened, thereby improving the speed of data access. Furthermore, due to the reduced connection load, the layout area of ​​the driving circuits used to drive the corresponding connections L1 or L2 in the circuit blocks BK[1] to BK[M] can also be reduced.

[0077] When one of the circuit blocks BK[1] to BK[M] (such as Figure 3a or Figure 3d When the circuit block BK[m] or BK[m'] needs to transmit data to the control and input / output circuit gctrl_io, the circuit block only needs to drive the corresponding short connection (L1 or L2) to the voltage corresponding to the data to enable the control and input / output circuit gctrl_io to receive the data via node QBI_M; even if the other short connection (L2 or L1) is driven to the voltage corresponding to the data later by the intermediate circuit 210, it will not affect the data reception of the control and input / output circuit gctrl_io. That is, the data module 200 of the present invention has a preferred margin in the timing of data access, which also helps to improve the data access speed.

[0078] Furthermore, when the signal SAT( Figure 5 After the voltage v_on drives one of the circuit blocks BK[1] to BK[M] to drive the connection L1 or L2 to the voltage (v0 or v1) corresponding to the data, even if the signal SAT switches back to the voltage v_off and the connection L1 and L2 are no longer driven by the circuit blocks BK[1] to BK[M], the intermediate circuit 210 will still keep the connection L1, L2 and the node QBI_M at the voltage (v0 or v1) corresponding to the data without fluctuation. Figure 3b , 3cAs shown in 3e, this ensures that node QBI_M has sufficient data retention time.

[0079] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and variations without departing from the concept and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the claims.

Claims

1. A circuit module with improved interconnect load, comprising: First connection; A first switch is coupled between the first connection and a first node, and can be turned on and off to conduct or not conduct between the first connection and the first node; First and second connection; A second switch is coupled between the second connection and the first node, and can be turned on and off to conduct or not conduct between the second connection and the first node; as well as A second driver includes a second driver input terminal and a second driver output terminal, respectively coupled to a second node and the second connection; the second driver is capable of enabling and disabling. When the second driver is enabled, it drives the second connection according to the voltage of the second node, so that the voltage of the second connection changes when the voltage of the second node changes; when the second driver is disabled, it stops driving the second connection; wherein: The voltage of the second node is controlled by the voltage of the first node; When the first switch is turned on, the second switch is turned off; and The second driver is enabled when the second switch is closed.

2. The circuit module as described in claim 1, wherein: When the second switch is turned on, the first switch is turned off.

3. The circuit module as described in claim 1, wherein: When the second switch is turned on, the second driver is disabled.

4. The circuit module as described in claim 1, further comprising: A buffer includes a buffer input and a buffer output, which are respectively coupled to the first node and the second node.

5. The circuit module of claim 4, wherein the buffer further includes a first inverter coupled between the input terminal and the output terminal of the buffer.

6. The circuit module of claim 1, further comprising: One or more first circuit blocks are coupled to the first connection; wherein, When one of the one or more first circuit blocks needs to transmit data, the first connection is driven according to the data after the first switch is turned on, and the driving of the first connection is stopped before the first switch is switched off.

7. The circuit module as described in claim 6, wherein, Each of these first circuit blocks is a storage repository.

8. The circuit module of claim 6, further comprising: A latch is coupled to the first node; when one of the one or more first circuit blocks stops driving the first connection, the latch maintains the voltage of the first node so that the voltage of the first node does not fluctuate.

9. The circuit module as described in claim 8, wherein, The latch includes: A third inverter, comprising a third inverter input and a third inverter output, respectively coupled to the first node and an internal node; and A fourth inverter includes a fourth inverter input and a fourth inverter output, which are respectively coupled to the internal node and the first node.

10. The circuit module as claimed in claim 1, wherein, During a certain period of time, both the first switch and the second switch are closed.

11. The circuit module of claim 1, further comprising: One or more second circuit blocks are coupled to the second connection; in, When one of the one or more second circuit blocks needs to transmit data, the second connection is driven according to the data after the second switch is turned on, and the driving of the second connection is stopped before the second switch is switched off.

12. The circuit module as claimed in claim 11, wherein, Each of these second circuit blocks is a repository.

13. The circuit module of claim 1, further comprising: A first driver includes a first driver input and a first driver output, respectively coupled to the second node and the first connection; the first driver is capable of enabling and disabling the first connection according to the voltage of the second node; wherein: When the second switch is turned on, the first switch is turned off; as well as The first driver is enabled when the first switch is closed.

14. The circuit module as claimed in claim 13, wherein, When the first switch is turned on, the first driver is disabled.

15. The circuit module of claim 13, wherein the first driver further comprises: A first transistor includes a first controlled terminal and a first channel terminal; A second transistor includes a second controlled terminal and two second channel terminals, wherein the two second channel terminals are respectively coupled to the first channel terminal and the first driver output terminal; An eighth transistor, comprising an eighth controlled terminal and an eighth channel terminal; and A seventh transistor includes a seventh controlled terminal and two seventh channel terminals, wherein the two seventh channel terminals are respectively coupled to the eighth channel terminal and the first driver output terminal; wherein: One of the first controlled terminal and the second controlled terminal is coupled to the first driver input terminal, and the other of the first controlled terminal and the second controlled terminal is coupled to a first inverting selection signal; One of the seventh controlled terminal and the eighth controlled terminal is coupled to the first driver input terminal, and the other of the seventh controlled terminal and the eighth controlled terminal is coupled to a first selection signal; and The first selection signal and the first inverted selection signal are inverses of each other.

16. The circuit module of claim 15, wherein the first switch comprises: A fifth transistor includes a fifth controlled terminal and two fifth channel terminals, which are respectively coupled to the first selection signal, the first node and the first connection.

17. The circuit module of claim 15, wherein the first switch comprises: an eleventh transistor, including an eleventh controlled terminal and two eleventh channel terminals, respectively coupled to the first inverting selection signal, the first node and the first connection.

18. The circuit module of claim 1, wherein the second driver further comprises: A third transistor, comprising a third controlled terminal and a third channel terminal; A fourth transistor includes a fourth controlled terminal and two fourth channel terminals, wherein the two fourth channel terminals are respectively coupled to the third channel terminal and the output terminal of the second driver; A tenth transistor, comprising a tenth controlled terminal and a tenth channel terminal; and A ninth transistor includes a ninth controlled terminal and two ninth channel terminals, wherein the two ninth channel terminals are respectively coupled to the tenth channel terminal and the output terminal of the second driver; wherein: One of the third controlled terminal and the fourth controlled terminal is coupled to the second driver input terminal, and the other of the third controlled terminal and the fourth controlled terminal is coupled to a second inverting selection signal; One of the ninth controlled terminal and the tenth controlled terminal is coupled to the second driver input terminal, and the other of the ninth controlled terminal and the tenth controlled terminal is coupled to a second selection signal; and The second selection signal and the second inverted selection signal are inverses of each other.

19. The circuit module of claim 18, wherein the second switch comprises: A sixth transistor includes a sixth controlled terminal and two sixth channel terminals, which are respectively coupled to the second selection signal, the first node and the second connection.

20. The circuit module of claim 18, wherein the second switch comprises: A twelfth transistor includes a twelfth controlled terminal and two twelfth channel terminals, respectively coupled to the second inverting selection signal, the first node and the second connection.

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