Latch and driving method, page buffer, memory device and memory system

Abstract

The present disclosure provides a latch and a driving method, a page buffer, a memory device, and a memory system. The latch includes: a data latch unit, a data input unit, a current control unit, and a sensing transistor; wherein the data latch unit includes: a first inverter and a second inverter connected in reverse; the connection points of the two inverters are a first node and a second node respectively; the data input unit includes: a first transistor and a second transistor whose control terminals are connected to a first input terminal and a second input terminal respectively; the current control unit includes: a third transistor and a fourth transistor whose control terminals are connected to the first input terminal and the second input terminal respectively, the second terminal of the third transistor is connected to the first inverter; the second terminal of the fourth transistor is connected to the second inverter; the control terminal of the sensing transistor is connected to the sensing node, and the first terminal of the sensing transistor is connected to the second terminal of the first transistor and the second terminal of the second transistor.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a latch and a driving method, a page buffer, a memory device, and a memory system. Background Art

[0002] Recently, three-dimensional non-volatile memory devices (e.g., vertical NAND memory devices) have been developed to increase the integration density and storage capacity of non-volatile memory devices. The non-volatile memory device includes a memory cell array and peripheral circuits, wherein the peripheral circuits include a page buffer connected to the memory cell array via bit lines. The page buffer can store (e.g., temporarily store) data to be programmed into a selected memory page of the memory cell array or read data from a selected memory page of the memory cell array. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a latch and a driving method, a page buffer, a memory device, and a memory system to solve at least one technical problem in the prior art.

[0004] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a latch, comprising: a data latch unit, a data input unit, a current control unit, and a sensing transistor; wherein,

[0006] The data latch unit includes: a first inverter and a second inverter; an output terminal of the first inverter is connected to an input terminal of the second inverter and is connected to a first node; an input terminal of the first inverter is connected to an output terminal of the second inverter and is connected to a second node;

[0007] The data input unit includes: a first transistor and a second transistor, wherein the control terminal of the first transistor is connected to the first input terminal, and the first terminal of the first transistor is connected to the first node; the control terminal of the second transistor is connected to the second input terminal, and the first terminal of the second transistor is connected to the second node;

[0008] The current control unit includes: a third transistor and a fourth transistor, wherein the control terminal of the third transistor is connected to the first input terminal, and the second terminal of the third transistor is connected to the first inverter; the control terminal of the fourth transistor is connected to the second input terminal; the second terminal of the fourth transistor is connected to the second inverter; and the first terminal of the third transistor and the first terminal of the fourth transistor are connected to a power supply voltage;

[0009] The control terminal of the sensing transistor is connected to the sensing node, the first terminal of the sensing transistor is connected to the second terminal of the first transistor and the second terminal of the second transistor, and the second terminal of the sensing transistor is grounded.

[0010] In some embodiments, the first inverter includes a first P-type transistor and a first N-type transistor; the second inverter includes a second P-type transistor and a second N-type transistor; wherein,

[0011] The control terminal of the first P-type transistor is connected to the second node, the first terminal of the first P-type transistor is connected to the second terminal of the third transistor, and the second terminal of the first P-type transistor is connected to the first node;

[0012] The control terminal of the first N-type transistor is connected to the second node, the first terminal of the first N-type transistor is connected to the first node, and the second terminal of the first N-type transistor is grounded;

[0013] a control terminal of the second P-type transistor connected to the first node, a first terminal of the second P-type transistor connected to the second terminal of the fourth transistor, and a second terminal of the second P-type transistor connected to the second node;

[0014] A control terminal of the second N-type transistor is connected to the first node, a first terminal of the second N-type transistor is connected to the second node, and a second terminal of the second N-type transistor is connected to a ground voltage.

[0015] In some embodiments, the first transistor, the second transistor, and the sensing transistor are N-type transistors;

[0016] The third transistor and the fourth transistor are P-type transistors.

[0017] In some embodiments, the current control unit further includes: a fifth transistor and a sixth transistor; wherein,

[0018] The control terminal of the fifth transistor is connected to the third input terminal, the first terminal of the fifth transistor is connected to the first inverter, and the second terminal of the fifth transistor is grounded;

[0019] The control terminal of the sixth transistor is connected to the fourth input terminal, the first terminal of the sixth transistor is connected to the second inverter, and the second terminal of the sixth transistor is grounded;

[0020] Among them, the first input end is used to input a first signal, the second input end is used to input a second signal, the third input end is used to input a third signal that is an inverted signal of the second signal; and the fourth input end is used to input a fourth signal that is an inverted signal of the first signal.

[0021] In some embodiments, the first inverter includes a first P-type transistor and a first N-type transistor; the second inverter includes a second P-type transistor and a second N-type transistor; wherein,

[0022] The control terminal of the first P-type transistor is connected to the second node, the first terminal of the first P-type transistor is connected to the second terminal of the third transistor, and the second terminal of the first P-type transistor is connected to the first node;

[0023] The control terminal of the first N-type transistor is connected to the second node, the first terminal of the first N-type transistor is connected to the first node, and the second terminal of the first N-type transistor is connected to the first terminal of the fifth transistor;

[0024] a control terminal of the second P-type transistor connected to the first node, a first terminal of the second P-type transistor connected to the second terminal of the fourth transistor, and a second terminal of the second P-type transistor connected to the second node;

[0025] A control terminal of the second N-type transistor is connected to the first node, a first terminal of the second N-type transistor is connected to the second node, and a second terminal of the second N-type transistor is connected to the first terminal of the sixth transistor.

[0026] In some embodiments, the fifth transistor and the sixth transistor are N-type transistors.

[0027] In some embodiments, the current control unit further includes: a seventh transistor; wherein,

[0028] The control terminal of the seventh transistor is connected to the fifth input terminal, the first terminal of the seventh transistor is connected to the data latch unit, and the second terminal of the seventh transistor is grounded;

[0029] Among them, the first input end is used to input the first signal, the second input end is used to input the second signal, and the fifth input end is used to input the fifth signal. The fifth signal is a signal obtained by performing a logical AND operation on the inverted signal of the first signal and the inverted signal of the second signal.

[0030] In some embodiments, the first inverter includes a first P-type transistor and a first N-type transistor; the second inverter includes a second P-type transistor and a second N-type transistor; wherein,

[0031] The control terminal of the first P-type transistor is connected to the second node, the first terminal of the first P-type transistor is connected to the second terminal of the third transistor, and the second terminal of the first P-type transistor is connected to the first node;

[0032] The control terminal of the first N-type transistor is connected to the second node, the first terminal of the first N-type transistor is connected to the first node, and the second terminal of the first N-type transistor is connected to the first terminal of the seventh transistor;

[0033] a control terminal of the second P-type transistor connected to the first node, a first terminal of the second P-type transistor connected to the second terminal of the fourth transistor, and a second terminal of the second P-type transistor connected to the second node;

[0034] A control terminal of the second N-type transistor is connected to the first node, a first terminal of the second N-type transistor is connected to the second node, and a second terminal of the second N-type transistor is connected to the first terminal of the seventh transistor.

[0035] In some embodiments, the seventh transistor is an N-type transistor.

[0036] In a second aspect, an embodiment of the present disclosure provides a latch driving method, which is applied to the latch described in the above technical solution; the driving method includes:

[0037] If the voltage of the sensing node is less than the flip voltage, when the sensing transistor is turned on, the power supply voltage VDD is input to the first input terminal, and the ground voltage VSS is input to the second input terminal, then the voltage of the first node decreases from VDD to VDD / 2, and the voltage of the second node increases from VSS to VDD / 2;

[0038] If the voltage of the sensing node is greater than or equal to the flip voltage, when the sensing transistor is turned on, VDD is input to the first input terminal and VSS is input to the second input terminal, then the voltage of the first node flips from VDD to VSS, and the voltage of the second node flips from VSS to VDD.

[0039] In a third aspect, an embodiment of the present disclosure provides a page buffer, comprising: at least one latch as described in the above technical solution; wherein the latch is used to store bit programming verification information or bit line forcing information.

[0040] In a fourth aspect, an embodiment of the present disclosure provides a memory device, comprising: a memory cell array and a peripheral circuit; wherein:

[0041] The memory cell array has a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings;

[0042] The peripheral circuit is connected to the memory cell array through the bit line and is used to operate the memory cell array; wherein a plurality of page buffers as described in the above technical solution are arranged in the peripheral circuit, and the page buffers are connected to the memory cell string through the bit line.

[0043] In a fifth aspect, an embodiment of the present disclosure provides a memory system, comprising: a memory device and a controller as described in the above technical solution; wherein the controller is connected to the memory device and is used to control the memory device.

[0044] In a sixth aspect, an embodiment of the present disclosure provides an electronic device, which includes the memory system described in the above technical solution.

[0045] Embodiments of the present disclosure provide a latch and a driving method, a page buffer, a memory device, and a memory system. The latch includes: a data latch unit, a data input unit, a current control unit and a sensing transistor; wherein the data latch unit includes: a first inverter and a second inverter; the output end of the first inverter is connected to the input end of the second inverter and is connected to a first node; the input end of the first inverter is connected to the output end of the second inverter and is connected to a second node; the data input unit includes: a first transistor and a second transistor, the control terminal of the first transistor is connected to the first input end, and the first terminal of the first transistor is connected to the first node; the control terminal and the second input end of the second transistor are connected, and the first terminal of the second transistor is connected to the second node; the current control unit includes: a third transistor and a fourth transistor, the control terminal of the third transistor is connected to the first input end, and the second terminal of the third transistor is connected to the first inverter; the control terminal and the second input end of the fourth transistor are connected; the second terminal of the fourth transistor is connected to the second inverter; the first terminal of the third transistor and the first terminal of the fourth transistor are connected to the power supply voltage; the control terminal of the sensing transistor is connected to the sensing node, the first terminal of the sensing transistor is connected to the second terminal of the first transistor and the second terminal of the second transistor, and the second terminal of the sensing transistor is grounded. In the embodiment of the present disclosure, by setting the control terminals of the third transistor in the current control unit and the first transistor in the data input unit to be connected to the first input terminal, and the control terminals of the fourth transistor in the current control unit and the second transistor in the data input unit to be connected to the second input terminal, not only can the DC current passing through the data latch unit be effectively reduced, but also the transient current passing through the data latch unit can be reduced during the flipping operation of the latch, thereby improving power supply efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1A Schematics of latches provided for some examples;

[0047] Figure 1B The operating signal waveforms of the latch are provided for some examples;

[0048] Figure 2A Schematic diagram 1 of a latch provided in an embodiment of the present disclosure;

[0049] Figure 2B FIG1 is a working signal waveform diagram of a latch provided in an embodiment of the present disclosure;

[0050] Figure 2C Schematic diagram 2 of a latch provided in an embodiment of the present disclosure;

[0051] Figure 2D FIG2 is a second waveform diagram of operating signals of a latch provided in an embodiment of the present disclosure;

[0052] Figure 2E Schematic diagram of a latch provided in an embodiment of the present disclosure Figure 3 ;

[0053] Figure 2F The working signal waveform of the latch provided by the embodiment of the present disclosure Figure 3 ;

[0054] Figure 3 A schematic diagram of a page buffer provided in an embodiment of the present disclosure;

[0055] Figure 4 A schematic diagram of a memory device provided in an embodiment of the present disclosure;

[0056] Figure 5 A schematic diagram of a memory device having a memory cell array provided in an embodiment of the present disclosure;

[0057] Figure 6 A schematic diagram of a memory device with a peripheral circuit provided in an embodiment of the present disclosure;

[0058] Figure 7 A schematic diagram of a memory system provided in an embodiment of the present disclosure;

[0059] Figure 8 A schematic diagram of a system having a memory device according to an embodiment of the present disclosure;

[0060] Figure 9A A schematic diagram of a memory card having a memory device is provided for one example of the present disclosure;

[0061] Figure 9B A schematic diagram of a solid-state drive having a memory device is provided for one example of the present disclosure. DETAILED DESCRIPTION

[0062] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0063] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0064] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0065] refer to Figure 1A , Figure 1A Schematic diagram of a latch is provided for some examples. Figure 1A As shown, the latch includes: a data latch unit 110, a data input unit 120 and a sensing transistor 130; wherein the data latch unit 110 includes: a first inverter 111 and a second inverter 112; the output end of the first inverter 111 is connected to the input end of the second inverter 112, and is connected to a first node 113; the input end of the first inverter 111 is connected to the output end of the second inverter 112, and is connected to a second node 114.

[0066] Here, the first inverter 111 includes a first P-type transistor P1 and a first N-type transistor N1, wherein the first P-type transistor P1 includes a control terminal connected to the second node 114, a first terminal connected to a power supply voltage (e.g., VDD), and a second terminal connected to the first node 113. The first N-type transistor N1 includes a control terminal connected to the second node 114, a first terminal connected to the first node 113, and a second terminal connected to a ground voltage (e.g., VSS).

[0067] Here, the second inverter 112 includes a second P-type transistor P2 and a second N-type transistor N2, wherein the second P-type transistor P2 includes: a control terminal connected to the first node 113; a first terminal connected to a power supply voltage (e.g., VDD); and a second terminal connected to the second node 114. The second N-type transistor N2 includes: a control terminal connected to the first node 113; a first terminal connected to the second node 114; and a second terminal connected to a ground voltage (e.g., VSS).

[0068] It should be noted that, for a P-type transistor, the first terminal is the source (S), the second terminal is the drain (D), and the control terminal is the gate (G); for an N-type transistor, the first terminal is the drain (D), the second terminal is the source (S), and the control terminal is the gate (G).

[0069] like Figure 1A As shown, the data input unit 120 of the latch includes: a first transistor 121 and a second transistor 122. The control terminal of the first transistor 121 is connected to the first input terminal, and the first terminal of the first transistor 121 is connected to the first node 113. The control terminal of the second transistor 122 is connected to the second input terminal, and the first terminal of the second transistor 122 is connected to the second node 114. The control terminal of the latch's sensing transistor 130 is connected to the sensing node SO, the first terminal of the sensing transistor 130 is connected to the second terminal of the first transistor 121 and the second terminal of the second transistor 122, and the second terminal of the sensing transistor 130 is grounded.

[0070] Here, the first transistor, the second transistor and the sensing transistor may all be N-type transistors (eg, NMOS transistors).

[0071] Here, the first transistor is configured to respond to a Set signal received at a first input terminal, and the second transistor is configured to respond to an Rst signal received at a second input terminal.

[0072] refer to Figure 1B , Figure 1B The working signal waveforms of the latch are provided for some examples. Figure 1B As shown, the control terminal of the sensing transistor is connected to the sensing node SO, charging the sensing node SO. The sensing transistor can be turned on by the voltage level of the sensing node SO. At time t1, the Set signal is at a high level (e.g., VDD). In response to the Set signal, the first transistor NM1 is turned on, and the voltage at the first node a is at a high level VDD. At this time, the second N-type transistor N2 is turned on. The Rst signal is at a low level (e.g., VSS). In response to the Rst signal, the second transistor NM2 is not turned on, and the voltage at the second node b is at a low level VSS. At this time, the first P-type transistor P1 is turned on. After the first transistor NM1 is turned on, the voltage at the first node a gradually decreases, and the second P-type transistor P2 is turned on. The voltage at the second node b gradually increases, and the first N-type transistor N1 is turned on. At time t2, the voltage at the first node a decreases from VDD to VDD / 2, and the voltage at the second node b increases from VSS to VDD / 2.

[0073] Here, after both inverters of the data latch unit are turned on, the first P-type transistor P1 and the first N-type transistor N1 of the first inverter, and the second P-type transistor P2 and the second N-type transistor N2 of the second inverter are all in an open state, and the DC current (DC current) passing through the data latch unit is large, resulting in poor power efficiency (power efficiency).

[0074] As previously described, the first terminals of the first P-type transistor P1 and the second P-type transistor P2 are both connected to the power supply voltage VDD. However, due to line loss, the actual voltages at the first terminals of the first P-type transistor P1 and the second P-type transistor P2 are slightly lower than the power supply voltage VDD. Similarly, the second terminals of the first N-type transistor N1 and the second N-type transistor N2 are both connected to the ground voltage VSS. The actual voltages at the second terminals of the first N-type transistor N1 and the second N-type transistor N2 are slightly higher than the ground voltage VSS. As the DC current through the data latch unit increases, the corresponding line loss also increases. As a result, the actual voltages at the first terminals of the first P-type transistor P1 and the second P-type transistor P2 decrease (VDD drop), while the actual voltages at the second terminals of the first N-type transistor N1 and the second N-type transistor N2 increase (VSS bunce). This can lead to high Fail Bit Count (FBC) statistics in asynchronous multi-plane independent (AMPI) read and cache operations.

[0075] Here, as the voltage at the sensing node SO gradually increases to a value greater than the turn-on voltage of the sensing transistor, the sensing transistor can be turned on. Furthermore, when the voltage at the sensing node SO rises to a value greater than or equal to the flip voltage Vtrip, the voltage at the first node a rapidly flips from a high level VDD to a low level VSS, while the voltage at the second node b flips from a low level VSS to a high level VDD. During the flip operation, there is a brief period during which both the first and second inverters are turned on simultaneously. During this period, the transient currents I1 and I2 flowing through the first and second inverters are very large, resulting in significant losses.

[0076] It should be noted that the flip voltage Vtrip is defined as the minimum sensing node voltage that can flip the data latch unit after applying a high level pulse to the first input terminal or the second input terminal. In a specific embodiment, Vtrip can be VDD / 2.

[0077] In view of this, embodiments of the present disclosure provide a latch and a driving method, a page buffer, a memory device, and a memory system.

[0078] refer to Figure 2A , Figure 2A Schematic diagram 1 of a latch provided in an embodiment of the present disclosure. Figure 2A As shown, the latch provided by the embodiment of the present disclosure includes: a data latch unit 210, a data input unit 220, a current control unit 240 and a sensing transistor 230; wherein the data latch unit 210 includes: a first inverter 211 and a second inverter 212; the output terminal of the first inverter 211 is connected to the input terminal of the second inverter 212 and is connected to a first node 213; the input terminal of the first inverter 211 is connected to the output terminal of the second inverter 212 and is connected to a second node 214. Here, the data input unit 220 of the latch includes: a first transistor 221 and a second transistor 222, wherein the control terminal of the first transistor 221 is connected to the first input terminal, and the first terminal of the first transistor 221 is connected to the first node 213; the control terminal of the second transistor 222 is connected to the second input terminal, and the first terminal of the second transistor 222 is connected to the second node 214. Here, the control terminal of the latch sensing transistor 230 is connected to the sensing node SO, the first terminal of the sensing transistor 230 is connected to the second terminal of the first transistor 221 and the second terminal of the second transistor 222, and the second terminal of the sensing transistor 230 is grounded.

[0079] In the embodiment of the present disclosure, the first transistor, the second transistor and the sensing transistor may all be N-type transistors (eg, NMOS transistors).

[0080] like Figure 2A As shown, the current control unit 240 of the latch provided by the embodiment of the present disclosure includes: a third transistor 243 and a fourth transistor 244, the control terminal of the third transistor 243 is connected to the first input terminal, and the second terminal of the third transistor 243 is connected to the first inverter 211; the control terminal of the fourth transistor 244 is connected to the second input terminal; the second terminal of the fourth transistor 244 is connected to the second inverter 212; the first terminal of the third transistor 243, the first terminal of the fourth transistor 244 and the power supply voltage (for example, VDD) are connected.

[0081] In the embodiment of the present disclosure, the third transistor and the fourth transistor may both be P-type transistors (eg, PMOS transistors).

[0082] In the embodiment of the present disclosure, the first inverter 211 includes a first P-type transistor P1 and a first N-type transistor N1. The first P-type transistor P1 includes: a control terminal connected to the second node 214; a first terminal connected to the second terminal of the third transistor 243; and a second terminal connected to the first node 213. The first N-type transistor N1 includes: a control terminal connected to the second node 214; a first terminal connected to the first node 213; and a second terminal connected to a ground voltage (e.g., VSS).

[0083] In the embodiment of the present disclosure, the second inverter 212 includes a second P-type transistor P2 and a second N-type transistor N2. The second P-type transistor P2 includes: a control terminal connected to the first node 213; a first terminal connected to the second terminal of the fourth transistor 244; and a second terminal connected to the second node 214. The second N-type transistor N2 includes: a control terminal connected to the first node 213; a first terminal connected to the second node 214; and a second terminal connected to a ground voltage (e.g., VSS).

[0084] In the embodiment of the present disclosure, the first transistor NM1 and the third transistor PM3 are configured to respond to the Set signal received at the first input terminal, and the second transistor NM2 and the fourth transistor PM4 are configured to respond to the Rst signal received at the second input terminal.

[0085] refer to Figure 2B , Figure 2B FIG1 is a working signal waveform diagram of the latch provided in the embodiment of the present disclosure. Figure 2B As shown, the control terminal of the sensing transistor is connected to the sensing node SO, charging the sensing node SO. The sensing transistor can be turned on by the voltage level of the sensing node SO. At time t1, the Set signal is at a high level (e.g., VDD). In response to the Set signal, the first transistor NM1 is turned on, and the voltage at the first node a is at a high level VDD. At this time, the second N-type transistor N2 is turned on. The Rst signal is at a low level (e.g., VSS). In response to the Rst signal, the second transistor NM2 is not turned on, and the voltage at the second node b is at a low level VSS. At this time, the first P-type transistor P1 is turned on. After the first transistor NM1 is turned on, the voltage at the first node a gradually decreases, and the second P-type transistor P2 is turned on. The voltage at the second node b gradually increases, and the first N-type transistor N1 is turned on. At time t2, the voltage at the first node a decreases from VDD to VDD / 2, and the voltage at the second node b increases from VSS to VDD / 2.

[0086] In the embodiment of the present disclosure, when the Set signal is at a high level (e.g., VDD), the third transistor PM3 responding to the Set signal is in the off state; when the Rst signal is at a low level (e.g., VSS), the fourth transistor PM4 responding to the Rst signal is in the open state. Only the second inverter of the data latch unit is turned on, and the fourth transistor PM4, the second P-type transistor P2, and the second N-type transistor N2 are all in the open state, and the DC current passing through the data latch unit is reduced by half. Figure 1A Compared with the latch shown, the DC current passing through the data latch unit is reduced, and the line loss is also reduced, thereby improving power efficiency.

[0087] In the embodiment of the present disclosure, when the voltage of the sensing node SO gradually increases to a value greater than the turn-on voltage of the sensing transistor, the sensing transistor can be turned on. Further, when the voltage of the sensing node SO increases to a value greater than or equal to the flip voltage Vtrip, the voltage of the first node a quickly flips from the high level VDD to the low level VSS, and the voltage of the second node b flips from the low level VSS to the high level VDD. During the flip operation, the third transistor PM3 is in the off state, and the third transistor PM3 is in the off state. Figure 1A In comparison, the latch shown in FIG. 1 has a transient current I0 flowing through the first inverter or the second inverter for at least a short period of time, causing the voltages of the first node a and the second node b to flip. At this time, the transient current flowing through the data latch unit is reduced by half, thereby improving power efficiency.

[0088] refer to Figure 2C , Figure 2C Schematic diagram 2 of the latch provided in the embodiment of the present disclosure. Figure 2C As shown, the latch provided by the embodiment of the present disclosure includes: a data latch unit 210, a data input unit 220, a current control unit and a sensing transistor 230; wherein the settings of the data latch unit 210, the data input unit 220 and the sensing transistor 230 can refer to Figure 2A The relevant description will not be repeated here.

[0089] like Figure 2C As shown, the current control unit of the latch provided by the embodiment of the present disclosure includes: a third transistor 243, a fourth transistor 244, a fifth transistor 245 and a sixth transistor 246. The connection relationship between the third transistor 243 and the fourth transistor 244 can be referred to Figure 2AThe relevant description is not repeated here. Here, the control terminal of the fifth transistor 245 is connected to the third input terminal; the first terminal of the fifth transistor 245 is connected to the first inverter 211, more specifically, the first terminal of the fifth transistor 245 is connected to the second terminal of the first N-type transistor N1; the second terminal of the fifth transistor 245 is grounded (e.g., VSS). Here, the control terminal of the sixth transistor 246 is connected to the fourth input terminal; the first terminal of the sixth transistor 246 is connected to the second inverter 212, more specifically, the first terminal of the sixth transistor 246 is connected to the second terminal of the second N-type transistor N2; the second terminal of the sixth transistor 246 is grounded (e.g., VSS).

[0090] In the embodiment of the present disclosure, the first input terminal is used to input a first signal (e.g., a Set signal), the second input terminal is used to input a second signal (e.g., a Rst signal), the third input terminal is used to input a third signal that is an inverted signal to the second signal (e.g., a Rst_n signal); the fourth input terminal is used to input a fourth signal that is an inverted signal to the first signal (e.g., a Set_n signal).

[0091] In the embodiment of the present disclosure, the fifth transistor and the sixth transistor may both be N-type transistors (eg, NMOS transistors).

[0092] In the embodiment of the present disclosure, the first transistor NM1 and the third transistor PM3 are configured to respond to the Set signal received at the first input terminal, the second transistor NM2 and the fourth transistor PM4 are configured to respond to the Rst signal received at the second input terminal, the fifth transistor NM5 is configured to respond to the Rst_n signal received at the third input terminal, and the sixth transistor NM6 is configured to respond to the Set_n signal received at the fourth input terminal.

[0093] refer to Figure 2D , Figure 2D FIG2 is a working signal waveform diagram of the latch provided in the embodiment of the present disclosure. Figure 2DAs shown, the control terminal of the sensing transistor is connected to the sensing node SO, charging the sensing node SO. The sensing transistor can be turned on by the voltage level of the sensing node SO. At time t1, the Set signal is at a high level (e.g., VDD). In response to the Set signal, the first transistor NM1 is turned on, and the voltage at the first node a is at a high level VDD. At this time, the second N-type transistor N2 is turned on. The Rst signal is at a low level (e.g., VSS). In response to the Rst signal, the second transistor NM2 is not turned on, and the voltage at the second node b is at a low level VSS. At this time, the first P-type transistor P1 is turned on. After the first transistor NM1 is turned on, the voltage at the first node a gradually decreases, and the second P-type transistor P2 is turned on. The voltage at the second node b gradually increases, and the first N-type transistor N1 is turned on. At time t2, the voltage at the first node a decreases from VDD to VDD / 2, and the voltage at the second node b increases from VSS to VDD / 2.

[0094] In the embodiment of the present disclosure, when the Set signal is at a high level (e.g., VDD), the third transistor PM3 responding to the Set signal is in an off state; when the Rst signal is at a low level (e.g., VSS), the fourth transistor PM4 responding to the Rst signal is in an open state; when the Rst_n signal is at a high level (e.g., VDD), the fifth transistor NM5 responding to the Rst_n signal is in an open state; when the Set_n signal is at a low level (e.g., VSS), the sixth transistor NM6 responding to the Set_n signal is in an off state. Since the third transistor PM3 and the sixth transistor NM6 are in an off state, no DC current passes through the data latch unit. Figure 1A In comparison with the latch shown, no DC current flows through the data latch unit, thereby improving power efficiency.

[0095] In the embodiment of the present disclosure, when the voltage of the sensing node SO gradually increases to a value greater than the turn-on voltage of the sensing transistor, the sensing transistor can be turned on. Further, when the voltage of the sensing node SO increases to a value greater than or equal to the flip voltage Vtrip, the voltage of the first node a quickly flips from the high level VDD to the low level VSS, and the voltage of the second node b flips from the low level VSS to the high level VDD. During the flip operation, the third transistor PM3 and the sixth transistor NM6 are both in the off state, and the third transistor PM3 and the sixth transistor NM6 are in the off state. Figure 1A In comparison, the latch shown in FIG. 1 has a transient current I0 flowing through the first inverter or the second inverter for at least a short period of time, causing the voltages of the first node a and the second node b to flip. At this time, the transient current flowing through the data latch unit is reduced by half, thereby improving power efficiency.

[0096] refer to Figure 2E , Figure 2E Schematic diagram of a latch provided in an embodiment of the present disclosure Figure 3 .like Figure 2E As shown, the latch provided by the embodiment of the present disclosure includes: a data latch unit 210, a data input unit 220, a current control unit and a sensing transistor 230; wherein the settings of the data latch unit 210, the data input unit 220 and the sensing transistor 230 can refer to Figure 2A The relevant description will not be repeated here.

[0097] like Figure 2E As shown, the current control unit of the latch provided by the embodiment of the present disclosure includes: a third transistor 243, a fourth transistor 244 and a seventh transistor 247. The connection relationship between the third transistor 243 and the fourth transistor 244 can be referred to Figure 2A The relevant description is omitted here. Here, the control terminal of the seventh transistor 247 is connected to the fifth input terminal; the first terminal of the seventh transistor 247 is connected to the data latch unit, more specifically, the first terminal of the seventh transistor 247 is connected to the second terminals of the first N-type transistor N1 and the second N-type transistor N2; and the second terminal of the seventh transistor 247 is connected to the ground voltage (e.g., VSS).

[0098] In an embodiment of the present disclosure, the first input terminal is used to input a first signal (for example, a Set signal), the second input terminal is used to input a second signal (for example, a Rst signal), and the fifth input terminal is used to input a fifth signal (for example, Rst_n&Set_n), where the fifth signal is a signal obtained by performing a logical AND operation on the inverted signal of the first signal and the inverted signal of the second signal.

[0099] In the embodiment of the present disclosure, the seventh transistor may be an N-type transistor (eg, an NMOS transistor).

[0100] In the embodiment of the present disclosure, the first transistor NM1 and the third transistor PM3 are configured to respond to the Set signal received at the first input terminal, the second transistor NM2 and the fourth transistor PM4 are configured to respond to the Rst signal received at the second input terminal, and the seventh transistor NM7 is configured to respond to the Rst_n&Set_n signal received at the fifth input terminal.

[0101] refer to Figure 2F , Figure 2F The working signal waveform of the latch provided by the embodiment of the present disclosure Figure 3 .like Figure 2FAs shown, the control terminal of the sensing transistor is connected to the sensing node SO, charging the sensing node SO. The sensing transistor can be turned on by the voltage level of the sensing node SO. At time t1, the Set signal is at a high level (e.g., VDD). In response to the Set signal, the first transistor NM1 is turned on, and the voltage at the first node a is at a high level VDD. At this time, the second N-type transistor N2 is turned on. The Rst signal is at a low level (e.g., VSS). In response to the Rst signal, the second transistor NM2 is not turned on, and the voltage at the second node b is at a low level VSS. At this time, the first P-type transistor P1 is turned on. After the first transistor NM1 is turned on, the voltage at the first node a gradually decreases, and the second P-type transistor P2 is turned on. The voltage at the second node b gradually increases, and the first N-type transistor N1 is turned on. At time t2, the voltage at the first node a decreases from VDD to VDD / 2, and the voltage at the second node b increases from VSS to VDD / 2.

[0102] In the embodiment of the present disclosure, when the Set signal is at a high level (e.g., VDD), the third transistor PM3 responding to the Set signal is in an off state; when the Rst signal is at a low level (e.g., VSS), the fourth transistor PM4 responding to the Rst signal is in an open state; after a logic AND operation is performed on the inverted signal Set_n of the Set signal and the inverted signal Rst_n of the Rst signal, that is, the fifth signal is at a low level (e.g., VSS), the seventh transistor NM7 responding thereto is in an off state. Since both the third transistor PM3 and the seventh transistor NM7 are in an off state, no DC current passes through the data latch unit. Figure 1A In comparison with the latch shown, no DC current flows through the data latch unit, thereby improving power efficiency.

[0103] In the embodiment of the present disclosure, when the voltage of the sensing node SO gradually increases to a value greater than the turn-on voltage of the sensing transistor, the sensing transistor can be turned on. Further, when the voltage of the sensing node SO increases to a value greater than or equal to the flip voltage Vtrip, the voltage of the first node a quickly flips from the high level VDD to the low level VSS, and the voltage of the second node b flips from the low level VSS to the high level VDD. During the flip operation, the third transistor PM3 and the seventh transistor NM7 are both in the off state, and the third transistor PM3 and the seventh transistor NM7 are in the off state. Figure 1A In comparison, the latch shown in FIG. 1 has a transient current I0 flowing through the first inverter or the second inverter for at least a short period of time, causing the voltages of the first node a and the second node b to flip. At this time, the transient current flowing through the data latch unit is reduced by half, thereby improving power efficiency.

[0104] and Figure 1ACompared with the latch shown in FIG, in the embodiment of the present disclosure, by setting a current control unit, Figure 2A The DC current through the data latch unit in the latch shown is reduced by half, Figure 2C and Figure 2E In the latch shown, no DC current flows through the data latch unit, thereby improving power efficiency. Figure 1A Compared with the latch shown in FIG, in the embodiment of the present disclosure, by setting a current control unit, Figure 2A 、 Figure 2C and Figure 2E During the flip operation of the latch shown, the transient current through the data latch unit is reduced by half, thereby improving power efficiency.

[0105] An embodiment of the present disclosure provides a latch driving method, which is applied to the latch in the above technical solution. The driving method includes:

[0106] If the voltage of the sensing node SO is lower than the flip voltage Vstrip, when the sensing transistor is turned on, a Set signal (e.g., the power supply voltage VDD) is input to the first input terminal, and an Rst signal (e.g., the ground voltage VSS) is input to the second input terminal, then the voltage of the first node a decreases from VDD to VDD / 2, and the voltage of the second node b increases from VSS to VDD / 2.

[0107] If the voltage of the sensing node SO is greater than or equal to the flip voltage Vstrip, when the sensing transistor is turned on, the Set signal (for example, the power supply voltage VDD) is input to the first input terminal, and the Rst signal (for example, the ground voltage VSS) is input to the second input terminal, then the voltage of the first node a is flipped from VDD to VSS, and the voltage of the second node b is flipped from VSS to VDD.

[0108] The power supply voltage VDD may be, for example, a high level VDD, and the ground voltage VSS may be, for example, a low level VSS.

[0109] An embodiment of the present disclosure provides a page buffer, which includes: at least one latch according to the above technical solution; wherein the latch is used to store program verification information or bit line forcing information.

[0110] refer to Figure 3 , Figure 3 Schematic diagram of a page buffer provided by an embodiment of the present disclosure. Figure 3As shown, the page buffer includes: a charge and discharge unit 310, a latch 320 and a bit line voltage setting unit 330; wherein the charge and discharge unit 310 is connected to the power supply voltage and is connected to the bit line through the bit line voltage setting unit 330; wherein the charge and discharge unit 310 is used to provide the power supply voltage to the bit line voltage setting unit 330; the latch 320 connects the charge and discharge unit 310 and the bit line; wherein the latch 320 is used to store programming verification information or bit line forcing information; the bit line voltage setting unit 330 connects the charge and discharge unit 310 and the bit line; wherein the bit line voltage setting unit 330 is used to apply a bit line forcing voltage to the bit line based on the power supply voltage according to the bit line forcing information stored in the latch 320.

[0111] In the disclosed embodiment, latch 320 can be used to store program verification information or bit line force information. For example, the latch can be used to store data indicating the verification result after the program and verification operations. Here, the verification result can be binary data "0" or "1" to indicate whether the verification passed.

[0112] In a specific embodiment, the page buffer may include a first latch, a second latch, and a third latch. Based on a first verification voltage Vfc1, a second verification voltage Vfc2, and a third verification voltage Vvfy, the memory cells are divided into normal programming cells, first force cells, second force cells, and program-inhibited cells. The threshold voltage of the normal programming cells is lower than the first verification voltage Vfc1, the threshold voltage of the first force cells is between the first verification voltage Vfc1 and the second verification voltage Vfc2, the threshold voltage of the second force cells is between the second verification voltage Vfc2 and the third verification voltage Vvfy, and the threshold voltage of the program-inhibited cells is higher than the third verification voltage Vvfy.

[0113] Here, the first latch can store first verification information DL corresponding to the first verification voltage Vfc1 as first bitline forcing information. For example, when the threshold voltage of a memory cell is greater than the first verification voltage Vfc1, "1" can be stored as the first verification information DL, indicating that the memory cell on the corresponding bitline includes a first forcing unit, a second forcing unit, and a program-inhibited unit. When the threshold voltage of a memory cell is less than the first verification voltage Vfc1, "0" can be stored as the first verification information DL, indicating that the memory cell on the corresponding bitline is a normal programming unit, i.e., the memory cell on the corresponding bitline will not undergo the first line forcing operation.

[0114] Here, the second latch may store second verification information DM corresponding to the second verification voltage Vfc2 as second bit line forcing information. For example, when the threshold voltage of a memory cell is greater than the second verification voltage Vfc2, "1" may be stored as the second verification information DM, indicating that the memory cell on the corresponding bit line includes a second forcing unit and a program-inhibited unit. When the threshold voltage of a memory cell is less than the second verification voltage Vfc2, "0" may be stored as the second verification information DM, indicating that the memory cell on the corresponding bit line will not undergo the second bit line forcing operation.

[0115] Here, the third latch may store third verification information DS corresponding to the third verification voltage Vvfy. For example, when the threshold voltage of the memory cell is greater than the third verification voltage Vvfy, "1" may be stored as the third verification information DS, indicating that the memory cell on the corresponding bit line is a program-inhibited cell; when the threshold voltage of the memory cell is less than the third verification voltage Vvfy, "0" may be stored as the third verification information DS.

[0116] In the disclosed embodiment, the bit line voltage setting unit 330 may be an NMOS transistor, a PMOS transistor, or a combination of multiple NMOS transistors and / or multiple PMOS transistors. The bit line voltage setting unit may also be other components that can be used to adjust voltage, such as a Zener diode, a transient voltage suppressor, and a varistor.

[0117] In the disclosed embodiment, the bitline voltage setting unit 330 can adjust the power supply voltage to an appropriate voltage value, such as a first bitline forced voltage (ground voltage < first bitline forced voltage < power supply voltage), based on the verification result stored in the latch 320, and then apply the voltage to the bitline. The bitline voltage setting unit 330 applies the bitline forced voltage to the bitline based on the power supply voltage according to the verification result stored in the latch 320, thereby narrowing the threshold voltage distribution of the memory cells.

[0118] refer to Figure 4 , Figure 4 Schematic diagram of a memory device provided by an embodiment of the present disclosure. Figure 4 As shown, an embodiment of the present disclosure provides a memory device, the memory device 400 includes: a memory cell array 410 and a peripheral circuit 420; wherein the memory cell array 410 has a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; the peripheral circuit 420 is connected to the memory cell array through the bit lines, and is used to operate the memory cell array; wherein a plurality of page buffers 421 are arranged in the peripheral circuit 420, and the page buffers 421 are connected to the memory cell strings through the bit lines.

[0119] In the embodiment of the present disclosure, the memory device 400 may be a non-volatile storage device such as a NAND chip.

[0120] In the embodiment of the present disclosure, the memory cell array can be any suitable memory cell array. Figure 5 , describing in detail the memory cell array of the memory device provided by the embodiment of the present disclosure.

[0121] like Figure 5 As shown, the memory device 500 includes a memory cell array 510 and a peripheral circuit 520 coupled to the memory cell array 510. Here, the memory cell array can be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory cell strings 511, and each NAND memory cell string 511 extends vertically above the substrate. In some examples, each NAND memory cell string 511 may include a plurality of memory cells coupled in series and stacked vertically. Each memory cell holds a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the memory cell area. In addition, each memory cell in the above-mentioned memory cell array 510 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0122] In some examples, the memory cell may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, the first storage state "0" may correspond to a first threshold voltage range, and the second storage state "1" may correspond to a second threshold voltage range. In other examples, each memory cell may be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple level cell (TLC)), or four bits per cell (also known as a quad level cell (QLC)).

[0123] In some examples, the peripheral circuit 520 can be coupled to the memory cell array 510 via a bit line (BL), a word line (WL), a source line (Source Line), a source select gate (SSG), and a drain select gate (DSG). Here, the peripheral circuit can include any suitable analog, digital, and mixed signal circuits for facilitating the relevant operation of the memory cell array by applying a voltage signal and / or a current signal to each target memory cell via a bit line, a word line, a source line, an SSG, or a DSG, and sensing a voltage signal and / or a current signal from each target memory cell. In addition, the peripheral circuit can also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0124] In the embodiment of the present disclosure, the peripheral circuit can be any suitable memory cell array. Figure 6 , the peripheral circuits of the memory device provided by the embodiments of the present disclosure are described in detail.

[0125] refer to Figure 6 , Figure 6 Schematic diagram of a memory device with peripheral circuits provided by an embodiment of the present disclosure. Figure 6 As shown, the memory device 600 includes a memory cell array 610 and peripheral circuits, wherein the peripheral circuits include a page buffer / sense amplifier 621, a column decoder / bit line driver 622, a row decoder / word line driver 623, a voltage generator 624, a control logic unit 625, a register 626, an interface 627, and a data bus 628. It should be understood that in some examples, the peripheral circuits may also include Figure 6 Additional peripheral circuitry not shown.

[0126] The page buffer / sense amplifier 621 can be configured to read data from the memory cell array 610 and program (write) data to the memory cell array 610 according to a control signal from the control logic unit 625. In one example, the page buffer / sense amplifier 621 can store a page of programming data (write data) to be programmed into a memory page of the memory cell array 610. In another example, the page buffer / sense amplifier 621 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 621 can also sense a low-power signal from the bit line representing the data bit stored in the memory cell and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 622 can be configured to be controlled by the control logic unit 625 and select one or more memory cell strings by applying a bit line voltage generated from the voltage generator 624.

[0127] The row decoder / word line driver 623 can be configured to be controlled by the control logic unit 625 and select / deselect memory blocks of the memory cell array 610 and select / deselect word lines of the memory blocks. The row decoder / word line driver 623 can also be configured to drive word lines using word line voltages generated from the voltage generator 624. In some examples, the row decoder / word line driver 623 can also select / deselect and drive source select gates and drain select gates. As described in detail below, the row decoder / word line driver 623 is configured to perform an erase operation on memory cells coupled to (one or more) selected word lines. The voltage generator 624 can be configured to be controlled by the control logic unit 625 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verification voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 610.

[0128] The control logic unit 625 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The register 626 may be coupled to the control logic unit 625 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 627 may be coupled to the control logic unit 625 and act as a control buffer to buffer the data from the host ( Figure 6The interface 627 is configured to receive control commands received from the memory cell array 610 (not shown) and relay them to the control logic unit 625, and to buffer and relay status information received from the control logic unit 625 to the host. The interface 627 may also be coupled to the column decoder / bit line driver 622 via the data bus 628 and function as a data I / O interface and data buffer to buffer and relay data to or from the memory cell array 610.

[0129] refer to Figure 7 , Figure 7 Schematic diagram of a memory system provided by an embodiment of the present disclosure. Figure 7 As shown, an embodiment of the present disclosure provides a memory system, the memory system 700 includes: a memory device 710 and a controller 720; wherein the memory device 710 is further provided with a peripheral circuit 711; the controller 720 is connected to the memory device 710 and is used to control the memory device 710.

[0130] In the embodiment of the present disclosure, the memory system may be a memory card or a solid-state drive.

[0131] refer to Figure 8 , Figure 8 Schematic diagram of a system with a memory device provided in an embodiment of the present disclosure. Figure 8 As shown, the system 800 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 8 As shown, system 800 may include a host 820 and a memory system 810, wherein the memory system 810 has one or more memory devices 811 and a controller 812. The host 820 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 820 may be configured to send data to the memory device 811 or receive data from the memory device 811.

[0132] The memory device 811 can be any memory device disclosed in the present disclosure. The memory device 811 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have reduced leakage current from a driver transistor (e.g., a bit line driver) coupled to an unselected word line during an erase operation, which allows for further size reduction of the driver transistor.

[0133] In some examples, controller 812 is coupled to memory device 811 and host 820 and is configured to control memory device 811. Controller 812 can manage data stored in memory device 811 and communicate with host 820. In some examples, controller 812 is designed to operate in low-duty-cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some examples, controller 812 is designed to operate in high-duty-cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage devices for mobile devices such as smartphones, tablets, laptops, etc. Controller 812 can be configured to control operations of memory device 811, such as read, erase, and program operations. Controller 812 can also be configured to manage various functions related to data stored or to be stored in memory device 811, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some examples, the controller 812 is further configured to process error correction codes (ECC) on data read from or written to the memory device 811. The controller 812 may also perform any other suitable functions, such as formatting the memory device 811. The controller 812 may communicate with an external device (e.g., the host 820) according to a specific communication protocol. For example, the controller 812 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer miniature interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0134] The controller 812 and one or more memory devices 811 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 810 can be implemented and packaged into different types of terminal electronic products. Figure 9AIn one example shown, the controller 812 and the single memory device 811 may be integrated into a memory card 910. The memory card 910 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a standard flash memory (Compact Flash, CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 910 may also include a computer that connects the memory card 910 to a host (e.g., Figure 8 820) is coupled to a memory card connector 920. Figure 9B In another example shown in FIG, the controller 812 and the plurality of memory devices 811 may be integrated into a solid-state drive 930. The solid-state drive 930 may also include a method for connecting the solid-state drive 930 to a host (e.g., Figure 8 820) is shown coupled to a solid-state drive connector 940. In some examples, the storage capacity and / or operating speed of the solid-state drive 930 is greater than the storage capacity and / or operating speed of the memory card 910.

[0135] An embodiment of the present disclosure provides an electronic device, which includes the memory system in the above technical solution.

[0136] In some embodiments, the electronic device includes at least one of the following: a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device, and a mobile power supply.

[0137] Embodiments of the present disclosure provide a latch and a driving method, a page buffer, a memory device, and a memory system. The latch includes: a data latch unit, a data input unit, a current control unit and a sensing transistor; wherein the data latch unit includes: a first inverter and a second inverter; the output end of the first inverter is connected to the input end of the second inverter and is connected to a first node; the input end of the first inverter is connected to the output end of the second inverter and is connected to a second node; the data input unit includes: a first transistor and a second transistor, the control terminal of the first transistor is connected to the first input end, and the first terminal of the first transistor is connected to the first node; the control terminal and the second input end of the second transistor are connected, and the first terminal of the second transistor is connected to the second node; the current control unit includes: a third transistor and a fourth transistor, the control terminal of the third transistor is connected to the first input end, and the second terminal of the third transistor is connected to the first inverter; the control terminal and the second input end of the fourth transistor are connected; the second terminal of the fourth transistor is connected to the second inverter; the first terminal of the third transistor and the first terminal of the fourth transistor are connected to the power supply voltage; the control terminal of the sensing transistor is connected to the sensing node, the first terminal of the sensing transistor is connected to the second terminal of the first transistor and the second terminal of the second transistor, and the second terminal of the sensing transistor is grounded. In the embodiment of the present disclosure, by setting the control terminals of the third transistor in the current control unit and the first transistor in the data input unit to be connected to the first input terminal, and the control terminals of the fourth transistor in the current control unit and the second transistor in the data input unit to be connected to the second input terminal, not only can the DC current passing through the data latch unit be effectively reduced, but also the transient current passing through the data latch unit can be reduced during the flipping operation of the latch, thereby improving power supply efficiency.

[0138] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0139] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A latch, characterized in that: The latch includes: a data latch unit, a data input unit, a current control unit and a sensing transistor; wherein, The data latch unit includes: a first inverter and a second inverter; an output terminal of the first inverter is connected to an input terminal of the second inverter and is connected to a first node; an input terminal of the first inverter is connected to an output terminal of the second inverter and is connected to a second node; The data input unit includes: a first transistor and a second transistor, wherein the control terminal of the first transistor is connected to the first input terminal, and the first terminal of the first transistor is connected to the first node; the control terminal of the second transistor is connected to the second input terminal, and the first terminal of the second transistor is connected to the second node; The current control unit includes: a third transistor and a fourth transistor, wherein the control terminal of the third transistor is connected to the first input terminal, and the second terminal of the third transistor is connected to the first inverter; the control terminal of the fourth transistor is connected to the second input terminal; the second terminal of the fourth transistor is connected to the second inverter; and the first terminal of the third transistor and the first terminal of the fourth transistor are connected to a power supply voltage; The control terminal of the sensing transistor is connected to the sensing node, the first terminal of the sensing transistor is connected to the second terminal of the first transistor and the second terminal of the second transistor, and the second terminal of the sensing transistor is grounded.

2. The latch according to claim 1, wherein: The first inverter includes a first P-type transistor and a first N-type transistor; the second inverter includes a second P-type transistor and a second N-type transistor; wherein, The control terminal of the first P-type transistor is connected to the second node, the first terminal of the first P-type transistor is connected to the second terminal of the third transistor, and the second terminal of the first P-type transistor is connected to the first node; The control terminal of the first N-type transistor is connected to the second node, the first terminal of the first N-type transistor is connected to the first node, and the second terminal of the first N-type transistor is grounded; a control terminal of the second P-type transistor connected to the first node, a first terminal of the second P-type transistor connected to the second terminal of the fourth transistor, and a second terminal of the second P-type transistor connected to the second node; A control terminal of the second N-type transistor is connected to the first node, a first terminal of the second N-type transistor is connected to the second node, and a second terminal of the second N-type transistor is connected to a ground voltage.

3. The latch according to claim 1, wherein: The first transistor, the second transistor and the sensing transistor are N-type transistors; The third transistor and the fourth transistor are P-type transistors.

4. The latch according to claim 1, wherein: The current control unit further includes: a fifth transistor and a sixth transistor; wherein, The control terminal of the fifth transistor is connected to the third input terminal, the first terminal of the fifth transistor is connected to the first inverter, and the second terminal of the fifth transistor is grounded; The control terminal of the sixth transistor is connected to the fourth input terminal, the first terminal of the sixth transistor is connected to the second inverter, and the second terminal of the sixth transistor is grounded; Among them, the first input end is used to input a first signal, the second input end is used to input a second signal, the third input end is used to input a third signal that is an inverted signal of the second signal; and the fourth input end is used to input a fourth signal that is an inverted signal of the first signal.

5. The latch according to claim 4, wherein: The first inverter includes a first P-type transistor and a first N-type transistor; the second inverter includes a second P-type transistor and a second N-type transistor; wherein, The control terminal of the first P-type transistor is connected to the second node, the first terminal of the first P-type transistor is connected to the second terminal of the third transistor, and the second terminal of the first P-type transistor is connected to the first node; The control terminal of the first N-type transistor is connected to the second node, the first terminal of the first N-type transistor is connected to the first node, and the second terminal of the first N-type transistor is connected to the first terminal of the fifth transistor; a control terminal of the second P-type transistor connected to the first node, a first terminal of the second P-type transistor connected to the second terminal of the fourth transistor, and a second terminal of the second P-type transistor connected to the second node; A control terminal of the second N-type transistor is connected to the first node, a first terminal of the second N-type transistor is connected to the second node, and a second terminal of the second N-type transistor is connected to the first terminal of the sixth transistor.

6. The latch according to claim 4, wherein: The fifth transistor and the sixth transistor are N-type transistors.

7. The latch according to claim 1, wherein: The current control unit further includes: a seventh transistor; wherein, The control terminal of the seventh transistor is connected to the fifth input terminal, the first terminal of the seventh transistor is connected to the data latch unit, and the second terminal of the seventh transistor is grounded; Among them, the first input end is used to input the first signal, the second input end is used to input the second signal, and the fifth input end is used to input the fifth signal. The fifth signal is a signal obtained by performing a logical AND operation on the inverted signal of the first signal and the inverted signal of the second signal.

8. The latch according to claim 7, wherein: The first inverter includes a first P-type transistor and a first N-type transistor; the second inverter includes a second P-type transistor and a second N-type transistor; wherein, The control terminal of the first P-type transistor is connected to the second node, the first terminal of the first P-type transistor is connected to the second terminal of the third transistor, and the second terminal of the first P-type transistor is connected to the first node; The control terminal of the first N-type transistor is connected to the second node, the first terminal of the first N-type transistor is connected to the first node, and the second terminal of the first N-type transistor is connected to the first terminal of the seventh transistor; a control terminal of the second P-type transistor connected to the first node, a first terminal of the second P-type transistor connected to the second terminal of the fourth transistor, and a second terminal of the second P-type transistor connected to the second node; A control terminal of the second N-type transistor is connected to the first node, a first terminal of the second N-type transistor is connected to the second node, and a second terminal of the second N-type transistor is connected to the first terminal of the seventh transistor.

9. The latch according to claim 7, wherein: The seventh transistor is an N-type transistor.

10. A latch driving method, characterized in that: The driving method is applied to the latch according to any one of claims 1 to 9; the driving method comprises: If the voltage of the sensing node is less than the flip voltage, when the sensing transistor is turned on, the power supply voltage VDD is input to the first input terminal, and the ground voltage VSS is input to the second input terminal, then the voltage of the first node decreases from VDD to VDD / 2, and the voltage of the second node increases from VSS to VDD / 2; If the voltage of the sensing node is greater than or equal to the flip voltage, when the sensing transistor is turned on, VDD is input to the first input terminal and VSS is input to the second input terminal, then the voltage of the first node flips from VDD to VSS, and the voltage of the second node flips from VSS to VDD.

11. A page buffer, characterized in that: The page buffer includes: at least one latch according to any one of claims 1 to 9; wherein the latch is used to store program verification information or bit line forcing information.

12. A memory device, characterized in that: The memory device comprises: a memory cell array and a peripheral circuit; wherein, The memory cell array has a plurality of memory cell strings and a plurality of bit lines connected to the plurality of memory cell strings; The peripheral circuit is connected to the memory cell array through the bit line and is used to operate the memory cell array; wherein a plurality of page buffers as claimed in claim 11 are arranged in the peripheral circuit, and the page buffers are connected to the memory cell string through the bit line.

13. A memory system, characterized in that: The memory system comprises: the memory device according to claim 12 and a controller; wherein the controller is connected to the memory device and is used to control the memory device.

14. An electronic device, characterized in that: The electronic device comprises the memory system of claim 13.

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