Memory, data processing structures and data analysis methods

Abstract

Embodiments of the present application relate to the field of semiconductor circuit design, and in particular to a memory, a data processing structure, and a data analysis method, including: a storage module, storing initial data and first verification data; an ECC module, configured to compile and generate first verification data corresponding to the initial data based on the initial data to be stored in the storage module, and store the initial data and the first verification data in the storage module; the ECC module is also configured to compile and generate second verification data corresponding to the initial data based on the initial data read from the storage module, and verify and correct the initial data read from the storage module based on the second verification data and the first verification data read from the storage module; an interface module, acquiring the initial data to be stored in the storage module, and outputting the corrected initial data and the first verification data; and a control module, configured to control the interface module to acquire and output the first verification data, so as to provide a simple and reliable testing method for the ECC function of the memory.

Description

Technical Field

[0001] The present application relates to the field of semiconductor circuit design, and in particular to a memory, a data processing structure and a data analysis method. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. With the development of semiconductor technology, DRAM technology has become increasingly advanced, and the integration of memory cells has become increasingly higher. At the same time, various applications have also placed increasingly higher demands on DRAM performance, power consumption, and reliability.

[0003] In order to ensure that data storage is error-free, an error correction code (ECC) function is introduced to verify the stored data to improve the accuracy of DRAM data storage. That is, ensuring the correct operation of the ECC function can ensure that the stored data is error-free to a certain extent.

[0004] However, the applicant has found that the current testing environment for the ECC function in DRAM is relatively limited, and there is an urgent need to design a simple and reliable testing method to test whether the ECC function in DRAM is normal. Summary of the Invention

[0005] The embodiments of the present application provide a memory, a data processing structure, and a data analysis method. After the memory is put into use, it is also possible to test whether the ECC function in the memory is normal.

[0006] An embodiment of the present application provides a memory, including: a storage module for storing initial data and first verification data; an ECC module, configured to compile and generate first verification data corresponding to the initial data based on the initial data to be stored in the storage module, and store the initial data and the first verification data in the storage module; the ECC module is also configured to compile and generate second verification data corresponding to the initial data based on the initial data read from the storage module, and verify and correct the initial data read from the storage module based on the second verification data and the first verification data read from the storage module; an interface module, configured to obtain the initial data to be stored in the storage module, and to output the corrected initial data and first verification data; and a control module, configured to control the interface module to obtain and output the first verification data.

[0007] An embodiment of the present application provides a data processing structure for writing data into a storage unit of a memory or reading data stored in the storage unit, including: a verification module, configured to compile and generate first verification data corresponding to the initial data based on initial data to be stored in the storage unit, and store the initial data and the first verification data in the storage unit; the verification module is also configured to compile and generate second verification data corresponding to the initial data based on the initial data read from the storage unit, and verify and correct the initial data read from the storage unit based on the second verification data and the first verification data read from the storage unit; an input / output module, used to obtain the initial data to be stored in the storage unit, and used to output the corrected initial data and the first verification data; and a control module, configured to control the input / output module to obtain and output the first verification data.

[0008] An embodiment of the present application provides a data analysis method, which is applied to the above-mentioned memory, including: in a data writing phase, an interface module obtains initial data to be stored in a storage module, an ECC module compiles and generates first verification data corresponding to the initial data based on the initial data, and stores the initial data and the first verification data in the storage module; in a data reading phase, the ECC module is used to obtain the initial data read from the storage module, and compile and generate second verification data corresponding to the initial data based on the initial data read from the storage module, and correct the initial data according to the second verification data and the first verification data read from the storage module, and output the verified and corrected initial data; a control module is used to generate a control signal according to an instruction, and the control signal is used to control the ECC module to output the first verification data to the interface module in the data reading phase; based on the read first verification data and the corrected initial data, it is judged whether the compilation operation of the ECC module is correct.

[0009] After the memory is put into use, the control module controls the ECC module to output the first verification data, and the first verification data is output from the interface module together with the corrected initial data. The output initial data and the first verification data are used to determine whether the verification function of the ECC module is normal. That is, after the memory is put into use, a relatively simple method can still be used to verify the ECC function. The test environment is real and the test data obtained is more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of the structure of a memory provided in one embodiment of the present application;

[0011] Figure 2 A schematic diagram of the specific structure of a memory provided in one embodiment of the present application;

[0012] Figure 3 A schematic diagram of a data processing structure provided in another embodiment of the present application;

[0013] Figure 4 A schematic diagram of a data processing structure according to another embodiment of the present invention;

[0014] Figure 5 A flowchart of a data analysis method provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0015] In order to ensure that data storage is error-free, an error correction code (ECC) function is introduced to verify the stored data to improve the accuracy of DRAM data storage. That is, ensuring the correct operation of the ECC function can ensure that the stored data is error-free to a certain extent.

[0016] The applicant has found that the current testing environment for the ECC function in DRAM is relatively limited, and there is an urgent need to design a simple and reliable testing method to test whether the ECC function in DRAM is normal.

[0017] An embodiment of the present application provides a memory, including: a storage module for storing initial data and first verification data; an ECC module, configured to compile and generate first verification data corresponding to the initial data based on the initial data to be stored in the storage module, and store the initial data and the first verification data in the storage module; the ECC module is also configured to compile and generate second verification data corresponding to the initial data based on the initial data read from the storage module, and verify and correct the initial data read from the storage module based on the second verification data and the first verification data read from the storage module; an interface module, configured to obtain the initial data to be stored in the storage module, and to output the corrected initial data and first verification data; and a control module, configured to control the interface module to obtain and output the first verification data.

[0018] Those skilled in the art will appreciate that, in the various embodiments of this application, many technical details are provided to help readers better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0019] Figure 1 A schematic diagram of the structure of the memory provided in this embodiment, Figure 2 The specific structural diagram of the memory provided in this embodiment is further described in detail below with reference to the accompanying drawings, as follows:

[0020] refer to Figure 1 , memory, including:

[0021] The ECC module 102 is configured to compile and generate first parity data Parity1 corresponding to the initial data Data to be stored in the storage module 101 , and store the initial data Data and the first parity data Parity1 in the storage module 101 .

[0022] It should be noted that, in this embodiment, the initial data Data is illustrated by taking a 128-bit binary number as an example, which does not constitute a limitation of this embodiment; in specific applications, the data length of the initial data Data can be adjusted according to the data length required to be stored in the memory. Accordingly, the first check data Parity1 compiled and generated by the ECC module 102 based on the initial data Data is an 8-bit binary number.

[0023] The storage module 101 is configured to store initial data Data and first verification data Parity1.

[0024] The initial data Data is stored in the data storage area of ​​the storage module 101 , and the first verification data Parity1 is stored in the verification storage area of ​​the storage module 101 .

[0025] In an example, the initial data Data stored in the data storage area is stored in 16 groups of 8 bits to ensure that the storage space of each storage unit in the data storage area is consistent with the storage space of the storage unit in the verification storage area; it should be noted that the initial data Data stored in the data storage area can be divided according to the division method of the storage space of the memory storage unit. This embodiment does not constitute a limitation on the data division during data storage.

[0026] The ECC module 102 is further configured to compile and generate second parity data Parity2 corresponding to the initial data Data based on the initial data Data read from the storage module 101, and to verify and correct the initial data Data read from the storage module 101 based on the second parity data Parity2 and the first parity data Parity1 read from the storage module 101.

[0027] Since the memory stores data in the form of level storage, and the level stored data may cause the written data and the read data to be different due to the change of the level, ECC is needed to detect and correct errors in the written data and the read data.

[0028] Specifically, if the second verification data Parity2 compiled based on the read data Data is consistent with the read first verification data Parity1, it means that the initial data Data to be stored in the storage module 101 is consistent with the initial data Data read from the storage module 101, and the initial data Data has not changed during the access process; if the second verification data Parity2 compiled based on the read data Data is different from the read first verification data Parity1, it means that the initial data Data to be stored in the storage module 101 is different from the initial data Data read from the storage module 101, and the initial data Data has changed during the access process.

[0029] Furthermore, if only one bit of the initial data Data changes, the initial data Data can be repaired according to the second verification data Parity2 and the first verification data Parity1. If the number of bits of the initial data Data that change is greater than 1, the initial data cannot be repaired.

[0030] The interface module 103 is used to obtain the initial data Data to be stored in the storage module 101 and to output the first verification data Parity1 and the corrected initial data Data′.

[0031] The control module 104 is configured to control the interface module 103 to obtain and output the first verification data Parity1.

[0032] For a memory in a normal operating state, its ECC function will not output verification data after verification and repair, so it is impossible to verify whether the ECC function of the memory put into use is normal. In this embodiment, the control module 104 controls the interface module 103 to output the first verification data Parity1, thereby realizing the ECC function detection of the memory put into use.

[0033] Specifically, the detection data is compiled and generated based on the read corrected initial data Data′. If the detection data is the same as the read first verification data Parity1, the compilation operation of the ECC module is correct. If the detection data is different from the read first verification data Parity1, the compilation operation of the ECC module is wrong.

[0034] It should be noted that the compilation algorithm for compiling the read-out corrected initial data Data′ is consistent with the compilation algorithm of the ECC module 102; in addition, it is also possible to determine whether the ECC module 102 is working by comparing the initial data Data and the corrected initial data Data′.

[0035] In addition, in this embodiment, the memory further includes: a data channel 105 connecting the interface module 103 and the ECC module 102 , and used for data transmission between the interface module 103 and the ECC module 102 .

[0036] In one example, the data channel 105 includes: a first data path 115, which is used for the interface module 103 to transmit the initial data Data to the ECC module 102, and for the ECC module 102 to transmit the corrected initial data Data′ to the interface module 103; a second data path 125, which is used for the ECC module 102 to transmit the first verification data Parity1 to the interface module 103, that is, the first data path 115 transmits real data, and the second data path 125 transmits verification data, and the accuracy of data transmission is guaranteed by the classified transmission of data.

[0037] In some embodiments, reference Figure 2 The control module 104 includes: a signal receiving unit 124, which is used to receive external instructions and generate a control signal based on the external instructions; a processing unit 114, which controls the interface module 103 to obtain and output the first verification data Parity1 based on the control signal, that is, to control the ECC function test of the memory through interaction between the memory and the outside to avoid unnecessary data transmission.

[0038] In some embodiments, the second data path 125 is enabled based on the control signal, which further ensures that the memory outputs the first parity data Parity1 only when the ECC function is tested.

[0039] In some embodiments, reference Figure 2 The interface module 103 includes: a data pad 113, the external data received by the data pad 113 is used as the initial data Data to be stored in the storage module 101, the initial data Data is written into the storage module 101 through the data pad 113, and the initial data Data read from the storage module 101 is output through the data pad 113; a mask pad 123, used to output the first verification data Parity1, through the classified output of the data pad 113 and the mask pad 123, that is, the classified transmission of data, to ensure the accuracy of data transmission.

[0040] Furthermore, normal memory data reading and writing processes may involve masking operations, which are based on whether the control terminal sends a mask and whether the relevant masking function is enabled. Masking operations are not used during ECC testing of the memory. That is, during ECC testing, the memory's mask pads are essentially useless. Therefore, using the mask pads to output the first parity data, Parity1, does not require adding pads to the memory and does not change the memory's external structure.

[0041] In some embodiments, the memory further includes a cache module (not shown), connected to the interface module 103 , for caching the initial data Data written from the interface module 103 , or for caching the initial data Data to be output from the interface module 103 .

[0042] After the memory is put into use, the control module controls the ECC module to output the first verification data, and the first verification data is output from the interface module together with the corrected initial data. The output initial data and the first verification data are used to determine whether the verification function of the ECC module is normal. That is, after the memory is put into use, a relatively simple method can still be used to verify the ECC function. The test environment is real and the test data obtained is more reliable.

[0043] It is worth mentioning that all units involved in this embodiment are logical units. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovation of this application, this embodiment does not include units that are not closely related to solving the technical problem proposed by this application. However, this does not mean that other units do not exist in this embodiment.

[0044] Another embodiment of the present application provides a data processing structure for writing data into a storage unit of a memory or reading data stored in the storage unit, including: a verification module, configured to compile and generate first verification data corresponding to the initial data based on the initial data to be stored in the storage unit, and store the initial data and the first verification data in the storage unit; the verification module is also configured to compile and generate second verification data corresponding to the initial data based on the initial data read from the storage unit, and verify and correct the initial data read from the storage unit based on the second verification data and the first verification data read from the storage unit; an input / output module, used to obtain the initial data to be stored in the storage unit, and to output the corrected initial data and the first verification data; and a control module, configured to control the input / output module to obtain and output the first verification data.

[0045] Figure 3 A schematic diagram of the data processing structure provided in this embodiment. Figure 4 The data processing structure provided in this embodiment is a schematic diagram of a specific structure. The data processing structure provided in this embodiment is further described in detail below with reference to the accompanying drawings, as follows:

[0046] refer to Figure 3 The data processing structure 200 is used to write data into a storage unit of the memory or read out the verification data stored in the storage unit, including:

[0047] The verification module 202 is configured to compile and generate first verification data Parity1 corresponding to the initial data Data to be stored in the storage unit based on the initial data Data, and store the initial data Data and the first verification data Parity1 in the storage unit.

[0048] The verification module 202 is further configured to compile and generate second verification data Parity2 corresponding to the initial data Data based on the initial data Data read from the storage unit, and verify and correct the initial data Data read from the storage unit according to the second verification data Parity2 and the first verification data Parity1 read from the storage unit.

[0049] Since the memory stores data in the form of level storage, and the level stored data may cause the written data and the read data to be different due to the change of the level, ECC is needed to detect and correct errors in the written data and the read data.

[0050] Specifically, if the second verification data Parity2 compiled based on the read data Data is consistent with the read first verification data Parity1, it means that the initial data Data to be stored in the storage unit is consistent with the initial data Data read from the storage unit, and the initial data Data has not changed during the access process; if the second verification data Parity2 compiled based on the read data Data is different from the read first verification data Parity1, it means that the initial data Data to be stored in the storage unit is different from the initial data Data read from the storage unit, and the initial data Data has changed during the access process.

[0051] Furthermore, if only one bit of the initial data Data changes, the initial data Data can be repaired according to the second verification data Parity2 and the first verification data Parity1. If the number of bits of the initial data Data that change is greater than 1, the initial data cannot be repaired.

[0052] The input / output module 203 is used to obtain the initial data Data to be stored in the storage unit, and to output the first verification data Parity1 and the corrected initial data Data′.

[0053] The control module 204 is configured to control the input / output module 203 to obtain and output the first verification data Parity1.

[0054] The test data is compiled and generated based on the read corrected initial data Data′. If the test data is the same as the read first verification data Parity1, the compilation operation of the ECC module is correct. If the test data is different from the read first verification data Parity1, the compilation operation of the ECC module is wrong.

[0055] It should be noted that the compilation algorithm for compiling the read-out corrected initial data Data′ is consistent with the compilation algorithm of the ECC module 102; in addition, it is also possible to determine whether the ECC module 102 is working by comparing the initial data Data and the corrected initial data Data′.

[0056] In addition, in this embodiment, the data processing structure 200 further includes: a data channel 205 connecting the input / output module 203 and the verification module 202 for data transmission between the input / output module 203 and the verification module 202.

[0057] In one example, the data channel 205 includes: a first data path 215, used for the input / output module 203 to transmit the initial data Data to the verification module 202, and used for the verification module 202 to transmit the corrected initial data Data′ to the input / output module 203; a second data path 225, used for the verification module 202 to transmit the first verification data Parity1 to the input / output module 203, that is, the first data path 115 transmits real data, and the second data path 125 transmits verification data, and the accuracy of data transmission is guaranteed by the classified transmission of data.

[0058] In some embodiments, the control module 204 includes: a signal receiving unit 224, which is used to receive external instructions and generate a control signal based on the external instructions; a processing unit 214, which controls the input / output module 203 to obtain and output the first verification data Parity1 based on the control signal, that is, to control the ECC function test of the memory through interaction between the memory and the outside to avoid unnecessary data transmission.

[0059] In some embodiments, the second data path 125 is enabled based on the control signal, which further ensures that the memory outputs the first parity data Parity1 only when the ECC function is tested.

[0060] In some embodiments, reference Figure 4, the data pad 213 and the mask pad 223 of the memory are used as the input / output module 203, the data pad 213, the external data received by the data pad 213 is used as the initial data Data to be stored in the storage unit, the initial data Data is written into the storage unit through the data pad 213, and the initial data Data read from the storage unit is output through the data pad 213; the mask pad 223 is used to output the first verification data Parity1, through the classified output of the data pad 213 and the mask pad 223, that is, the classified transmission of data, to ensure the accuracy of data transmission.

[0061] Furthermore, normal memory data reading and writing processes may involve masking operations, which are based on whether the control terminal sends a mask and whether the relevant masking function is enabled. Masking operations are not used during ECC testing of the memory. That is, during ECC testing, the memory's mask pads are essentially useless. Therefore, using the mask pads to output the first parity data, Parity1, does not require adding pads to the memory and does not change the memory's external structure.

[0062] In some embodiments, the memory further includes a cache module (not shown), connected to the input / output module 203 , for caching the initial data Data written from the input / output module 203 , or for caching the initial data Data to be output from the input / output module 203 .

[0063] After the memory is put into use, the control module controls the ECC module to output the first verification data, and the first verification data is output from the interface module together with the corrected initial data. The output initial data and the first verification data are used to determine whether the verification function of the ECC module is normal. That is, after the memory is put into use, a relatively simple method can still be used to verify the ECC function. The test environment is real and the test data obtained is more reliable.

[0064] It is worth mentioning that all units involved in this embodiment are logical units. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovation of this application, this embodiment does not include units that are not closely related to solving the technical problem proposed by this application. However, this does not mean that other units do not exist in this embodiment.

[0065] Another embodiment of the present application provides a data analysis method, which is applied to the above-mentioned memory, including: in the data writing stage, the interface module obtains the initial data to be stored in the storage module, the ECC module compiles and generates first verification data corresponding to the initial data based on the initial data, and stores the initial data and the first verification data into the storage module; in the data reading stage, the ECC module is used to obtain the initial data read from the storage module, and compile and generate second verification data corresponding to the initial data based on the initial data read from the storage module, and correct the initial data according to the second verification data and the first verification data read from the storage module, and output the verified and corrected initial data; the control module is used to generate a control signal according to an instruction, and the control signal is used to control the ECC module to output the first verification data to the interface module in the data reading stage; based on the read first verification data and the corrected initial data, it is judged whether the compilation operation of the ECC module is correct.

[0066] Figure 5 The following is a flow chart of the data analysis method provided in this embodiment. The data analysis method provided in this embodiment is further described in detail with reference to the accompanying drawings, as follows:

[0067] refer to Figure 1 、 Figure 2 and Figure 5 , data analysis methods, including:

[0068] Step 1: In the data writing phase, write the initial data.

[0069] Specifically, in the data writing stage, the interface module 103 obtains the initial data Data to be stored in the storage module 101, the ECC module 102 compiles and generates the first verification data Parity1 corresponding to the initial data Data based on the initial data Data, and stores the initial data Data and the first verification data Parity1 into the storage module 101.

[0070] Step 2: In the data reading phase, the corrected initial data and the first verification data are read out.

[0071] Specifically, the ECC module 101 is used to obtain the initial data Data read from the storage module 101, and compile and generate second verification data Parity2 corresponding to the initial data Data based on the initial data Data read from the storage module 101, and verify and correct the initial data Data according to the second verification data Parity2 and the first verification data Parity1 read from the storage module 101, and output the corrected initial data Data′.

[0072] The control module 104 is used to generate a control signal according to the instruction, and the control signal is used to control the ECC module 102 to output the first parity data Parity1 to the interface module 103 during the data reading phase.

[0073] Since the memory stores data in the form of level storage, and the level stored data may cause the written data and the read data to be different due to the change of the level, ECC is needed to detect and correct errors in the written data and the read data.

[0074] Specifically, if the second verification data Parity2 compiled based on the read data Data is consistent with the read first verification data Parity1, it means that the initial data Data to be stored in the storage module 101 is consistent with the initial data Data read from the storage module 101, and the initial data Data has not changed during the access process; if the second verification data Parity2 compiled based on the read data Data is different from the read first verification data Parity1, it means that the initial data Data to be stored in the storage module 101 is different from the initial data Data read from the storage module 101, and the initial data Data has changed during the access process.

[0075] Furthermore, if only one bit of the initial data Data changes, the initial data Data can be repaired according to the second verification data Parity2 and the first verification data Parity1. If the number of bits of the initial data Data that change is greater than 1, the initial data cannot be repaired.

[0076] Based on the read first parity data Parity1 and the corrected initial data Data, it is determined whether the ECC module compilation operation is correct. Specifically, the third step: obtaining test data based on the corrected initial data compilation.

[0077] Specifically, the detection data is compiled and generated according to the corrected initial data Data′ read from the interface module 103 .

[0078] It is understandable that, when the ECC function is normal, the corrected initial data Data' read from the interface module 103 should be consistent with the initial data Data written into the storage module 101. Therefore, the detection data can also be compiled based on the initial data Data written into the storage module 101.

[0079] For a memory in a normal operating state, its ECC function will not output verification data after verification and repair, so it is impossible to verify whether the ECC function of the memory put into use is normal. In this embodiment, the control module 104 controls the interface module 103 to output the first verification data Parity1, thereby realizing the ECC function detection of the memory put into use.

[0080] It should be noted that the compilation algorithm for compiling the read-out corrected initial data Data′ is consistent with the compilation algorithm of the ECC module 102; in addition, it is also possible to determine whether the ECC module 102 is working by comparing the initial data Data and the corrected initial data Data′.

[0081] Step 4: Determine whether the ECC module compilation operation is correct.

[0082] Specifically, if the detection data is identical to the read first verification data Parity1 , the compilation operation of the ECC module is correct; if the detection data is different from the read first verification data Parity1 , the compilation operation of the ECC module is incorrect.

[0083] In this embodiment, the data pad 113 and the mask pad 123 of the memory are used as the interface module 103, the data pad 113, the external data received by the data pad 113 is used as the initial data Data to be stored in the storage module 101, the initial data Data is written into the storage module 101 through the data pad 113, and the initial data Data read from the storage module 101 is output through the data pad 113; the mask pad 123 is used to output the second verification data Parity2, and the classification output through the data pad 113 and the mask pad 123, that is, the classification transmission of the data, ensures the accuracy of data transmission.

[0084] Furthermore, normal memory data reading and writing processes may involve masking operations, which are based on whether the control terminal sends a mask and whether the relevant masking function is enabled. Masking operations are not used during ECC testing of the memory. That is, during ECC testing, the memory's mask pads are essentially useless. Therefore, using the mask pads to output the first parity data, Parity1, does not require adding pads to the memory and does not change the memory's external structure.

[0085] After the memory is put into use, the control module controls the ECC module to output the first verification data, and the first verification data is output from the interface module together with the corrected initial data. The output initial data and the first verification data are used to determine whether the verification function of the ECC module is normal. That is, after the memory is put into use, a relatively simple method can still be used to verify the ECC function. The test environment is real and the test data obtained is more reliable.

[0086] The above division of various steps is only for the purpose of clear description. During implementation, they can be combined into one step or some steps can be split and decomposed into multiple steps. Adding insignificant modifications to the process or introducing insignificant designs that do not change the core design of the process are all within the scope of protection of this patent.

[0087] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A memory, characterized in that: include: A storage module, configured to store initial data and first verification data; An ECC module is configured to compile and generate first verification data corresponding to the initial data to be stored in the storage module based on the initial data to be stored in the storage module, and store the initial data and the first verification data in the storage module; The ECC module is further configured to compile and generate second check data corresponding to the initial data based on the initial data read from the storage module, and verify and correct the initial data read from the storage module based on the second check data and the first check data read from the storage module; an interface module, configured to obtain the initial data to be stored in the storage module, and to output the corrected initial data and the first verification data; The control module is configured to control the interface module to obtain and output first verification data.

2. The memory according to claim 1, wherein The interface module includes: a data pad, wherein external data received by the data pad is used as the initial data to be stored in the storage module, the initial data is written into the storage module through the data pad, and the initial data read from the storage module is output through the data pad; The mask pad is used to output the first verification data.

3. The memory according to claim 1, wherein: The control module includes: a signal receiving unit, configured to receive an external instruction and generate a control signal based on the external instruction; The processing unit controls the interface module to obtain and output first verification data based on the control signal.

4. The memory according to claim 3, wherein: Also includes: A data channel connects the interface module and the ECC module and is used for data transmission between the interface module and the ECC module.

5. The memory according to claim 4, wherein: The data channel includes: a first data path, for the interface module to transmit the initial data to the ECC module, and for the ECC module to transmit the corrected initial data to the interface module; A second data path is used for the ECC module to transmit the first verification data to the interface module.

6. The memory according to claim 5, wherein: The second data path is turned on based on the control signal.

7. A data processing structure for writing data into a storage unit of a memory or reading data stored in the storage unit, characterized in that: include: a verification module configured to compile and generate first verification data corresponding to the initial data to be stored in the storage unit based on the initial data to be stored in the storage unit, and store the initial data and the first verification data in the storage unit; The verification module is further configured to compile and generate second verification data corresponding to the initial data based on the initial data read from the storage unit, and verify and correct the initial data read from the storage unit according to the second verification data and the first verification data read from the storage unit; an input / output module, configured to obtain initial data to be stored in the storage unit, and to output the corrected initial data and the first verification data; The control module is configured to control the input / output module to obtain and output the first verification data.

8. The data processing structure according to claim 7, characterized in that: include: Using the data pad and mask pad of the memory as the input / output module; The data pad is used to obtain the initial data to be stored in the storage unit and output the corrected initial data; The mask pad is used to output the first verification data.

9. The data processing structure according to claim 7, characterized in that: The control module includes: a signal receiving unit, configured to receive an external instruction and generate a control signal based on the external instruction; The processing unit controls the input / output module to obtain and output first verification data based on the control signal.

10. The data processing structure according to claim 9, characterized in that: Also includes: A data channel connects the input / output module and the verification module and is used for data transmission between the input / output module and the verification module.

11. The data processing structure according to claim 10, characterized in that: The data channel includes: a first data path, for the input / output module to transmit the initial data to the verification module, and for the verification module to transmit the initial data to the input / output module; a second data path, for the verification module to transmit the first verification data to the input / output module; The second data path is enabled based on the control signal.

12. A data analysis method, applied to the memory according to any one of claims 1 to 6, characterized in that: include: In the data writing phase, the interface module obtains the initial data to be stored in the storage module, the ECC module compiles and generates first check data corresponding to the initial data based on the initial data, and stores the initial data and the first check data in the storage module; In a data reading phase, the ECC module is configured to obtain the initial data read from the storage module, compile and generate second check data corresponding to the initial data based on the initial data read from the storage module, verify and correct the initial data based on the second check data and the first check data read from the storage module, and output the corrected initial data; The control module is used to generate a control signal according to the instruction, and the control signal is used to control the ECC module to output the first check data to the interface module during the data reading phase; Based on the read first verification data and the corrected initial data, it is determined whether the compilation operation of the ECC module is correct.

13. The data analysis method according to claim 12, characterized in that: Using the data pad and mask pad of the memory as the interface module; The mask pad is used to output the first verification data; The interface module acquires the initial data to be stored in the storage module, comprising: using data input from the data pad as the initial data to be stored in the storage module, and writing the initial data into the memory through the data pad; The outputting the modified initial data includes: outputting the modified initial data to the outside of the memory through the mask pad.

14. The data analysis method according to claim 13, characterized in that: Determining whether the compilation operation of the ECC module is correct includes: Compile and acquire detection data corresponding to the initial data based on the read initial data; If the detection data is identical to the read first verification data, the compilation operation of the ECC module is correct; If the detection data is different from the read first verification data, the compilation operation of the ECC module is wrong.

15. The data analysis method according to claim 14, characterized in that: The compilation method used for compiling the read initial data to obtain the detection data corresponding to the initial data is the same as the compilation method of the compilation operation of the ECC module.

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