Semiconductor structure manufacturing method and semiconductor structure
By forming a mask with a first sidewall in the semiconductor structure and removing part of the second structure using a patterning layer, the problem of large width difference in self-aligned double patterning technology is solved, thereby improving the yield and reliability of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-11-04
- Publication Date
- 2026-05-26
AI Technical Summary
In existing semiconductor structures formed by self-aligned dual patterning technology, the width difference between the first and second structures along the first direction is significant, which affects the yield and performance of the semiconductor structure.
A first sidewall is formed on the sidewall of a portion of the first structure that is opposite to each other in the first direction to form a first mask. A portion of the second structure is removed from the mask by a first pattern layer to reduce the width difference and form a first mask and a second mask with a smaller width.
By reducing the width difference between the first and second structures along the first direction, the yield and reliability of the semiconductor structure are improved, and subsequent process problems caused by the width difference are reduced.
Smart Images
Figure CN115910760B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology
[0002] In semiconductor structure manufacturing processes, the fabrication of some tiny dimensions requires the formation of tiny patterns with precise dimensions in the semiconductor substrate or the dielectric layer on the substrate using techniques such as photolithography.
[0003] With the development of semiconductor technology, the size of these tiny patterns is constantly decreasing. To meet size requirements, the methods currently available for forming tiny patterns include self-aligned double patterning (SADP) technology, which can achieve excellent linewidth and pitch control.
[0004] However, there is still room for improvement in the yield and performance of semiconductor structures formed using self-aligned dual patterning technology. Summary of the Invention
[0005] This disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, which at least helps to reduce the width difference between the first structure and the second structure along the first direction in a semiconductor structure formed using self-aligned dual patterning technology.
[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, on which a first patterned layer is formed, the first patterned layer comprising a plurality of first structures and a plurality of second structures arranged alternately at intervals, wherein, along a first direction, at least a portion of the width of the first structures is less than the width of a portion of the second structures; forming a first sidewall, the first sidewall being located at least on opposite sidewalls of a portion of the first structures along the first direction, the first structures and the first sidewalls located on the sidewalls of the first structures constituting a first mask; forming a first patterned layer, the first patterned layer being located on the first sidewalls, the first structures, the substrate, and the second structures, and the first patterned layer further having a first opening penetrating the first patterned layer, the first opening being at least directly opposite a portion of the second structures adjacent to the first structures; using the first patterned layer as a mask, removing at least a portion of the second structures adjacent to the first structures along the first opening, the remaining portion of the second structures constituting a second mask; and removing the first patterned layer.
[0007] In some embodiments, prior to forming the first sidewall, the method further includes: forming a second patterned layer, the second patterned layer covering the first structure, the second structure, and the substrate, the second patterned layer having a second opening therein, the second opening exposing at least a portion of the first structure and also exposing a portion of the substrate adjacent to the first structure; in the process step of forming the first sidewall, the first sidewall is also formed on the sidewall of the second patterned layer; the manufacturing method further includes: removing the first sidewall located on the sidewall of the portion of the first structure, removing the first sidewall located on the sidewall of the second patterned layer, and removing the second patterned layer.
[0008] In some embodiments, the process steps of forming the first sidewall include: forming the first sidewall on the top surface and sidewall of the first structure, the top surface and sidewall of the second graphic layer, and the substrate; removing the first sidewall located on the top surface of the first structure, the top surface of the second graphic layer, and a portion of the substrate, while retaining the first sidewall located on the sidewall of the first structure and the sidewall of the second graphic layer.
[0009] In some embodiments, the step of removing the first sidewall located on the sidewall of the second graphic layer includes: removing the second graphic layer, retaining the first sidewall located on the sidewall of the second graphic layer as the target sidewall; forming a third graphic layer, the third graphic layer being located on the first structure, the first sidewall, and the substrate, the third graphic layer having a third opening penetrating the third graphic layer, and the third opening being directly opposite the target sidewall; using the third graphic layer as a mask, removing the target sidewall along the third opening; and removing the third graphic layer.
[0010] In some embodiments, a method for removing the first sidewall located on the sidewall of the second patterned layer includes: removing the second patterned layer, retaining the first sidewall located on the sidewall of the second patterned layer as a target sidewall; in the process step of forming the first patterned layer, the first opening is also directly opposite the target sidewall; in the process step of removing a portion of the second structure adjacent to the first structure along the first opening using the first patterned layer as a mask, the target sidewall is also removed.
[0011] In some embodiments, the step of forming the first sidewall includes: forming a first sidewall that covers the top surface and sidewall of the first structure, the top surface and sidewall of the second structure, and also covers the substrate surface between the first structure and the second structure; in the process step of forming the first patterned layer, the first opening is also directly opposite the first sidewall located on the sidewall of the second structure; in the process step of removing at least a portion of the second structure adjacent to the first structure along the first opening, the step further includes: removing the first sidewall located on the sidewall of the second structure.
[0012] In some embodiments, before forming the first pattern layer, the method further includes: removing the first sidewall located on the top surface of the first structure, a portion of the sidewall of the first structure, and a portion of the first sidewall on the top surface of the second structure, and also removing the first sidewall on the substrate located between the first structure and the second structure.
[0013] In some embodiments, before removing at least a portion of the second structure adjacent to the first structure along the first opening, the method further includes: removing a portion of the first sidewall located on the top surface of the second structure along the first opening.
[0014] In some embodiments, the material of the first sidewall is different from the material of the second structure.
[0015] In some embodiments, the material of the first sidewall is the same as the material of the first structure.
[0016] In some embodiments, the material of the first structure is the same as the material of the second structure.
[0017] In some embodiments, the width of the first mask is the same as the width of the second mask along the first direction.
[0018] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor structure, including: a substrate; a plurality of first masks located on the substrate; a plurality of second masks located on the substrate, at least a portion of the second masks including a first structure and a first sidewall, the first sidewall being located on a sidewall of the first structure opposite to it along a first direction; wherein the plurality of first masks and the plurality of second masks are alternately arranged on the substrate along the first direction, and the width of the first mask is equal to the width of the second mask along the first direction.
[0019] In some embodiments, the material of the first sidewall is the same as the material of the first structure, and the material of the first sidewall may be the same as or different from the material of the second mask.
[0020] In some embodiments, the material of the first mask is the same as the material of the second mask.
[0021] The technical solutions provided in this disclosure have at least the following advantages:
[0022] This disclosure provides a method for manufacturing a semiconductor structure. A first sidewall is formed on opposite sidewalls of a portion of a first structure along a first direction. The first structure and the first sidewall on its sidewall constitute a first mask to increase the width of the portion of the first structure along the first direction. The width of the portion of the first structure along the first direction is smaller than the width of the portion of a second structure. The first sidewall reduces the width difference between the smaller portion of the first structure and the second structure along the first direction. After forming the first sidewall, a first pattern layer is formed. The first pattern layer is located on the first sidewall, the first structure, the substrate, and the second structure. A patterned layer also has a first opening penetrating the first patterned layer. The first opening is at least directly opposite a portion of the second structure adjacent to the first structure. By using the first patterned layer as a mask, removing a portion of the second structure directly opposite the first opening along the first opening can reduce the width of the second structure along the first direction. The remaining portion of the second structure constitutes the second mask. Thus, the width of the formed second mask along the first direction is less different from the width of the first mask. This reduces the phenomenon of subsequent fabrication problems caused by the width difference between the original first structure and the second structure along the first direction, which is beneficial to improving the yield and reliability of the formed semiconductor structure. Attached Figure Description
[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure manufacturing method.
[0025] Figures 7 to 13 This is a schematic diagram of the structure corresponding to each step of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
[0026] Figures 14 to 17 A schematic diagram of the structure corresponding to each step of a method for manufacturing another semiconductor structure according to an embodiment of this disclosure;
[0027] Figure 18 This is a schematic diagram of a semiconductor structure provided in yet another embodiment of the present disclosure. Detailed Implementation
[0028] As can be seen from the background technology, the yield and performance of semiconductor structures formed using self-aligned dual patterning technology still need improvement.
[0029] Figures 1 to 6 This is a schematic diagram illustrating the structural steps involved in the fabrication of a semiconductor structure. (Reference) Figure 1 A substrate 101 is provided, on which an etchable layer 102, a first film layer 103, and a first pattern layer 104 are sequentially formed. The first pattern layer 104 has a first opening 105 penetrating the first pattern layer 104, wherein, along a first direction (e.g., ... Figure 1 (As shown in the X direction), the width of the first opening 105 is three times the width of the first graphic layer 104; Reference Figure 2 Using the first patterned layer 104 as a mask, the portion of the first film layer 103 not covered by the first patterned layer 104 is etched away along the first opening 105. The remaining first film layer 103 constitutes the first structure 106, and the first patterned layer 104 is removed. (Reference) Figure 3 This forms a first sidewall 107, which is located on the opposite sidewall of the first structure 106 along a first direction, wherein the spacing between adjacent first sidewalls 107 along the first direction is equal to the width of the first structure 106; Reference Figure 4 A filling layer 108 is formed, which is located on the sidewall and top surface of the first sidewall 107 and the top surface of the first structure 106. The filling layer 108 is also located on the base 101, wherein the material of the filling layer 108 is the same as the material of the first structure 106; Reference Figure 5 The filler layer 108 located on the top surface of the first sidewall 107 and the top surface of the first structure 106 is removed. The remaining filler layer 108 on the base 101 constitutes the second structure 109. A portion of the filler layer 108 located on the top surface of the base 101 is also removed to ensure that along the second direction (e.g., ... Figure 5 In the Y-direction (as shown), the height of the second structure 109 is equal to the height of the first structure 106, wherein, along the first direction, the width of the first core layer 106 is equal to the width of the second core layer 109; Reference Figure 6 Remove the first side wall 109.
[0030] Analysis revealed that the first structure 106 and the second structure 109 are formed in different steps. Affected by the data fluctuations of the relevant equipment and the measurement feedback to the relevant equipment, errors may occur in each step during the formation of the first structure 106 and the second structure 109. Consequently, along the first direction, the width of part of the first structure 106 and the width of part of the second structure 109 are not completely equal, which is different from the expected result that the width of the first structure 106 is equal to the width of the second structure 109. This result will affect other process steps of the semiconductor structure in the future, thereby affecting the yield and performance of the formed semiconductor structure.
[0031] This disclosure provides a method for manufacturing a semiconductor structure, wherein a first sidewall is formed on a sidewall opposite to a portion of a first structure along a first direction, the first structure and the first sidewall located on the sidewall of the first structure constitute a first mask, the width of the first structure along the first direction is smaller than the width of a portion of a second structure, the provision of the first sidewall can reduce the width difference between the portion of the first structure and the portion of the second structure along the first direction, and a first patterned layer with a first opening is formed as a mask, the first opening being at least directly opposite a portion of the portion of the second structure adjacent to the first structure, the portion of the second structure adjacent to the first structure is removed by etching along the first opening, thereby reducing the width of the portion of the second structure with a larger width along the first direction, thereby further reducing the width difference between the portion of the first structure and the portion of the second structure, wherein the first patterned layer is located on the first sidewall, the first structure, the substrate and the second structure, so as to protect the semiconductor structure located below the first patterned layer that is not expected to be etched during the etching process. Thus, based on the original first and second structures, this embodiment forms a first mask and a second mask with smaller width differences and larger spacing, reducing the phenomenon that the width difference between a portion of the original first structure and a portion of the second structure affects the subsequent processes of the semiconductor structure, which is beneficial to improving the performance and yield of the formed semiconductor structure.
[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0033] Figures 7 to 13 This is a schematic diagram of the steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
[0034] refer to Figure 7A substrate 201 is provided, on which a first patterned layer 202 is formed. The first patterned layer 202 includes a plurality of first structures 203 and a plurality of second structures 204 arranged alternately at intervals, and along a first direction (e.g., Figure 7 In the X direction (as shown), at least a portion of the width of the first structure 203 is smaller than the width of a portion of the second structure 204.
[0035] It is understood that the first patterned layer 202 can be formed using a self-aligned double patterning technique. During the formation of the first patterned layer 202 using this technique, multiple first structures 203 and multiple second structures 204 are formed in different steps. Due to fluctuations in data from the relevant equipment and measurement feedback, along the first direction, there may be instances where the width of at least some of the first structures 203 differs from the width of some of the second structures 204, or where the width of some of the first structures 203 is equal to the width of some of the second structures 204. Specifically, the first structures 203 can be formed in steps before or after the formation of the second structures 204.
[0036] In some embodiments, the material of the substrate 201 can be any of the common semiconductor substrate materials such as silicon, germanium, silicon-germanium, and silicon carbide. In other embodiments, the substrate 201 can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), etc.
[0037] The material of the first structure 203 can be any one or more of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride. The material of the second structure 203 can be any one or more of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.
[0038] In some embodiments, the materials of the first structure 203 and the second structure 204 may be the same; for example, the material of the first structure 203 may be silicon oxide, and the material of the second structure 204 may also be silicon oxide. In other embodiments, the materials of the first structure 203 and the second structure 204 may also be different; for example, the material of the first structure 203 may be silicon oxide, and the material of the second structure 204 may be silicon nitride.
[0039] In some embodiments, along the first direction, the width of a portion of the first structure 203 and the width of a portion of the second structure 204 may be equal. The width range of both the portion of the first structure 203 and the portion of the second structure 204 may be 33.1 nm to 34.1 nm. For example, the width of the first structure 203 may be 33.5 nm, and the width of the second structure 204 may be 33.5 nm. Alternatively, the width of the first structure 203 may be 33.8 nm, and the width of the second structure 204 may be 33.8 nm. Yet another example is that the width of both the first structure and the second structure 204 may be 34 nm.
[0040] A first pad 205 may also be formed on the surface of the substrate 201 facing the first patterned layer 202. The first pad 205 can serve as a mask to protect the substrate 201 from corrosion. The material of the first pad 205 may include A-Si (amorphous silicon), and the material of the first pad 205 may also include any one or more of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.
[0041] Subsequent steps may further include: forming a first sidewall, the first sidewall being located at least on the opposite sidewall of a portion of the first structure 203 along a first direction, the first structure 203 and the first sidewall located on the sidewall of the first structure 203 constituting a first mask. It is understood that, among all the first structures 203, the width of the first structure 203 in the first mask is smaller than the width of the other first structures 203 along the first direction, in order to reduce the width difference between the plurality of first structures 203.
[0042] Before forming the first sidewall, the process may further include cleaning the substrate 201 and the first patterned layer 202 to remove impurities, dust, etc., remaining on the semiconductor structure after the first patterned layer 202 is formed using a self-aligned dual patterning technique.
[0043] refer to Figure 8 After cleaning the substrate 201 and the first patterned layer 202, before forming the first sidewall, the process may further include: forming a second patterned layer 208, which covers the first structure 203, the second structure 204, and the substrate 201, to protect the portion of the semiconductor structure covered by the second patterned layer 208 from process influence during the subsequent step of forming the first sidewall. The second patterned layer 208 may also have a second opening 209 penetrating the second patterned layer 208, which exposes at least a portion of the first structure 203 and also exposes a portion of the substrate 201 adjacent to the first structure 203, so that during the step of forming the first sidewall, a portion of the first sidewall may be formed on the sidewall of a portion of the first structure 203, and the portion of the first structure 203 and the first sidewall of its sidewall constitute a first mask.
[0044] The second patterning layer 208 may include a first mask layer 210 and a second mask layer 211. The second mask layer 211 is formed between the first mask layer 210 and the first patterning layer 202. A second opening 209 penetrates the first mask layer 210 and the second mask layer 211. The first mask layer 210 covers the second mask layer 211. The second mask layer 211 covers the first structure 203, the second structure 204 and the substrate 201. The first mask layer 210 may cover a portion of the second mask layer 211. This portion of the second mask layer 211 may at least cover the second structure 204.
[0045] The material of the first mask layer 210 can be photoresist, so as to protect the portion of the second mask layer 211 covered by the photoresist and the second structure 204 located opposite the portion of the second mask layer 211 from erosion and to perform a masking function.
[0046] The material of the second mask layer 211 can be a bottom anti-reflection coating (BARC). During the process of forming the first mask layer 210 using photoresist, the bottom anti-reflection coating can reduce the reflected light generated during the formation of the first mask layer 210 and play a masking role.
[0047] The step of forming the first patterned layer 202 may include: forming a second initial mask layer, the second initial mask layer covering the first patterned layer 202 and the substrate 201; forming a first mask layer 210 on the second initial mask layer, the first mask layer 210 having an opening that exposes a portion of the second initial mask layer, the portion of the second initial mask layer exposing at least the first structure 203; using the first mask layer 210 as a mask, etching away the portion of the second initial mask layer not covered by the first mask layer 210 along the opening, the remaining second initial mask layer constituting the second mask layer 211, and the opening and the area of the removed portion of the second initial mask layer constituting the second opening 209.
[0048] In some embodiments, the first mask layer 210 may cover a portion of the second initial mask layer, which may cover the second structure 204 and a portion of the substrate 201 adjacent to the second structure 204, to protect the sidewalls of the second structure 204 from erosion during the etching process of removing a portion of the second initial mask layer along the second opening 209, and in the subsequent step of forming the first sidewall 206, a portion of the first sidewall 206 may be located on the second mask layer 211 on the sidewall of the second structure 204.
[0049] In other embodiments, the first mask layer 210 may also cover a portion of the second initial mask layer, the opening of which exposes the location of the portion of the second initial mask layer. This portion of the second initial mask layer may cover the second structure 204, so that in the subsequent step of forming the first sidewall 206, a portion of the first sidewall 206 may be located on the sidewall of the second structure 204 opposite to it in the first direction.
[0050] It is understandable that the second pattern layer 208 may also not have a second mask layer 211, that is, the second pattern layer 208 is the first mask layer 210.
[0051] It is also understandable that, in the subsequent process steps of forming the first sidewall 206, the first sidewall 206 can also be formed on the sidewall of the second pattern layer 208. This is to reduce the formation of the first mask 207 (refer to...) along the first direction. Figure 10 The width difference between the first structure 203 and the second structure 204 with larger widths may further include the steps of: removing the first sidewall 206 located on a portion of the sidewall of the first structure 203, removing the first sidewall located on the sidewall of the second graphic layer 208, and removing the second graphic layer 208 after the first sidewall 206 is formed.
[0052] refer to Figure 9 and Figure 10 This forms a first sidewall 206, which is located at least in a portion of the first structure 203 along a first direction (e.g., Figure 9 On the opposite sidewalls (shown in the X direction), the first structure 203 and the first sidewall 206 located on the sidewall of the first structure 203 constitute the first mask 207.
[0053] In some embodiments, the process steps of forming the first sidewall 206 may include: forming the first sidewall 206 on the top surface and sidewall of the first structure 203, the top surface and sidewall of the second pattern layer 208 and the substrate 201, wherein, among the plurality of first structures 203, the first structure 203 with a relatively small width along the first direction and the first sidewall 206 located on the sidewall of the first structure 203 constitute a first mask 207.
[0054] In some embodiments, the process of forming the first sidewall 206 may include atomic vapor deposition, chemical vapor deposition or physical vapor deposition, etc., wherein the width of the first sidewall 206 in the first mask formed along the first direction may be in the range of 4.5nm to 5.5nm, for example, it may be 4.5nm, 5nm or 5.5nm.
[0055] The material of the first sidewall 206 can be any one or more of silicon oxide, silicon nitride, or silicon oxynitride.
[0056] In some embodiments, the material of the first sidewall 206 may be the same as the material of the first structure 203. For example, the material of the first structure 203 may be silicon oxide, and correspondingly, the material of the first sidewall 206 may be silicon oxide. As another example, the material of the first structure 203 may be silicon nitride, and correspondingly, the material of the first sidewall 206 may be silicon nitride.
[0057] In some embodiments, the material of the first sidewall 206 may be different from the material of the second structure 204. For example, the material of the second structure 204 may be silicon oxide, and the material of the first sidewall 206 may be silicon nitride. As another example, the material of the second structure 204 may be silicon nitride, and the material of the first sidewall 206 may be silicon oxide.
[0058] In other embodiments, the material of the first sidewall 206 may be the same as the material of the second structure 204. For example, the material of the second structure 204 may be silicon oxide, and correspondingly, the material of the first sidewall 206 may be silicon oxide. As another example, the material of the second structure 204 may be silicon nitride, and correspondingly, the material of the first sidewall 206 may be silicon nitride.
[0059] It is understandable that the materials of the first side wall 206, the first structure 203, and the second structure 204 can all be the same, and the materials of the first side wall 206 and the first structure 203 can also be different from the materials of the second structure 204.
[0060] In some embodiments, the second pattern layer 208 may include a first mask layer 210 and a second mask layer 211. The step of forming the first sidewall 206 may include: removing the first mask layer 210 to form the first sidewall 206, the first sidewall 206 being located on the substrate 201, the top surface and sidewall of the first structure 203, and the top surface and sidewall of the second mask layer 211.
[0061] It is also understandable that, in order to reduce the width difference between the first structure 203 and the second structure 204 along the first direction, subsequent steps require removing the first sidewall 206 located on the sidewall of the first structure 203 and the second structure 204, which have a larger width, along the first direction. Specifically, after forming the first sidewall 206, the first sidewall 206 located on the top surface of the first structure 203, the top surface of the second graphic layer 208, and part of the base 201 can also be removed, while retaining the first sidewall 206 located on the sidewall of the first structure 203 and the sidewall of the second graphic layer 208.
[0062] refer to Figure 11The step of removing the first sidewall 206 located on the sidewall of the second graphic layer 208 may include: removing the second graphic layer 208, retaining the first sidewall 206 located on the sidewall of the second graphic layer 208 as the target sidewall; forming a third graphic layer 212, the third graphic layer 212 being located on the first structure 203, the first sidewall 204 and the base 201, the third graphic layer 212 having a third opening 213 penetrating the third graphic layer 212, and the third opening 213 being directly opposite the target sidewall.
[0063] In some embodiments, a third mask layer 214 may be formed between the third pattern layer 212 and the first pattern layer 202, the third mask layer 214 covering the first pattern layer 202, the target sidewall and the substrate 201.
[0064] It is understandable that before forming the third pattern layer 212, only a portion of the second pattern layer 208 can be removed, which is the first mask layer 210, while retaining the second mask layer 211. Mask material can be deposited on the second mask layer 211, and the second mask layer 211 and the deposited mask material together constitute the third mask layer 214. In this way, the process cost can be reduced.
[0065] The material of the third patterning layer 212 may include photoresist to protect the portion of the third mask layer 214 covered by the photoresist, the first patterned layer 202 located below the third mask layer 212, and the substrate 201 from erosion, and to serve as a mask.
[0066] The material of the third mask layer 214 can be a bottom anti-reflection coating (BARC). During the process of forming the third pattern layer 212 using photoresist, the bottom anti-reflection coating can reduce the reflected light generated during the formation of the third pattern layer 212 and act as a mask.
[0067] The third opening 213 can also be located directly opposite the first sidewall 206 of the sidewall of the first structure 203. In the first direction, the width of the first structure 203 is greater than the width of the first structure 203 in the first mask 207. In order to reduce the width difference of multiple first structures 203, the subsequent step of removing the target sidewall along the third opening 213 using the third pattern layer as a mask can also include: removing the first sidewall 206 of the sidewall of the first structure 203 with a larger width along the third opening 213.
[0068] The method of removing the first sidewall 206 located on the sidewall of the second pattern layer 208 may further include: using the third pattern layer 212 as a mask, removing the target sidewall along the third opening 213, that is, the first sidewall 206 located on the sidewall of the second pattern layer 208 on the second structure 204 along the third opening 213, wherein, after removing the target sidewall, the remaining first sidewall 206 located on the sidewall of the first structure 203 with a smaller width and the first structure 203 together constitute the first mask 207.
[0069] Along the first direction (e.g.) Figure 11 (As shown in the X direction), the width of the first mask 207 can be in the range of 33.1nm to 34.1nm, for example, the width can be 33.5nm, 33.8nm or 34nm.
[0070] Understandably, subsequent steps may also include forming a first patterned layer with a first opening, and using the first patterned layer as a mask to remove at least a portion of the second structure 204 region along the first opening to reduce the width of the second structure 204, which is larger than the first mask 207, along the first direction, and the second structure 204 partially constitutes the second mask.
[0071] In some embodiments, the removal of the third graphic layer 212 may be included before forming the first graphic layer in a subsequent step along the first direction.
[0072] In other embodiments, the method of removing the first sidewall 206 located on the sidewall of the second pattern layer 208 may further include: removing the second pattern layer 208 and retaining the first sidewall 206 located on the sidewall of the second pattern layer 208 as the target sidewall; in the subsequent process step of forming the first pattern layer, the first opening is also directly opposite the target sidewall, so that in the process step of removing a portion of the second structure 204 adjacent to the first structure 203 along the first opening using the first pattern layer as a mask, the target sidewall is also removed, that is, the target sidewall and the reduction of the width of the second structure 204 along the first direction are carried out in the same process, thus the process steps are relatively simple.
[0073] refer to Figure 12 A first graphic layer 215 is formed, which is located on the first sidewall 206, the first structure 203, the base 201 and the second structure 204. The first graphic layer 215 also has a first opening 216 that penetrates the first graphic layer 215. The first opening 216 is at least directly opposite a portion of the second structure 204 that is adjacent to the first structure 203.
[0074] In some embodiments, a fourth mask layer 217 may be formed between the first pattern layer 215 and the first mask 207, the second structure 204 and the substrate 201, with the first opening 216 exposing a portion of the fourth mask layer 217.
[0075] The material of the first pattern layer 215 can be photoresist to protect the portion of the fourth mask layer 217 covered by the photoresist, the portion of the second structure 204 located below the portion of the fourth mask layer 217, the first mask 207, and the substrate 201 from erosion.
[0076] The material of the fourth mask layer 217 can be a bottom anti-reflective coating. During the process of forming the first pattern layer 215 using photoresist, the bottom anti-reflective coating can reduce the reflected light generated during the formation of the first pattern layer 215 and act as a mask.
[0077] refer to Figure 13 Using the first pattern layer 215 as a mask, at least a portion of the second structure 204 adjacent to the first structure 203 is removed along the first opening 216, and the remaining portion of the second structure 204 constitutes the second mask 218.
[0078] Along the first direction (e.g.) Figure 13 The width of the second mask 218 (shown in the X direction) can be in the range of 33.1 nm to 34.1 nm, for example, the width can be 33.5 nm, 33.8 nm or 34 nm.
[0079] Along the first direction, the width of the second mask 218 can be the same as the width of the first mask 207 formed in the aforementioned steps. For example, the width of the first mask 207 can be 33.5 nm, and the width of the second mask 218 can be 33.5 nm.
[0080] It is understood that in the provided first patterned layer, along the first direction, the width of a portion of the first structure 203 is equal to the width of a portion of the second structure 204. In the aforementioned steps, the width of the first mask 207 and the width of the second mask 218 formed are equal to the width of the portion of the first structure 203 and the second structure 204. For example, the width of the first structure 203 can be 33.5 nm, the width of the second structure 204 can be 33.5 nm, the width of the first mask 207 can be 33.5 nm, and the width of the second mask 218 can be 33.5 nm.
[0081] In some embodiments, after forming the first mask 207 and the second mask 218, the method may further include: removing the first pattern layer 215; and using the first mask 207 and the second mask 218 as masks, removing the portion of the first pad layer 205 that is not covered by the first mask 207 and the second mask 218.
[0082] refer to Figures 14 to 17 , Figures 14 to 17 This is a schematic diagram of the steps in a method for manufacturing another semiconductor structure according to an embodiment of the present disclosure.
[0083] refer to Figure 14 A substrate 201 is provided, on which a first patterned layer 202 is formed. The first patterned layer 202 includes a plurality of first structures 203 and a plurality of second structures 204 arranged alternately at intervals, and along a first direction (e.g. Figure 14 (in the X direction shown), at least part of the width of the first structure 203 is smaller than the width of part of the second structure 204.
[0084] A first pad 205 may also be formed on the surface of the substrate 201 facing the first patterned layer 202. The first pad 205 can serve as a mask to prevent the substrate 201 from being partially removed in subsequent steps. The material of the first pad 205 may include A-Si (amorphous silicon), and the material of the first pad 205 may also be any one or more of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.
[0085] In some embodiments, the material of the first structure 203 and the material of the second structure 204 may be the same, and the material of the first structure 203 may be any one or more of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride. In other embodiments, the materials of the first structure 203 and the second structure 204 may be different.
[0086] In some embodiments, along the first direction, the width of a portion of the first structure 203 and the width of a portion of the second structure 204 may be equal. Both the width of the portion of the first structure 203 and the width of the portion of the second structure 204 may be 33.1 nm to 34.1 nm. For example, the width of the first structure 203 may be 33.5 nm, and the width of the second structure 204 may be 33.5 nm. Alternatively, the width of the first structure 203 may be 33.8 nm, and the width of the second structure 204 may be 33.8 nm. Yet another example is that both the width of the first structure and the width of the second structure 204 may be 34 nm.
[0087] Subsequent steps may further include: forming a first sidewall, the first sidewall being located at least on the opposite sidewall of a portion of the first structure 203 along a first direction, the first structure 203 and the first sidewall located on the sidewall of the first structure 203 constituting a first mask, wherein the difference between the width of the first mask and the width of the second structure 204 is reduced along the first direction.
[0088] refer to Figure 15A first sidewall 206 is formed, which can cover the top surface and sidewall of the first structure 203, the top surface and sidewall of the second structure 204, and also cover the surface of the substrate 201 between the first structure 203 and the second structure 204. That is, the first sidewall 206 is directly deposited on the provided first patterned layer 202 and the substrate 201. The first sidewall 206 located on the sidewall of the first structure 203 opposite to each other in the first direction constitutes the first mask 207 with the first structure 203.
[0089] Along the first direction, the width of the first mask 207 can range from 33.1 nm to 34.1 nm; for example, the width can be 33.5 nm, 33.8 nm, or 34 nm. Along the first direction (e.g....) Figure 15 (As shown in the X direction), the width of the first sidewall 206 in the first mask 207 can be in the range of 4.5nm to 5.5nm, for example, it can be 4.5nm, 5nm or 5.5nm.
[0090] The material of the first sidewall 206 can be any one or more of silicon oxide, silicon nitride, or silicon oxynitride.
[0091] In some embodiments, the material of the first sidewall 206 may be the same as the material of the first structure 203. For example, the material of the first structure 203 may be silicon oxide, and correspondingly, the material of the first sidewall 206 may be silicon oxide. As another example, the material of the first structure 203 may be silicon nitride, and correspondingly, the material of the first sidewall 206 may be silicon nitride.
[0092] In some embodiments, the material of the first sidewall 206 may be different from the material of the second structure 204. For example, the material of the second structure may be silicon oxide, and the material of the first sidewall 206 may be silicon nitride. As another example, the material of the second structure 204 may be silicon nitride, and the material of the first sidewall 206 may be silicon oxide.
[0093] In some embodiments, the material of the first sidewall 206 can be the same as the material of the second structure 204. For example, the material of the second structure 204 can be silicon oxide, and correspondingly, the material of the first sidewall 206 can be silicon oxide. As another example, the material of the second structure 204 can be silicon nitride, and correspondingly, the material of the first sidewall 206 can be silicon nitride. Compared to the previous embodiments where the first sidewall 206 was formed with a material different from that of the second structure 204, the process of removing the first sidewall 206 and a portion of the second structure 204 located on the sidewall of the second structure 204 in the subsequent step of simultaneously removing a portion of the second structure 204 and the first sidewall 206 is relatively less difficult and has a smaller process error in this embodiment.
[0094] In some embodiments, the process of forming the first sidewall 206 may include atomic vapor deposition, chemical vapor deposition or physical vapor deposition, etc. Along the first direction, the width of the first sidewall 206 in the first mask 207 may be in the range of 4.5nm to 5.5nm, for example, it may be 4.5nm, 5nm or 5.5nm.
[0095] Subsequent steps may further include: forming a first pattern layer, wherein, before forming the first pattern layer, the steps may further include removing a first sidewall 206 located on the top surface of the first structure 203, a portion of the sidewall of the first structure 203, and a portion of the first sidewall 206 on the top surface of the second structure 204, and also removing a first sidewall 206 located on the base 201 between the first structure 203 and the second structure 204. Along the first direction, the width of the first structure 203 to which the first sidewall 206 has been removed is equal to the width of the first mask 207.
[0096] refer to Figure 16 A first graphic layer 215 is formed, which is located on the first sidewall 206, the first structure 203, the base 201, and the second structure 204. The first graphic layer 215 also has a first opening 216 penetrating the first graphic layer 215. The first opening 216 is directly opposite a portion of the second structure 204 adjacent to the first structure 204. Specifically, along the first direction (e.g.) Figure 16 (As shown in the X direction), the first structure 203 with a smaller width and the first sidewall 206 of its sidewall constitute the first mask 207.
[0097] In the process of forming the first pattern layer 215, the first opening 216 can also be directly opposite the first sidewall 206 located on the side wall of the second structure 204. Thus, in the process of removing at least a portion of the area of the second structure 204 adjacent to the first structure 203 along the first opening 216, the first sidewall 206 located on the side wall of the second structure 204 can also be removed simultaneously. In this way, the process is relatively simple.
[0098] A fourth mask layer 217 may also be formed between the first pattern layer 215, the first mask 207, the second structure 204, and the substrate 201, with the first opening 216 exposing a portion of the fourth mask layer 217.
[0099] The material of the first pattern layer 215 can be photoresist to protect the portion of the fourth mask layer 217 covered by the photoresist, the portion of the second structure 204 located below the portion of the fourth mask layer 217, the first mask 207, and the substrate 201 from erosion.
[0100] The material of the fourth mask layer 217 can be a bottom anti-reflective coating. During the process of forming the first pattern layer 215 using photoresist, the bottom anti-reflective coating can reduce the reflected light generated during the formation of the first pattern layer 215 and act as a mask.
[0101] refer to Figure 17 Using the first pattern layer 215 as a mask, a portion of the second structure 204 adjacent to the first structure 203 is removed along the first opening 216, and the first sidewall 206 located on the sidewall of the second structure 204 is also removed. The remaining portion of the second structure 204 constitutes the second mask 218. In this way, the difference between the formed second mask 218 and the first mask 207 along the first direction (e.g., ...) can be reduced. Figure 17 The width difference in the X direction (as shown) avoids the impact of the width difference between the first mask 207 and the second mask 218 on subsequent processes of the semiconductor structure, which is beneficial to improving the yield and reliability of the formed semiconductor structure.
[0102] It is understandable that, since the width of a portion of the first structure 203 formed using the self-aligned dual patterning technique is equal to the width of the first mask 207 along the first direction, it is necessary to remove the first sidewall 206 located on the sidewall of that portion of the first structure 203.
[0103] In some embodiments, the first pattern layer 215 may have a fourth opening (not shown) penetrating the first pattern layer 215, the fourth opening being directly opposite a first sidewall 206 on the sidewall opposite the portion of the first structure 203. In the first direction, the width of the portion of the first structure 203 is equal to the width of the first mask 207. The step of removing a portion of the second structure 204 adjacent to the first structure 203 along the first opening 216 using the first pattern layer 215 as a mask may further include: removing the first sidewall 206 on the sidewall of the portion of the first structure 203 along the fourth opening.
[0104] It is also understandable that, since the portion of the first sidewall 206 located on the top surface of the second structure 204 is covered by the fourth mask layer 217 and thus cannot be removed in this step during the step of removing the portion of the second structure 204 adjacent to the first structure 203 and the target sidewall along the first opening 216, the step may include: removing the portion of the first sidewall 206 located on the top surface of the second structure 204 along the first opening 216.
[0105] In some embodiments, the width of the first mask 207 formed along the first direction can be equal to the width of the second mask 218. This reduces the possibility that the width difference between the first mask 207 and the second mask 218 along the first direction will affect the subsequent processes of the semiconductor structure, which is beneficial to improving the yield and reliability of the formed semiconductor structure.
[0106] The width of the second mask 218 along the first direction can be in the range of 33.1 nm to 34.1 nm, for example, the width can be 33.5 nm, 33.8 nm or 34 nm.
[0107] Along the first direction, the width of the second mask 218 can be the same as the width of the first mask 207 formed in the aforementioned steps. For example, the width of the first mask 207 can be 33.5 nm, and the width of the second mask 218 can also be 33.5 nm.
[0108] It is understood that in the provided first patterning layer 202, along the first direction, the width of a portion of the first structure 203 is equal to the width of a portion of the second structure 204. In the aforementioned steps, the width of the first mask 207 and the width of the second mask 218 are equal to the width of the portion of the first structure 203 and the second structure 204. For example, the width of the first structure 203 can be 33.5 nm, the width of the second structure 204 can be 33.5 nm, the width of the first mask 207 can be 33.5 nm, and the width of the second mask 218 can be 33.5 nm.
[0109] In some embodiments, after forming the first mask 207 and the second mask 218, the method may further include: removing the first pattern layer 215; and using the first mask 207 and the second mask 218 as masks, removing the portion of the first pad layer 205 that is not covered by the first mask 207 and the second mask 218.
[0110] The semiconductor structure manufacturing method provided in this disclosure includes a plurality of first structures 203 and a plurality of second structures 204 formed on a substrate 201. In a first direction, the width of a portion of the first structures 203 is smaller than the width of a portion of the second structures 204. A first sidewall 206 is formed on the sidewall of the first structure 203 with the smaller width in the first direction. The first structures 203 and the first sidewall 206 constitute a first mask 207. The width difference between the first mask 207 and the second structures 204 is relatively small, which reduces the width difference between the first structures 203 and the second structures 204. After forming the first mask 207, a first patterned layer 2 with a first opening 216 is formed. 15. Using the first pattern layer 215 as a mask, a portion of the relatively wide second structure 204 is removed along the first opening 216. The remaining portion of the second structure 204 constitutes the second mask 218. The width of the second mask 218 can be equal to the width of the first mask 207, and the width of the second mask 218 can also be equal to the width of the unprocessed portion of the second structure 204 and the width of the first structure 203 without the first sidewall 206. In this way, the possibility of the difference between the width of the first structure 203 and the width of the second structure 204 affecting the normal process of the subsequent semiconductor structure can be reduced, thereby improving the yield and reliability of the formed semiconductor structure.
[0111] Accordingly, another embodiment of this disclosure also provides a semiconductor structure, which is manufactured by the manufacturing method of the semiconductor structure provided in the foregoing embodiment. The semiconductor structure provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions in the foregoing embodiments; detailed descriptions will not be repeated below. Figure 18 This is a schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure.
[0112] refer to Figure 18 The semiconductor structure may include: a substrate 201; a plurality of first masks 207 located on the substrate 201; and a plurality of second masks 218 located on the substrate 201, at least a portion of the second masks 218 including a first structure 203 and a first sidewall 206, the first sidewall 206 being located along a first direction (e.g., ...). Figure 18 On the opposite sidewalls (shown in the X direction); wherein, a plurality of first masks 207 and a plurality of second masks 218 are arranged alternately at intervals along the first direction on the substrate 201, and along the first direction, the width of the first mask 207 is equal to the width of the second mask 218.
[0113] The material of the first mask 207 can be any one or more of silicon oxide, silicon nitride, or silicon oxynitride. The material of the second mask 218 can be any one or more of silicon oxide, silicon nitride, or silicon oxynitride. The material of the first sidewall 206 can be any one or more of silicon oxide, silicon nitride, or silicon oxynitride.
[0114] In some embodiments, the material of the first sidewall 206 may be the same as the material of the first structure 203. For example, the material of the first structure 203 may be silicon oxide, and correspondingly, the material of the first sidewall 206 may be silicon oxide. As another example, the material of the first structure 203 may be silicon nitride, and correspondingly, the material of the first sidewall 206 may be silicon nitride.
[0115] In some embodiments, the material of the first sidewall 206 may be the same as the material of the second mask 218. For example, the material of the second mask 218 may be silicon oxide, and the material of the first sidewall 206 may also be silicon oxide. Alternatively, the material of the second mask 218 may be silicon nitride, and the material of the first sidewall 206 may also be silicon nitride. In some embodiments, the material of the first sidewall 206 may also be different from the material of the second mask 218. For example, the material of the second mask 218 may be silicon oxide, and the material of the first sidewall 206 may also be silicon nitride. Alternatively, the material of the second mask 218 may be silicon nitride, and the material of the first sidewall 206 may be silicon oxide.
[0116] In some embodiments, the material of the first mask 207 may be the same as the material of the second mask 218. For example, the material of the first mask 207 may be silicon oxide, and the material of the second mask 218 may also be silicon oxide. In other embodiments, the material of the first mask 207 may be different from the material of the second mask 218. For example, the material of the first mask 207 may be silicon oxide, and the material of the second mask 218 may be silicon nitride.
[0117] In some embodiments, a portion of the first mask 207 may also be a first structure 203, the width of which is greater than the width of the first structure 203 having a first sidewall 206 on its sidewall along the first direction.
[0118] A first pad 205 may be disposed between the substrate 201 and both the first mask 207 and the second mask 218. The first pad 205 includes a portion of the first pad 205 located directly opposite the first mask 207 and a portion of the first pad 205 located directly opposite the second mask 218. The material of the first pad 205 may include A-Si (amorphous silicon), and the material of the first pad 205 may also include any one or more of silicon oxide, silicon nitride, or silicon oxynitride.
[0119] This disclosure provides a semiconductor structure in which a plurality of first masks 207 and second masks 218 are disposed on a substrate 201. The first masks 207 and second masks 218 are manufactured by the semiconductor structure manufacturing method provided in the foregoing embodiments. In the first direction, the width of the first mask 207 is equal to the width of the second mask 218. This can reduce the phenomenon that subsequent manufacturing problems may occur due to the width difference between the first mask 207 and the second mask 218 and the small spacing between adjacent first masks 207 and second masks 218, which is beneficial to improving the yield and reliability of the semiconductor structure.
[0120] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided on which a first patterned layer is formed. The first patterned layer includes a plurality of first structures and a plurality of second structures arranged alternately at intervals, and along a first direction, at least a portion of the width of the first structures is smaller than the width of a portion of the second structures. A first sidewall is formed, the first sidewall being located at least on the opposite sidewall of a portion of the first structure along the first direction. The first structure and the first sidewall located on the sidewall of the first structure constitute a first mask; A first graphic layer is formed, which is located on the first sidewall, the first structure, the base and the second structure, and the first graphic layer also has a first opening that penetrates the first graphic layer, and the first opening is at least directly opposite a portion of the second structure adjacent to the first structure. Using the first patterned layer as a mask, at least a portion of the second structure adjacent to the first structure is removed along the first opening, and the remaining portion of the second structure constitutes the second mask. Remove the first graphics layer.
2. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, Before the formation of the first sidewall, the following is also included: A second pattern layer is formed, which covers the first structure, the second structure, and the substrate. The second pattern layer has a second opening that penetrates the second pattern layer, and the second opening exposes at least a portion of the first structure and also exposes a portion of the substrate adjacent to the first structure. In the process of forming the first sidewall, the first sidewall is also formed on the sidewall of the second pattern layer; The manufacturing method further includes: removing the first sidewall located on a portion of the first structure sidewall; removing the first sidewall located on the second pattern layer sidewall; and removing the second pattern layer.
3. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, The process steps for forming the first sidewall include: The first sidewall is formed on the top and sidewalls of the first structure, the top and sidewalls of the second graphic layer, and the base. Remove the first sidewall located on the top surface of the first structure, the top surface of the second graphic layer, and part of the base, while retaining the first sidewall located on the sidewall of the first structure and the sidewall of the second graphic layer.
4. The method for manufacturing a semiconductor structure as described in claim 3, characterized in that, The step of removing the first sidewall located on the sidewall of the second graphic layer includes: Remove the second graphic layer, and retain the first sidewall located on the sidewall of the second graphic layer as the target sidewall; A third graphic layer is formed, which is located on the first structure, the first sidewall, and the base. The third graphic layer has a third opening that penetrates the third graphic layer and is directly opposite the target sidewall. Using the third graphic layer as a mask, the target sidewall is removed along the third opening; Remove the third graphics layer.
5. The method for manufacturing a semiconductor structure as described in claim 3, characterized in that, A method for removing the first sidewall located on the sidewall of the second graphic layer includes: Remove the second pattern layer, and retain the first sidewall located on the side wall of the second pattern layer as the target sidewall; in the process step of forming the first pattern layer, the first opening is also directly opposite the target sidewall. In the process of removing a portion of the second structure adjacent to the first structure along the first opening using the first pattern layer as a mask, the target sidewall is also removed.
6. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The steps for forming the first sidewall include: A first sidewall is formed, which covers the top surface and sidewall of the first structure, and the top surface and sidewall of the second structure. It also covers the substrate surface between the first structure and the second structure; In the process of forming the first patterned layer, the first opening is also directly opposite the first sidewall located on the sidewall of the second structure; The process step of removing at least a portion of the second structure adjacent to the first structure along the first opening further includes: removing the first sidewall located on the sidewall of the second structure.
7. The method for manufacturing a semiconductor structure as described in claim 6, characterized in that, Before forming the first pattern layer, the method further includes: removing the first sidewall located on the top surface of the first structure, a portion of the sidewall of the first structure, and a portion of the first sidewall on the top surface of the second structure, and also removing the first sidewall on the substrate located between the first structure and the second structure.
8. The method for manufacturing a semiconductor structure as described in claim 6, characterized in that, Before removing at least a portion of the second structure adjacent to the first structure along the first opening, the method further includes: removing a portion of the first sidewall located on the top surface of the second structure along the first opening.
9. The method for manufacturing a semiconductor structure as described in claim 6, characterized in that, The material of the first sidewall is different from the material of the second structure.
10. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The material of the first sidewall is the same as the material of the first structure.
11. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The material of the first structure is the same as that of the second structure.
12. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, Along the first direction, the width of the first mask is the same as the width of the second mask.
13. A semiconductor structure, said semiconductor structure being formed by a method for manufacturing a semiconductor structure according to any one of claims 1-12, comprising: Base; Multiple first masks, the first masks being located on the substrate; Multiple second masks are located on the substrate, and at least a portion of the second masks include a first structure and a first sidewall, the first sidewall being located on the sidewall of the first structure opposite to it along a first direction; In this arrangement, a plurality of first masks and a plurality of second masks are alternately arranged on the substrate along the first direction, and the width of the first mask is equal to the width of the second mask along the first direction.
14. The semiconductor structure as described in claim 13, characterized in that, The material of the first sidewall is the same as the material of the first structure, and the material of the first sidewall may be the same as or different from the material of the second mask.
15. The semiconductor structure as described in claim 13, characterized in that, The material of the first mask is the same as the material of the second mask.