Packaging structure and packaging method

Abstract

Embodiments of the present application relate to the field of semiconductor packaging and provide a packaging structure and a packaging method. A packaging structure includes: a first metal layer and a second metal layer, the first metal layer is located on the first side of the circuit area, and the second metal layer is located on the first side of the support area; a third metal layer and a fourth metal layer, the third metal layer is located on the second side of the circuit area and electrically connected to the conductive structure, and the fourth metal layer is located on the second side of the support area; wherein the first side of one semiconductor structure of at least two stacked semiconductor structures is opposite to the second side of another adjacent semiconductor structure, and the first metal layer of the semiconductor structure is in contact and bonded with the third metal layer of the semiconductor structure in the adjacent layer, and the second metal layer of the semiconductor structure is in contact and bonded with the fourth metal layer of the semiconductor structure in the adjacent layer, which can solve the thermal problem in the integrated circuit.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit packaging, and in particular to a packaging structure and a packaging method. Background Art

[0002] Integrated circuit packaging is a crucial production process in the field of integrated circuit technology. Recent advances in computer and communications technologies have placed higher demands on integrated circuit packaging technology, requiring it to be smaller, thinner, lighter, more reliable, multifunctional, low power, and low-cost. With two-dimensional assembly density already reaching its theoretical maximum, higher-density three-dimensional stacking packaging technology (3D packaging) is beginning to develop.

[0003] 3D packaging is an advanced multi-chip module (MCM) technology developed based on 2D-MCM. It integrates IC chips in three dimensions (x, y, and z directions). Conventional 3D packaging involves vertically stacking two or more chips within the same package without changing the package dimensions. Summary of the Invention

[0004] The embodiments of the present application provide a packaging structure and a packaging method, which are at least helpful in solving the thermal problems of integrated circuits.

[0005] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a packaging structure, comprising: at least two stacked semiconductor structures, each of the semiconductor structures comprising a first surface and a second surface relative to each other, and the semiconductor structure comprising a circuit area and a support area, the semiconductor structure in the circuit area having a conductive structure; the semiconductor structure further comprising: a first metal layer and a second metal layer, the first metal layer being located on the first surface of the circuit area, and the second metal layer being located on the first surface of the support area; a third metal layer and a fourth metal layer, the third metal layer being located on the second surface of the circuit area and electrically connected to the conductive structure, and the fourth metal layer being located on the second surface of the support area; wherein the first surface of one of the at least two stacked semiconductor structures is opposite to the second surface of another adjacent semiconductor structure, and the first metal layer of the semiconductor structure is in contact and bonded to the third metal layer of the semiconductor structure in the adjacent layer, and the second metal layer of the semiconductor structure is in contact and bonded to the fourth metal layer of the semiconductor structure in the adjacent layer.

[0006] In some embodiments, the second metal layer located in the support area is a continuous film layer on the entire surface; and the fourth metal layer located in the support area is a continuous film layer on the entire surface.

[0007] In some embodiments, the semiconductor structure includes a plurality of first metal layers arranged at intervals, and in the arrangement direction along the support area and the circuit area, the ratio of the spacing between adjacent first metal layers to the width of the first metal layer ranges from 1 / 12 to 3 / 4.

[0008] In some embodiments, along the arrangement direction of the support area and the circuit area, the width of the first metal layer ranges from 40 um to 60 um.

[0009] In some embodiments, along the arrangement direction of the support area and the circuit area, the distance between adjacent first metal layers ranges from 5 um to 30 um.

[0010] In some embodiments, an orthographic projection of the third metal layer on the first surface is located inside an orthographic projection of the first metal layer bonded to the third metal layer on the first surface.

[0011] In some embodiments, a material of the first metal layer is the same as a material of the second metal layer.

[0012] In some embodiments, the material of the first metal layer includes copper, aluminum, or tungsten.

[0013] In some embodiments, in a direction from the first surface to the second surface, a thickness of the first metal layer is the same as a thickness of the third metal layer.

[0014] In some embodiments, in a direction from the first surface to the second surface, the thickness of the first metal layer is 1 μm to 100 μm.

[0015] In some embodiments, the conductive structure protrudes from the second surface of the circuit area; the semiconductor structure further includes: an insulating layer, the insulating layer is located on the second surface of the circuit area, and the insulating layer is also located on the side of the protruding conductive structure, and the third metal layer is located on the surface of the insulating layer.

[0016] In some embodiments, the insulating layer includes: a first dielectric layer, the first dielectric layer is located on the second surface of the circuit area, and the dielectric layer is also located on the side of the protruding conductive structure; a second dielectric layer, the second dielectric layer is located between the first dielectric layer and the third metal layer.

[0017] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a packaging method, including: providing at least two semiconductor structures, each of the semiconductor structures including a first surface and a second surface relative to each other, and the semiconductor structure including a circuit area and a support area, the semiconductor structure in the circuit area having a conductive structure; the semiconductor structure also including: a first metal layer and a second metal layer, the first metal layer being located on the first surface of the circuit area, and the second metal layer being located on the first surface of the support area; a third metal layer and a fourth metal layer, the third metal layer being located on the second surface of the circuit area and electrically connected to the conductive structure, and the fourth metal layer being located on the second surface of the support area; performing bonding processing on at least two of the semiconductor structures so that the first surface of one of the at least two semiconductor structures is opposite to the second surface of another adjacent semiconductor structure, and the first metal layer of the semiconductor structure is in contact and bonded with the third metal layer of the semiconductor structure in the adjacent layer, and the second metal layer of the semiconductor structure is in contact and bonded with the fourth metal layer of the semiconductor structure in the adjacent layer.

[0018] In some embodiments, the process steps for forming the semiconductor structure include: providing an initial semiconductor structure, the initial semiconductor structure including a first surface and a second surface relative to each other, and the initial semiconductor structure including a circuit area and a support area, the initial semiconductor structure in the circuit area having a conductive structure; forming a first metal film on the first surface of the initial semiconductor structure, patterning the first metal film located in the circuit area, and the remaining first metal film in the circuit area serves as the first metal layer, and the first metal film located in the support area serves as the second metal layer; forming a second metal film on the second surface of the initial semiconductor structure, patterning the second metal film located in the circuit area, and the remaining second metal film in the circuit area serves as the third metal layer, and the second metal film located in the support area serves as the fourth metal layer.

[0019] In some embodiments, the process steps of patterning the first metal film located in the circuit area include: forming a first mask layer on the first metal film, etching the first metal film located in the circuit area using the first mask layer as a mask, and forming a plurality of first metal layers arranged at intervals.

[0020] In some embodiments, the process steps of patterning the second metal film located in the circuit area include: forming a second mask layer on the first metal film, etching the second metal film located in the circuit area using the second mask layer as a mask, and forming a plurality of spaced-apart third metal layers.

[0021] In some embodiments, before forming the second metal film, it also includes: thinning the second surface of the initial semiconductor structure to expose the conductive structure of partial thickness; forming a first dielectric layer and a second dielectric layer in sequence on the second surface of the initial semiconductor structure, and the first dielectric layer is also located on the side of the conductive structure of partial thickness.

[0022] In some embodiments, the process parameters of the bonding process include: a process temperature range of the bonding process is 300° C. to 400° C., and a process pressure range of the bonding process is 2.5 MPa to 150 MPa.

[0023] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0024] The embodiments of the present application provide a packaging structure with superior structural performance, which includes at least two stacked semiconductor structures, wherein the first metal layer of the semiconductor structure is in contact and bonded with the third metal layer of the semiconductor structure in an adjacent layer, and the second metal layer of the semiconductor structure is in contact and bonded with the fourth metal layer of the semiconductor structure in an adjacent layer, which is equivalent to achieving high-density vertical interconnection of the at least two stacked semiconductor structures through the contact and bonding of the first metal layer and the third metal layer and the contact and bonding of the second metal layer and the fourth metal layer. The direct contact and bonding of the first metal layer and the third metal layer and the direct contact and bonding of the second metal layer and the fourth metal layer are equivalent to effectively shortening the distance between the at least two stacked semiconductor structures, reducing signal transmission delay and loss, improving signal speed and transmission bandwidth, and reducing power consumption, packaging volume, and packaging weight. At the same time, without changing the size of the package body, the direct contact and bonding of the first metal layer and the third metal layer and the direct contact and bonding of the second metal layer and the fourth metal layer can stack more semiconductor structures in a limited packaging area, which is conducive to improving the integration of integrated circuits.

[0025] Furthermore, the second and fourth metal layers in the support area are continuous films, increasing the proportion of the second and fourth metal layers in the semiconductor structure. Due to their excellent electrical and thermal conductivity, increasing the proportion of the second and fourth metal layers in the semiconductor structure can improve thermal management of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0027] Figure 1 A schematic diagram of a packaging structure;

[0028] Figure 2 A schematic diagram of a packaging structure provided in one embodiment of the present application;

[0029] Figure 3 A schematic diagram of a cross-sectional structure along the AA plane of a packaging structure provided by an embodiment of the present application;

[0030] Figures 4 to 13 This is a schematic diagram of the cross-sectional structure corresponding to each step in the packaging method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] Currently, existing integrated circuits have thermal problems.

[0032] Analysis revealed that the main causes of these issues include: The increased number of stacked micro-components (bare chips and chip components) in 3D packaging creates thermal issues within the integrated circuit. Furthermore, current 3D packaging typically utilizes micro-soldering and encapsulation processes to assemble the micro-components that make up the integrated circuit. Figure 1 This is a schematic diagram of a packaging structure. Figure 1 Analysis shows that the packaging structure includes: at least two stacked semiconductor structures, each semiconductor structure includes a first surface 103 and a second surface relative to each other, and the semiconductor structure includes a circuit area 101 and a support area 102, and the semiconductor structure also includes: a first metal layer 111 and a second metal layer 112, the first metal layer 111 is located on the first surface 103 of the circuit area 101, and the second metal layer 112 is located on the first surface 103 of the support area 102; a third metal layer and a fourth metal layer, the third metal layer is located on the second surface of the circuit area 101, and the fourth metal layer is located on the second surface of the support area 102. 3D packaging technology uses wire bonding, with the wires located between stacked microcomponents. Specifically, the wires are located between the first metal layer 111 and the third metal layer of the adjacent semiconductor structure, and between the second metal layer 112 and the fourth metal layer of the adjacent semiconductor structure. On the one hand, the placement of the wires between the stacked microcomponents increases the vertical size of the integrated circuit, further increasing the power consumption of the integrated circuit. On the other hand, the placement of the wires between the stacked microcomponents increases the distance between the stacked microcomponents, resulting in signal transmission delays and losses. Furthermore, the thermal conductivity of the wires is lower than that of the first metal layer 111, the second metal layer, the third metal layer 112, and the fourth metal layer. The placement of the wires between the stacked microcomponents exacerbates thermal issues within the integrated circuit and prevents timely heat dissipation, further impacting device performance.

[0033] The present application provides a packaging structure with superior structural performance, including at least two stacked semiconductor structures, wherein the first metal layer of the semiconductor structure is in contact and bonded with the third metal layer of the semiconductor structure in an adjacent layer, and the second metal layer of the semiconductor structure is in contact and bonded with the fourth metal layer of the semiconductor structure in an adjacent layer. The first metal layer is in direct contact and bonded with the third metal layer, and the second metal layer is in direct contact and bonded with the fourth metal layer. This is equivalent to effectively shortening the distance between the at least two stacked semiconductor structures, reducing signal transmission delay and loss, increasing signal speed and transmission bandwidth, and reducing power consumption, packaging volume, and packaging weight. In addition, the direct contact and bonding of the first metal layer with the third metal layer and the direct contact and bonding of the second metal layer with the fourth metal layer can expand the area of ​​the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer, which can improve thermal problems of the integrated circuit.

[0034] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0035] Figure 2 A schematic diagram of a packaging structure provided in one embodiment of the present application is shown. Figure 3 A schematic diagram of a cross-sectional structure along plane AA of a packaging structure provided in one embodiment of the present application.

[0036] refer to Figures 2 to 3 The package structure includes: at least two stacked semiconductor structures, each semiconductor structure includes a first surface 203 and a second surface 204 opposite to each other, and the semiconductor structure includes a circuit area 201 and a support area 202, and the semiconductor structure of the circuit area 201 has a conductive structure 208; the semiconductor structure also includes: a first metal layer 211 and a second metal layer 212, the first metal layer 211 is located on the first surface 203 of the circuit area 201, and the second metal layer 212 is located on the first surface 203 of the support area 202; a third metal layer 231 and a fourth metal layer 232, the third metal layer 232 is located on the first surface 203 of the circuit area 201, and the second metal layer 232 is located on the first surface 203 of the support area 202; The metal layer 231 is located on the second surface 204 of the circuit area 201 and is electrically connected to the conductive structure 208, and the fourth metal layer 232 is located on the second surface 204 of the support area 202; wherein, the first surface 203 of one semiconductor structure in at least two stacked semiconductor structures is opposite to the second surface 204 of another adjacent semiconductor structure, and the first metal layer 211 of the semiconductor structure is in contact and bonded with the third metal layer 231 of the semiconductor structure in the adjacent layer, and the second metal layer 212 of the semiconductor structure is in contact and bonded with the fourth metal layer 232 of the semiconductor structure in the adjacent layer.

[0037] The package structure includes at least two stacked semiconductor structures. A first metal layer 211 of the semiconductor structure is bonded to a third metal layer 231 of an adjacent semiconductor structure, and a second metal layer 212 of the semiconductor structure is bonded to a fourth metal layer 232 of an adjacent semiconductor structure. This is equivalent to achieving high-density vertical interconnection between the at least two stacked semiconductor structures through the bonded contact between the first metal layer 211 and the third metal layer 231, and the bonded contact between the second metal layer 212 and the fourth metal layer 232. The direct bonded contact between the first metal layer 211 and the third metal layer 231, and the direct bonded contact between the second metal layer 212 and the fourth metal layer 232, is equivalent to having no welded wires between the at least two stacked semiconductor structures. This effectively shortens the distance between the at least two stacked semiconductor structures, reduces signal transmission delay and loss, increases signal speed and transmission bandwidth, and reduces power consumption, package volume, and package weight. Furthermore, it helps alleviate thermal issues in integrated circuits. At the same time, there is no welded metal wire between at least two stacked semiconductor structures, which can increase the area of ​​the first metal layer 211, the second metal layer 212, the third metal layer 231 and the fourth metal layer 232, thereby increasing the content ratio of the first metal layer 211, the second metal layer 212, the third metal layer 231 and the fourth metal layer 232 in the semiconductor structure, which is further beneficial to improving thermal problems in integrated circuits.

[0038] In some embodiments, the semiconductor structure further includes: a circuit structure 205, an isolation structure 206, and a substrate 207. The circuit structure 205 is located within the semiconductor structure of the circuit area 201 and is electrically connected to the conductive structure 208. The isolation structure 206 and the substrate 207 are located within the semiconductor structure of the circuit area 201 and the support area 202.

[0039] A semiconductor structure is one of the various micro-components that make up an integrated circuit. In some embodiments, the semiconductor structure is a wafer. In other embodiments, the semiconductor structure can be a chip.

[0040] In some embodiments, the first surface 203 of the semiconductor structure is a top surface of the semiconductor structure, and the second surface 204 of the semiconductor structure is a bottom surface of the semiconductor structure.

[0041] In some embodiments, the circuit area 201 has a circuit structure, the circuit structure is electrically connected to the third metal layer 231 through the conductive structure 208, and the first metal layer 211 of the semiconductor structure is in contact and bonded with the third metal layer 231 of the semiconductor structure in the adjacent layer to ensure that at least two stacked semiconductor structures are vertically interconnected and establish signal transmission; there is no circuit structure in the support area 202, which plays a supporting role between at least two stacked semiconductor structures.

[0042] In some embodiments, the semiconductor structure includes a plurality of first metal layers 211 arranged at intervals, and in the arrangement direction of the support area 202 and the circuit area 201, the ratio of the spacing between adjacent first metal layers 211 to the width of the first metal layer 211 ranges from 1 / 12 to 3 / 4, and specifically can be 1 / 6, 1 / 2, or 3 / 5. On the one hand, this ensures that adjacent first metal layers 211 are discontinuous, thereby ensuring that each conductive structure 208 in the circuit area 201 is not electrically connected during the bonding process between the first metal layer 211 and the third metal layer 231 of the semiconductor structure in the adjacent layer, thereby preventing short circuits in the semiconductor structure. On the other hand, the area of ​​the first metal layer 211 is as large as possible, which is equivalent to the first metal layer 211 accounting for as large a proportion of the semiconductor structure as possible, which is beneficial for promoting heat dissipation of the integrated circuit and further improving the stability of the integrated circuit.

[0043] Specifically, along the arrangement direction of the support area 202 and the circuit area 201, the width of the first metal layer 211 ranges from 40um to 60um, specifically 45um, 50um, 55um; the spacing between adjacent first metal layers 211 ranges from 5um to 30um, specifically 10um, 15um, 20um or 25um.

[0044] In some embodiments, the thickness of the first metal layer 211 in the direction from the first surface 203 to the second surface 204 is 1 μm to 100 μm, specifically 10 μm, 30 μm, 50 μm, 70 μm, or 90 μm. This ensures that the first metal layer 211 of the semiconductor structure accounts for as large a proportion as possible, which facilitates heat dissipation of the integrated circuit and further improves the stability of the integrated circuit. Furthermore, this ensures that the memory capacity of a single integrated circuit is as large as possible, i.e., multiple semiconductor structures can be stacked as much as possible within the limited space of a single integrated circuit.

[0045] In some embodiments, the orthographic projection of the first metal layer 211 on the first surface 203 is a rectangle, wherein the length of the rectangle ranges from 55um to 200um, specifically 60um, 80um, 100um or 150um, and the width of the rectangle ranges from 40um to 60um, specifically 45um, 50um, 55um.

[0046] In some embodiments, the material of the first metal layer 211 is copper, wherein the thermal conductivity of copper is 401 W / (m·K). In other embodiments, the material of the first metal layer may also be zinc, silver, aluminum, or tungsten, wherein the thermal conductivity of zinc is 112 W / (m·K), the thermal conductivity of silver is 429 W / (m·K), the thermal conductivity of aluminum is 237 W / (m·K), and the thermal conductivity of tungsten is 173 W / (m·K).

[0047] In some embodiments, the second metal layer 212 located in the support area 202 is a continuous film layer. On the one hand, it ensures that it plays a supporting role between the two stacked semiconductor structures; on the other hand, the content of the second metal layer 212 of the semiconductor structure accounts for a relatively large proportion, which is beneficial to promoting the heat dissipation of the integrated circuit and further beneficial to improving the stability of the integrated circuit.

[0048] In some embodiments, the thickness of the second metal layer 212 may be the same as the thickness of the first metal layer 211 in the direction from the first surface 203 to the second surface 204. In other embodiments, the thickness of the second metal layer may be different from the thickness of the first metal layer.

[0049] In some embodiments, the material of the second metal layer 212 may be the same as that of the first metal layer 211. In other embodiments, the material of the second metal layer may be different from that of the first metal layer.

[0050] In some embodiments, the orthographic projection of the third metal layer 231 on the first surface 203 is located inside the orthographic projection of the first metal layer 211 bonded to the third metal layer 231 on the first surface 203, and the orthographic projection of the third metal layer 231 on the first surface 203 and the orthographic projection of the first metal layer 211 bonded to the third metal layer 231 on the first surface 203 are the same size, which is equivalent to each first metal layer 211 facing each third metal layer 231, ensuring that the areas of the first metal layer 211 and the third metal layer 231 are maximized, which is beneficial to improving thermal problems of the integrated circuit.

[0051] In other embodiments, the orthographic projection of the third metal layer on the first surface is located inside the orthographic projection of the first metal layer bonded to the third metal layer on the first surface, and the orthographic projection of the third metal layer on the first surface is smaller than the orthographic projection of the first metal layer bonded to the third metal layer on the first surface.

[0052] In some embodiments, the thickness of the third metal layer 231 may be the same as the thickness of the first metal layer 211 in the direction from the first surface 203 to the second surface 204. In other embodiments, the thickness of the third metal layer may be different from the thickness of the first metal layer.

[0053] In some embodiments, the material of the third metal layer 232 may be the same as the material of the first metal layer 211. In other embodiments, the material of the third metal layer may be different from the material of the first metal layer.

[0054] In some embodiments, the fourth metal layer 232 located in the support area 202 is a continuous film layer. On the one hand, it ensures that it plays a supporting role between the two stacked semiconductor structures; on the other hand, the content of the fourth metal layer 212 of the semiconductor structure accounts for a relatively large proportion, which is beneficial to promoting the heat dissipation of the integrated circuit and further beneficial to improving the stability of the integrated circuit.

[0055] In some embodiments, the orthographic projection of the fourth metal layer 232 on the first surface 203 is located inside the orthographic projection of the second metal layer 212 bonded to the fourth metal layer 232 on the first surface 203, and the orthographic projection of the fourth metal layer 232 on the first surface 203 is the same size as the orthographic projection of the second metal layer 212 bonded to the fourth metal layer 232 on the first surface, which is equivalent to each second metal layer 212 facing each fourth metal layer 232, ensuring that the area of ​​the second metal layer 212 and the fourth metal layer 232 is maximized, which is beneficial to improving thermal problems of the integrated circuit.

[0056] In other embodiments, the orthographic projection of the fourth metal layer on the first surface is located inside the orthographic projection of the second metal layer on the first surface that is in contact with and bonded to the fourth metal layer, and the orthographic projection of the fourth metal layer on the first surface is smaller than the orthographic projection of the second metal layer on the first surface that is in contact with and bonded to the fourth metal layer.

[0057] In the direction from the first surface 203 to the second surface 204, the upper surface of the fourth metal layer 232 is flush with the upper surface of the third metal layer 231. Specifically, in some embodiments, in the direction from the first surface 203 to the second surface 204, the thickness of the fourth metal layer 232 is less than the thickness of the third metal layer 231. In other embodiments, in the direction from the first surface to the second surface, the thickness of the fourth metal layer is equal to or greater than the thickness of the third metal layer.

[0058] In some embodiments, the material of the fourth metal layer 232 may be the same as the material of the second metal layer 231. In other embodiments, the material of the fourth metal layer may be different from the material of the second metal layer.

[0059] In some embodiments, the conductive structure 208 protrudes from the second surface 204 of the circuit region 201 to ensure electrical connection between the conductive structure 208 and the third metal layer 231 .

[0060] In some embodiments, the isolation structure 206 is made of silicon oxide, and the substrate 207 is made of silicon. In other embodiments, the isolation structure may be made of silicon carbide or silicon nitride, and the substrate may be made of germanium, silicon germanium, or silicon carbide.

[0061] In some embodiments, the semiconductor structure further includes an insulating layer 220 located on the second surface 204 of the circuit region 201 and on the side of the protruding conductive structure 208 . The third metal layer 231 is located on the surface of the insulating layer 220 .

[0062] In some embodiments, the insulating layer 220 includes: a first dielectric layer 221, the first dielectric layer 221 is located on the second surface 204 of the circuit area 201, and the first dielectric layer 221 is also located on the side of the protruding conductive structure 208; and a second dielectric layer 222, the second dielectric layer 222 is located between the first dielectric layer 221 and the third metal layer 231.

[0063] In some embodiments, the material of the first dielectric layer 221 is an insulating material, specifically silicon oxide; the material of the second dielectric layer 222 is silicon nitride. In other embodiments, the material of the first dielectric layer can be silicon carbide or silicon nitride; the material of the second dielectric layer can be an insulating material such as silicon oxide, silicon carbide, or other high-k dielectric constant material.

[0064] In some embodiments of the present application, the packaging structure includes at least two stacked semiconductor structures, the first metal layer of the semiconductor structure is in contact and bonded with the third metal layer of the semiconductor structure in an adjacent layer, the second metal layer of the semiconductor structure is in contact and bonded with the fourth metal layer of the semiconductor structure in an adjacent layer, the first metal layer is in direct contact and bonded with the third metal layer, and the second metal layer is in direct contact and bonded with the fourth metal layer, which is equivalent to effectively shortening the distance between the at least two stacked semiconductor structures, reducing signal transmission delay and loss, improving signal speed and transmission bandwidth, and reducing power consumption, packaging volume, and packaging weight. In addition, the direct contact and bonding of the first metal layer with the third metal layer and the direct contact and bonding of the second metal layer with the fourth metal layer can expand the area of ​​the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer, which can improve the thermal problems of the integrated circuit. Moreover, the materials of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are all copper, and the direct contact between copper and copper can improve the heat dissipation of the semiconductor structure, further improving the thermal problems of the integrated circuit.

[0065] Accordingly, some embodiments of the present application provide a packaging method that can be used to form the above-mentioned packaging structure.

[0066] Figures 4 to 13 This is a structural schematic diagram corresponding to each step in the packaging method provided in one embodiment of the present application. The packaging method provided in this embodiment will be described in detail below in conjunction with the accompanying drawings.

[0067] refer to Figures 4 to 12, providing at least two semiconductor structures, each semiconductor structure including a first surface 203 and a second surface 204 relative to each other, and the semiconductor structure including a circuit area 201 and a support area 202, and the semiconductor structure of the circuit area 201 has a conductive structure 208; the semiconductor structure also includes: a first metal layer 211 and a second metal layer 222, the first metal layer 211 is located on the first surface 203 of the circuit area 201, and the second metal layer 212 is located on the first surface 203 of the support area 202; a third metal layer 231 and a fourth metal layer 232, the third metal layer 231 is located on the second surface 204 of the circuit area 201 and is electrically connected to the conductive structure 208, and the fourth metal layer 232 is located on the second surface 204 of the support area 202.

[0068] refer to Figure 4 , providing an initial semiconductor structure, the initial semiconductor structure including a first surface 203 and a second surface 204 relative to each other, and the initial semiconductor structure including a circuit area 201 and a support area 202, the initial semiconductor structure of the circuit area 201 and the support area 202 having a stacked isolation structure 206 and a substrate 207, the initial semiconductor structure of the circuit area 201 having a conductive structure 208 and a circuit structure 205, the circuit structure 205 is also located in the isolation structure 206 and electrically connected to the conductive structure 208, the isolation structure 206 and the substrate 207 are also located on the side of the conductive structure 208.

[0069] The initial semiconductor structure is one of the various micro-components that make up an integrated circuit. In some embodiments, the initial semiconductor structure is a wafer. In other embodiments, the initial semiconductor structure can be a chip.

[0070] In some embodiments, the first surface 203 of the initial semiconductor structure is the top surface of the initial semiconductor structure, and the second surface 204 of the initial semiconductor structure is the bottom surface of the initial semiconductor structure; the initial semiconductor structure is located on the first carrier 209, and the first surface 203 of the initial semiconductor structure is away from the surface of the first carrier 209.

[0071] In some embodiments, the circuit area 201 has a circuit structure, the circuit structure is electrically connected to the third metal layer 231 through the conductive structure 208, and the first metal layer 211 of the semiconductor structure is in contact and bonded with the third metal layer 231 of the semiconductor structure in the adjacent layer to ensure that at least two stacked semiconductor structures are vertically interconnected and establish signal transmission; there is no circuit structure in the support area 202, which plays a supporting role between at least two stacked semiconductor structures.

[0072] In some embodiments, the isolation structure 206 is made of silicon oxide, and the substrate 207 is made of silicon. In other embodiments, the isolation structure may be made of silicon carbide or silicon nitride, and the substrate may be made of germanium, silicon germanium, or silicon carbide.

[0073] refer to Figure 5 as well as Figure 6 A first metal film 210 is formed on the first surface 203 of the initial semiconductor structure, the first metal film 210 located in the circuit area 201 is patterned, the first metal film 210 in the remaining circuit area 201 serves as the first metal layer 211, and the first metal film 210 located in the support area 202 serves as the second metal layer 212.

[0074] Specifically, refer to Figure 5 , a first metal film 210 is formed on the first surface 203 of the initial semiconductor structure.

[0075] In some embodiments, the thickness of the first metal film 210 in the direction from the first surface 203 to the second surface 204 is 1 μm to 100 μm, specifically 10 μm, 30 μm, 50 μm, 70 μm, or 90 μm. This ensures that the first metal layer 211 of the semiconductor structure accounts for as large a proportion as possible, which facilitates heat dissipation of the integrated circuit and further improves the stability of the integrated circuit. Furthermore, this ensures that the memory capacity of a single integrated circuit is as large as possible, i.e., multiple semiconductor structures can be stacked as much as possible within the limited space of a single integrated circuit.

[0076] In some embodiments, the material of the first metal film 210 is copper, wherein the thermal conductivity of copper is 401 W / (m·K). In other embodiments, the material of the first metal film may also be zinc, silver, aluminum, or tungsten, wherein the thermal conductivity of zinc is 112 W / (m·K), the thermal conductivity of silver is 429 W / (m·K), the thermal conductivity of aluminum is 237 W / (m·K), and the thermal conductivity of tungsten is 173 W / (m·K).

[0077] refer to Figure 6 , a first mask layer is formed on the first metal film 210, and the first mask layer is used as a mask to etch the first metal film 210 located in the circuit area 201 to form a plurality of first metal layers 211 arranged at intervals. The first metal film 210 located in the support area 202 is used as the second metal layer 212, and the first mask layer is removed.

[0078] In some embodiments, the semiconductor structure includes a plurality of first metal layers 211 arranged at intervals, and in the arrangement direction of the support area 202 and the circuit area 201, the ratio of the spacing between adjacent first metal layers 211 to the width of the first metal layer 211 ranges from 1 / 12 to 3 / 4, and specifically can be 1 / 6, 1 / 2, or 3 / 5. On the one hand, this ensures that adjacent first metal layers 211 are discontinuous, thereby ensuring that each conductive structure 208 in the circuit area 201 is not electrically connected during the bonding process between the first metal layer 211 and the third metal layer 231 of the semiconductor structure in the adjacent layer, thereby preventing short circuits in the semiconductor structure. On the other hand, the area of ​​the first metal layer 211 is as large as possible, which is equivalent to the first metal layer 211 accounting for as large a proportion of the semiconductor structure as possible, which is beneficial for promoting heat dissipation of the integrated circuit and further improving the stability of the integrated circuit.

[0079] Specifically, along the arrangement direction of the support area 202 and the circuit area 201, the width of the first metal layer 211 ranges from 40um to 60um, specifically 45um, 50um, 55um; the spacing between adjacent first metal layers 211 ranges from 5um to 30um, specifically 10um, 15um, 20um or 25um.

[0080] In some embodiments, the orthographic projection of the first metal layer 211 on the first surface 203 is a rectangle, wherein the length of the rectangle ranges from 55um to 200um, specifically 60um, 80um, 100um or 150um, and the width of the rectangle ranges from 40um to 60um, specifically 45um, 50um, 55um.

[0081] In some embodiments, the second metal layer 212 in the support region 202 is a continuous film layer. This ensures support between the two stacked semiconductor structures. Furthermore, the relatively high proportion of the second metal layer 212 in the semiconductor structure facilitates heat dissipation in the integrated circuit, further improving the stability of the integrated circuit.

[0082] refer to Figure 7 , the first carrier 209 is removed, and the second carrier 219 is bonded to the initial semiconductor structure.

[0083] In some embodiments, the initial semiconductor structure is located on the second carrier 219 , and the second surface 204 of the initial semiconductor structure is away from the surface of the second carrier 219 .

[0084] refer to Figures 8 to 10, the second surface 204 of the initial semiconductor structure is thinned to expose a partial thickness of the conductive structure 208; a first dielectric layer 221 and a second dielectric layer 222 are sequentially formed on the second surface 204 of the initial semiconductor structure, and the first dielectric layer 221 is also located on the side of the partial thickness of the conductive structure 208.

[0085] refer to Figure 8 The circuit area 201 and the substrate 207 of the support area 202 of the initial semiconductor structure are thinned simultaneously so that the upper surface of the substrate 207 of the support area 202 is flush with the upper surface of the substrate 207 of the circuit area 201, and a partial thickness of the conductive structure 208 is exposed, thereby increasing the proportion of the subsequently formed fourth metal layer in the semiconductor structure, which is beneficial to improving thermal problems in the integrated circuit.

[0086] refer to Figure 9 An initial first dielectric layer 223 and an initial second dielectric layer 224 are sequentially formed on the substrate 207 . The initial first dielectric layer 223 and the initial second dielectric layer 224 are also located on the conductive structure 208 .

[0087] Specifically, in some embodiments, the material of the initial first dielectric layer 223 is an insulating material, specifically silicon oxide; and the material of the initial second dielectric layer 224 is silicon nitride. In other embodiments, the material of the initial first dielectric layer may be silicon carbide or silicon nitride; and the material of the initial second dielectric layer may be an insulating material such as silicon oxide, silicon carbide, or other high-k dielectric constant material.

[0088] In some embodiments, in a direction from the first surface 203 to the second surface 204, the thickness of the initial first dielectric layer 223 on the substrate 207 is the same as the thickness of the initial first dielectric layer 223 on the conductive structure 208; the thickness of the initial second dielectric layer 224 on the substrate 207 is the same as the thickness of the initial second dielectric layer 224 on the conductive structure 208.

[0089] In other embodiments, an initial first dielectric layer and an initial second dielectric layer are sequentially formed only on the substrate in the circuit area, thereby increasing the proportion of the subsequently formed fourth metal layer in the semiconductor structure, which is beneficial to improving thermal issues in the integrated circuit.

[0090] refer to Figure 10 , the initial first dielectric layer 223 and the initial second dielectric layer 224 located on the surface of the conductive structure 208 are etched to expose the conductive structure 208 so that the subsequently formed third metal layer is electrically connected to the conductive structure 208, and the remaining initial first dielectric layer 223 serves as the first dielectric layer 221, and the remaining initial second dielectric layer 224 serves as the second dielectric layer 222.

[0091] refer to Figure 11 as well as Figure 12 A second metal film 230 is formed on the second surface 204 of the initial semiconductor structure, and the second metal film 230 located in the circuit area 201 is patterned. The second metal film 230 in the remaining circuit area 201 serves as the third metal layer 231, and the second metal film 230 located in the support area 202 serves as the fourth metal layer 232.

[0092] Specifically, refer to Figure 11 , a second metal film 230 is formed on the second surface 204 of the initial semiconductor structure.

[0093] In some embodiments, the material of the second metal film 230 may be the same as that of the first metal film 210. In other embodiments, the material of the second metal film may be different from that of the first metal film.

[0094] refer to Figure 12 , a second mask layer is formed on the second metal film 230, and the second mask layer is used as a mask to etch the second metal film 230 located in the circuit area 201 to form a plurality of third metal layers 231 arranged at intervals. The second metal film 230 located in the support area 202 is used as the fourth metal layer 232, and the second mask layer is removed.

[0095] In some embodiments, the semiconductor structure includes a plurality of third metal layers 231 arranged at intervals. In the arrangement direction of the support area 202 and the circuit area 201, the ratio of the spacing between adjacent third metal layers 231 to the width of the third metal layer 231 is the same as the ratio of the spacing between adjacent first metal layers 211 to the width of the first metal layer 211, which can be 1 / 6, 1 / 2, or 3 / 5.

[0096] Specifically, along the arrangement direction of the support area 202 and the circuit area 201, the width of the third metal layer 231 is the same as the width of the first metal layer 211, which can be 45um, 50um, or 55um; the spacing between adjacent third metal layers 231 is the same as the spacing between adjacent first metal layers 211, which can be 10um, 15um, 20um, or 25um.

[0097] In some embodiments, the fourth metal layer 232 located in the support area 202 is a continuous film layer. On the one hand, it ensures that it plays a supporting role between the two stacked semiconductor structures; on the other hand, the content of the fourth metal layer 212 of the semiconductor structure accounts for a relatively large proportion, which is beneficial to promoting the heat dissipation of the integrated circuit and further beneficial to improving the stability of the integrated circuit.

[0098] refer to Figure 13, bonding treatment is performed on at least two semiconductor structures so that the first surface 203 of one semiconductor structure among the at least two semiconductor structures is opposite to the second surface 204 of another adjacent semiconductor structure, and the first metal layer 211 of the semiconductor structure is in contact and bonded with the third metal layer 231 of the semiconductor structure in the adjacent layer, and the second metal layer 212 of the semiconductor structure is in contact and bonded with the fourth metal layer 232 of the semiconductor structure in the adjacent layer.

[0099] In some embodiments, the orthographic projection of the third metal layer 231 on the first surface 203 is located inside the orthographic projection of the first metal layer 211 bonded to the third metal layer 231 on the first surface 203, and the orthographic projection of the third metal layer 231 on the first surface 203 and the orthographic projection of the first metal layer 211 bonded to the third metal layer 231 on the first surface 203 are the same size, which is equivalent to each first metal layer 211 facing each third metal layer 231, ensuring that the areas of the first metal layer 211 and the third metal layer 231 are maximized, which is beneficial to improving thermal problems of the integrated circuit.

[0100] In other embodiments, the orthographic projection of the third metal layer on the first surface is located inside the orthographic projection of the first metal layer bonded to the third metal layer on the first surface, and the orthographic projection of the third metal layer on the first surface is smaller than the orthographic projection of the first metal layer bonded to the third metal layer on the first surface.

[0101] In some embodiments, in some embodiments, the orthographic projection of the fourth metal layer 232 on the first surface 203 is located inside the orthographic projection of the second metal layer 212 bonded to the fourth metal layer 232 on the first surface 203, and the orthographic projection of the fourth metal layer 232 on the first surface 203 and the orthographic projection of the second metal layer 212 bonded to the fourth metal layer 232 on the first surface are the same size, which is equivalent to each second metal layer 212 facing each fourth metal layer 232, ensuring that the area of ​​the second metal layer 212 and the fourth metal layer 232 is maximized, which is beneficial to improving thermal problems of the integrated circuit.

[0102] In other embodiments, the orthographic projection of the fourth metal layer on the first surface is located inside the orthographic projection of the second metal layer on the first surface that is in contact with and bonded to the fourth metal layer, and the orthographic projection of the fourth metal layer on the first surface is smaller than the orthographic projection of the second metal layer on the first surface that is in contact with and bonded to the fourth metal layer.

[0103] In some embodiments, the process parameters of the bonding treatment include: the process temperature range of the bonding treatment is 300℃~400℃, specifically 300℃, 350℃ or 400℃; the process pressure range of the bonding treatment is 2.5MPa~150Mpa, specifically 10MPa, 80MPa or 130MPa.

[0104] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A packaging method, characterized in that: include: At least two semiconductor structures are provided, and the process steps for forming the semiconductor structures include: providing an initial semiconductor structure, the initial semiconductor structure including a first surface and a second surface opposite to each other, and the initial semiconductor structure including a circuit area and a support area, wherein the initial semiconductor structure in the circuit area has a conductive structure; forming a first metal film on the first surface of the initial semiconductor structure, patterning the first metal film in the circuit area, and using the remaining first metal film in the circuit area as the first metal layer, and using the first metal film in the support area as the second metal layer; forming a second metal film on the second surface of the initial semiconductor structure, patterning the second metal film in the circuit area, and using the remaining second metal film in the circuit area as the third metal layer, and using the second metal film in the support area as the fourth metal layer; Each of the semiconductor structures includes a first surface and a second surface opposite to each other, and the semiconductor structure includes a circuit area and a support area, wherein the semiconductor structure in the circuit area has a conductive structure; the semiconductor structure further includes: a first metal layer and a second metal layer, wherein the first metal layer is located on the first surface of the circuit area, and the second metal layer is located on the first surface of the support area; a third metal layer and a fourth metal layer, wherein the third metal layer is located on the second surface of the circuit area and is electrically connected to the conductive structure, and the fourth metal layer is located on the second surface of the support area; At least two of the semiconductor structures are bonded so that the first surface of one of the at least two semiconductor structures is opposite to the second surface of another adjacent semiconductor structure, and the first metal layer of the semiconductor structure is contact-bonded with the third metal layer of the semiconductor structure in the adjacent layer, and the second metal layer of the semiconductor structure is contact-bonded with the fourth metal layer of the semiconductor structure in the adjacent layer.

2. The packaging method according to claim 1, wherein: The process steps of patterning the first metal film located in the circuit area include: forming a first mask layer on the first metal film, and etching the first metal film located in the circuit area using the first mask layer as a mask to form a plurality of first metal layers arranged at intervals.

3. The packaging method according to claim 1, wherein: The process steps of patterning the second metal film located in the circuit area include: forming a second mask layer on the second metal film, etching the second metal film located in the circuit area using the second mask layer as a mask, and forming a plurality of the third metal layers arranged at intervals.

4. The packaging method according to claim 1, wherein: Before forming the second metal film, the method further includes: performing a thinning process on the second surface of the initial semiconductor structure to expose a partial thickness of the conductive structure; A first dielectric layer and a second dielectric layer are sequentially formed on the second surface of the initial semiconductor structure, wherein the first dielectric layer is also located on a side surface of the conductive structure having the partial thickness.

5. The packaging method according to claim 1, wherein: The process parameters of the bonding process include: a process temperature range of the bonding process is 300° C. to 400° C., and a process pressure range of the bonding process is 2.5 MPa to 150 MPa.

6. A packaging structure formed by the method according to any one of claims 1 to 5, characterized in that: include: At least two stacked semiconductor structures, each of the semiconductor structures comprising a first surface and a second surface opposite to each other, and the semiconductor structures comprising a circuit region and a support region, wherein the semiconductor structures in the circuit region have a conductive structure therein; The semiconductor structure further comprises: a first metal layer and a second metal layer, wherein the first metal layer is located on the first surface of the circuit area, and the second metal layer is located on the first surface of the support area; a third metal layer and a fourth metal layer, wherein the third metal layer is located on the second surface of the circuit area and is electrically connected to the conductive structure, and the fourth metal layer is located on the second surface of the support area; In which, the first surface of one of the at least two stacked semiconductor structures is opposite to the second surface of another adjacent semiconductor structure, and the first metal layer of the semiconductor structure is in contact and bonded with the third metal layer of the semiconductor structure in the adjacent layer, and the second metal layer of the semiconductor structure is in contact and bonded with the fourth metal layer of the semiconductor structure in the adjacent layer.

7. The packaging structure according to claim 6, wherein: The second metal layer located in the support area is a whole-surface continuous film layer; the fourth metal layer located in the support area is a whole-surface continuous film layer.

8. The packaging structure according to claim 6, wherein: The semiconductor structure includes a plurality of first metal layers arranged at intervals, and in an arrangement direction along the support area and the circuit area, a ratio of a spacing between adjacent first metal layers to a width of the first metal layer ranges from 1 / 12 to 3 / 4.

9. The packaging structure according to claim 8, wherein: In the arrangement direction of the support area and the circuit area, the width of the first metal layer ranges from 40um to 60um.

10. The packaging structure according to claim 8, wherein: In the arrangement direction of the support area and the circuit area, the distance between adjacent first metal layers ranges from 5 um to 30 um.

11. The packaging structure according to claim 6, wherein: The orthographic projection of the third metal layer on the first surface is located inside the orthographic projection of the first metal layer bonded to the third metal layer on the first surface.

12. The packaging structure according to claim 6, wherein: The material of the first metal layer is the same as that of the second metal layer.

13. The packaging structure according to claim 6 or 12, wherein: The material of the first metal layer includes copper, aluminum or tungsten.

14. The packaging structure according to claim 13, wherein: In a direction from the first surface to the second surface, the thickness of the first metal layer is the same as the thickness of the third metal layer.

15. The packaging structure according to claim 6 or 14, characterized in that: In a direction from the first surface to the second surface, the thickness of the first metal layer is 1 μm to 100 μm.

16. The packaging structure according to claim 6, wherein: The conductive structure protrudes from the second surface of the circuit area; the semiconductor structure further includes: an insulating layer, the insulating layer is located on the second surface of the circuit area, and the insulating layer is also located on the side of the protruding conductive structure, and the third metal layer is located on the surface of the insulating layer.

17. The packaging structure according to claim 16, wherein: The insulation layer includes: a first dielectric layer, the first dielectric layer being located on the second surface of the circuit area and also being located on a side of the protruding conductive structure; A second dielectric layer is located between the first dielectric layer and the third metal layer.

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