Swiss rectifier and passive anti-interference control method thereof

Abstract

This disclosure provides a SWISS rectifier and its self-initiated disturbance rejection control method, the method comprising: based on the three-phase line voltage v of a three-phase AC source. ab v bc v ca Calculate the maximum phase voltage V pmax Minimum phase voltage V pmin and line voltage peak V max Based on peak line voltage V max Actual load voltage V dc The reference voltage V of the load dc * and damping coefficient R a1 The equivalent duty cycle D of the first DC voltage regulator circuit and the second DC voltage regulator circuit is calculated. e Based on the maximum phase voltage V pmax Minimum phase voltage V pmin Preset parameters K and equivalent duty cycle D e The first duty cycle D1 of the first DC voltage regulator circuit and the second duty cycle D2 of the second DC voltage regulator circuit are calculated. Based on the first duty cycle D1 and the second duty cycle D2, the first DC voltage regulator circuit and the second DC voltage regulator circuit are turned on or off to keep the output voltage of the SWISS rectifier constant.

Description

Technical Field

[0001] This disclosure relates to the field of power technology, and in particular to a SWISS rectifier and a self-initiated disturbance rejection control method thereof. Background Technology

[0002] The Swiss rectifier is a step-down rectifier with short-circuit protection, which can limit load current, achieve constant voltage and constant current output, and reduce DC bus voltage, providing a wider range of output voltages. The downstream design can use small-size capacitors and low-voltage switching transistors, thereby reducing the overall system cost, hence its widespread use. However, existing Swiss rectifier control methods have poor anti-interference capabilities, resulting in unsatisfactory dynamic and static response capabilities, and the control process is complex. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is to propose a SWISS rectifier and a self-initiated disturbance rejection control method thereof.

[0004] To achieve the above objectives, this disclosure provides a self-initiated disturbance rejection control method for a SWISS rectifier, wherein the SWISS rectifier converts the AC voltage of a three-phase AC source into a DC voltage and supplies it to the load;

[0005] The SWISS rectifier includes a first DC voltage regulator circuit and a second DC voltage regulator circuit connected between the DC side of the SWISS rectifier and the load; the first DC voltage regulator circuit includes a first DC inductor L1 connected between a first terminal of the DC side and the load and a second DC inductor L2 connected between a second terminal of the DC side and the load;

[0006] The method includes:

[0007] Three-phase line voltage v based on a three-phase AC source ab v bc v ca Calculate the maximum phase voltage V pmax Minimum phase voltage V pmin and line voltage peak V max ;

[0008] Based on the peak line voltage V max Actual load voltage V dc The reference voltage V of the load dc * and damping coefficient R a1 The equivalent duty cycle D of the first DC voltage regulator circuit and the second DC voltage regulator circuit is calculated. e ;

[0009] Based on the maximum phase voltage Vpmax the phase voltage minimum value V pmin a preset parameter K and the equivalent duty cycle D e , the first duty cycle D1 of the first direct current stabilizing circuit and the second duty cycle D2 of the second direct current stabilizing circuit are calculated;

[0010] The first direct current stabilizing circuit and the second direct current stabilizing circuit are controlled based on the first duty cycle D1 and the second duty cycle D2 to make the output voltage of the SWISS rectifier constant.

[0011] In another aspect, the present disclosure provides a SWISS rectifier controlled by the method according to the first aspect.

[0012] As can be seen from the above, the SWISS rectifier and the passive active disturbance rejection control method thereof provided by the present disclosure are based on the actual voltage of the load and the reference voltage, the actual current of the direct current stabilizing circuit of the direct current side of the SWISS rectifier, and the line voltage peak value of the alternating current side, and the direct current stabilizing circuit of the direct current side of the SWISS rectifier is controlled by using the control mode of combining linear active disturbance rejection control and passive control, so that the anti-interference ability of the SWISS rectifier is improved, the dynamic and static response effects are improved, and the control process is simple and easy to implement. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the present disclosure or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0014] Figure 1 It is a schematic main circuit diagram of the SWISS rectifier according to the embodiments of the present disclosure.

[0015] Figure 2 It is a schematic diagram of the active disturbance rejection controller according to the embodiments of the present disclosure.

[0016] Figure 3 It is a schematic principle diagram of the active disturbance rejection control method of the SWISS rectifier according to the embodiments of the present disclosure.

[0017] Figure 4 It is a response curve schematic diagram when the load is suddenly changed according to the embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present disclosure more clear and apparent, the present disclosure will be further described in detail below with specific embodiments and with reference to the drawings.

[0019] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure shall have the common meaning understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0020] The SWISS rectifier is a step-down rectifier with short-circuit protection function, which can limit the load current, realize constant-voltage and constant-current output, reduce the DC bus voltage, provide a wider range of output voltage, and the design of the rear stage can select small-size capacitors and low-voltage switching tubes, thereby reducing the cost of the whole system. At the same time, the SWISS rectifier only has two upper and lower switching tubes and freewheeling diodes for high-frequency operation, which can bring extremely high efficiency. However, the existing SWISS rectifier mostly uses PI control, which has the disadvantages of large output voltage overshoot, slow dynamic response speed, and poor anti-interference performance.

[0021] In view of this, the embodiments of the present disclosure provide a disturbance rejection control method for a SWISS rectifier, which controls the DC side DC voltage stabilization circuit of the SWISS rectifier based on the actual voltage and reference voltage of the load, the actual current of the DC side DC voltage stabilization circuit of the SWISS rectifier, and the line voltage peak value of the AC side, adopts a control mode combining linear disturbance rejection control and passive control, improves the anti-interference ability of the SWISS rectifier, improves the dynamic and static response effect, and the control process is simple and easy to implement.

[0022] Referring to Figure 1 , Figure 1 A schematic main circuit diagram of a SWISS rectifier according to an embodiment of the present disclosure is shown. Figure 1 In the SWISS rectifier 100, the SWISS rectifier 100 includes an AC filter circuit 110, an uncontrollable rectifier circuit 120, a harmonic injection circuit 130, a first DC voltage stabilization circuit 140, a second DC voltage stabilization circuit 150, a DC capacitor C, and a load R L .

[0023] The AC filter circuit 110 is connected to a three-phase AC source (for example, a three-phase AC power grid) and is configured to filter out high-order harmonics of the three-phase AC source to obtain a filtered voltage. In particular, the AC voltage output by the three-phase AC source is filtered by the AC filter circuit 110 to obtain the filtered voltage. The filtered voltage is output by the AC filter circuit 110 to the uncontrolled rectifier circuit 120 as an input of the uncontrolled rectifier circuit 120.

[0024] In some embodiments, the AC filter circuit 110 can include a filter inductor circuit and a filter capacitor circuit. Further, the filter inductor circuit includes a first inductor L Fa , a second inductor L Fb , and a third inductor L Fc , and the filter capacitor circuit includes a first capacitor C Fa , a second capacitor C Fb , and a third capacitor C Fc . The first ends of the first inductor L Fa , the second inductor L Fb , and the third inductor L Fc are respectively connected to the three-phase AC source. The second end of the first inductor L Fa is connected to the first end of the first capacitor C Fa , the second end of the second inductor L b is connected to the first end of the second capacitor C Fb , and the second end of the third inductor L Fc is connected to the first end of the third capacitor C Fc . The second ends of the first capacitor C Fa , the second capacitor C Fb , and the third capacitor C Fc are connected to each other.

[0025] The uncontrolled rectifier circuit 120 is connected to the output of the AC filter circuit 110 and is configured to rectify the filtered voltage to obtain a rectified voltage. In particular, the uncontrolled rectifier circuit 120 rectifies the AC voltage output by the AC filter circuit 110 to obtain the rectified voltage.

[0026] In some embodiments, the uncontrolled rectifier circuit 120 includes a first diode D1 to a sixth diode D6. In particular, the cathodes of the first diode D1, the second diode D2, and the third diode D3 are connected to each other, and the connection point is denoted as a first connection point p. The anode of the first diode D1 is connected to the first end of the first capacitor C Fa (the second end of the first inductor L Fa ), the anode of the second diode D2 is connected to the first end of the second capacitor C Fb (the second end of the second inductor L Fb ), and the anode of the third diode D3 is connected to the first end of the third capacitor C Fc .The first terminal (i.e., the third inductor L) Fc The second terminal); the anodes of the fourth diode D4, the fifth diode D5, and the sixth diode D6 are interconnected, and this connection point is denoted as the second connection point n. The cathode of the fourth diode D4 is connected to the first capacitor C. Fa The first terminal (i.e., the first inductor L) Fa The cathode of the fifth diode D5 is connected to the second capacitor C (the second terminal of the diode). Fb The first terminal (i.e., the second inductor L) Fb The second terminal of the sixth diode (D6) is connected to the cathode of the third capacitor C. Fc The first terminal (i.e., the third inductor L) Fc (the second end).

[0027] The harmonic injection circuit 130 is connected to the uncontrolled rectifier circuit 120 and is used to perform dead-time compensation on the uncontrolled rectifier circuit 120. This compensates for the dead-time of the input current in the non-conducting phase of the uncontrolled rectifier circuit 120, thereby achieving unity power factor correction.

[0028] In some embodiments, the harmonic injection circuit 130 includes a first switching unit SW1, a second switching unit SW2, and a third switching unit SW3; the first terminal of the first switching unit SW1 is connected to the first capacitor C. Fa The first terminal (i.e., the first inductor L) Fa The second terminal of the second switching unit SW2 is connected to the second capacitor C. Fb The first terminal (i.e., the second inductor L) Fb The second terminal of the third switching unit SW3 is connected to the first terminal of the third capacitor C. Fc The first terminal (i.e., the third inductor L) Fc The second ends of the first switch unit SW1, the second switch unit SW2, and the third switch unit SW3 are interconnected to a third connection point (this third connection point can be denoted as y).

[0029] In some embodiments, the first switching unit SW1, the second switching unit SW2, and the third switching unit SW3 may have the same structure. Further, this identical structure may include a first power device (e.g., an IGBT) and a second power device (e.g., an IGBT). The first and second power devices may be bidirectional switches, with their control terminals (e.g., gates) connected as the control terminals of the switching unit; their emitters are connected; and their collectors serve as the first and second terminals of the switching unit, respectively. Further, a diode is connected between the emitter and collector of the first and second power devices, with the anode connected to the emitter and the cathode connected to the collector.

[0030] wherein the first, second and third switching units SW1, SW2 and SW3 correspond to the three phases A, B and C respectively. When the instantaneous value of the voltage of a phase (e.g. phase A) of the three-phase AC source is the largest, the diode (e.g. D1) corresponding to the phase is turned on, that is, only one of D1-D3 is turned on. When the instantaneous value of the voltage of a phase (e.g. phase B) of the three-phase AC source is the smallest, the diode (e.g. D5) corresponding to the phase is turned on, that is, only one of D4-D6 is turned on. Therefore, only two phases of the three-phase AC source are turned on and the current flows in parallel. For the phase (e.g. phase C) that is not turned on, the harmonic current injection control is applied to control the switch (e.g. switching unit SW3) corresponding to the phase in the first, second or third switching unit SW1, SW2 or SW3 to be turned on to provide an additional current path, thereby compensating for the dead zone of the current.

[0031] In some embodiments, the first and second DC voltage stabilizing circuits 140 and 150 are connected in series with the uncontrolled rectifying circuit 120, respectively, to output a constant DC voltage based on the rectified voltage output by the uncontrolled rectifying circuit 120.

[0032] In some embodiments, the first DC voltage stabilizing circuit 140 is connected to the first end (e.g. first connection point p) of the uncontrolled rectifying circuit 120, and the second DC voltage stabilizing circuit 150 is connected to the second end (e.g. second connection point n) of the uncontrolled rectifying circuit 120.

[0033] In some embodiments, the first DC voltage stabilizing circuit 140 comprises a first controllable switch T1, a first DC inductor L1 and a seventh diode D y+ wherein the first end (e.g. collector of IGBT) of the first controllable switch T1 is connected to the first end (e.g. first connection point p) of the uncontrolled rectifying circuit 120, the second end (e.g. emitter of IGBT) of the first controllable switch T1 is connected to the first end of the first DC inductor L1 and the cathode of the seventh diode D y+ the anode of the seventh diode D y+ is connected to the third connection point y, and the second end of the first DC inductor L1 is connected to the first end of the DC capacitor C and the first end of the load R L .

[0034] In some embodiments, the second DC voltage stabilizing circuit 150 comprises a second controllable switch T2, a second DC inductor L2 and an eighth diode D y- wherein the first end (e.g. emitter of IGBT) of the second controllable switch T2 is connected to the second end (e.g. second connection point n) of the uncontrolled rectifying circuit 120, the second end (e.g. collector of IGBT) of the second controllable switch T2 is connected to the first end of the second DC inductor L2 and the anode of the eighth diode D y- the cathode of the eighth diode Dy- The cathode of the seventh diode D L is connected to the second end of the second DC inductor L2 and the second end of the DC capacitor C and the load R y+ The anode of the seventh diode D y- is connected to the third connection point y.

[0035] Based on the circuit structure in Figure 1 , according to the on and off states of the first controllable switch T1 in the first DC voltage stabilizing circuit 140 and the second controllable switch T2 in the second DC voltage stabilizing circuit 150, the Kirchhoff's current law KCL and the Kirchhoff's voltage law KVL equations of the first DC voltage stabilizing circuit 140 or the second DC voltage stabilizing circuit 150 can be obtained as follows:

[0036]

[0037] Wherein, i L is the actual current of the DC inductor (for example, the first DC inductor L1 or the second DC inductor L2 in Figure 1 ), v py and v yn are the potential of the first connection point (p point) to the third connection point (y point), i.e. the first potential difference; and the potential of the third connection point (y point) to the second connection point (n point), i.e. the second potential difference. μ1 and μ2 are the switching functions of the first controllable switch T1 and the second controllable switch T2 respectively, including:

[0038]

[0039] After the switching function is processed by periodic averaging, the following can be obtained:

[0040]

[0041] Wherein, D1 and D2 are the duty cycles of the first controllable switch T1 and the second controllable switch T2 respectively.

[0042] Since V max in formula (1) is the peak value of the line voltage. The equivalent duty cycle D e can be defined as:

[0043]

[0044] Then formula (3) can be expressed as:

[0045]

[0046] Wherein,

[0047] Figure 1 The first DC voltage stabilizing circuit 140 and the second DC voltage stabilizing circuit 150 in the SWISS rectifier can be equivalent to a BUCK voltage reducing circuit, and the formula (5) can be an average equivalent circuit model of the first DC voltage stabilizing circuit 140 and the second DC voltage stabilizing circuit 150. That is, the SWISS rectifier can be equivalent to a BUCK circuit for passive control, for example, a passive controller is used to passively control the SWISS rectifier. Then, the equivalent duty cycle D e may comprise:

[0048]

[0049] wherein i L * is a reference current of the first DC inductor L1 or the second DC inductor L2, V dc * is a reference voltage of the load, V dc is an actual voltage of the load, R a1 is a damping coefficient of the passive control (PBC). In some embodiments, the damping coefficient R a1 may be adjusted within a preset range as needed.

[0050] The SWISS rectifier can also be controlled by a self-disturbance control, for example, a first-order linear self-disturbance control (LADRC), and the reference current i L * comprises:

[0051]

[0052] wherein z1 is a tracking signal of the load voltage V dc , z2 is a differential form of z1, b0 is a gain estimation value of the self-disturbance control, and k p is a proportional coefficient.

[0053] In some embodiments, the first-order linear self-disturbance control (LADRC) can comprise a linear extended state observer (LESO) and a linear state error feedback control law (LSEF). As Figure 2 shown, Figure 2 a schematic diagram of a self-disturbance control according to an embodiment of the present disclosure is shown. Figure 2 In the linear extended state observer (LESO), the value of z1 is observed, and z2 can be a differential form of z1.

[0054] Accordingly, the following can be further obtained:

[0055]

[0056] wherein D1 is a first duty cycle, D2 is a second duty cycle, and De For the equivalent duty cycle, the parameters V N V represents the phase voltage amplitude (e.g., the phase voltage amplitude of a three-phase AC source). pmax V represents the maximum phase voltage (e.g., the maximum phase voltage of a three-phase AC source). pmin This refers to the minimum phase voltage (e.g., the minimum phase voltage of a three-phase AC source).

[0057] Therefore, by controlling the first controllable switch T1 in the first DC voltage regulator circuit to turn on or off based on the first duty cycle D1, and by controlling the second controllable switch T2 in the second DC voltage regulator circuit to turn on or off based on the second duty cycle D2 (e.g., PWM control based on the first duty cycle D1 and the second duty cycle D2), the output voltage of the SWISS rectifier 100 can be kept constant, thereby enhancing the anti-interference capability and improving the dynamic and static response capabilities.

[0058] See Figure 2 , Figure 2 A schematic diagram of a passive disturbance rejection control method for a SWISS rectifier according to an embodiment of the present disclosure is shown. Figure 1 and Figure 2 The passive disturbance rejection control method for SWISS rectifiers may include:

[0059] Three-phase line voltage v based on a three-phase AC source ab v bc v ca Calculate the maximum phase voltage V pmax Minimum phase voltage V pmin and line voltage peak V max ;

[0060] Based on the peak line voltage V max Actual load voltage V dc The reference voltage V of the load dc * and damping coefficient R a1 The equivalent duty cycle D of the first DC voltage regulator circuit and the second DC voltage regulator circuit is calculated. e ;

[0061] Based on the maximum phase voltage V pmax Minimum phase voltage V pmin Parameter K and equivalent duty cycle D e The first duty cycle D1 of the first DC voltage regulator circuit and the second duty cycle D2 of the second DC voltage regulator circuit are calculated.

[0062] The first DC voltage stabilizing circuit and the second DC voltage stabilizing circuit are controlled based on the first duty ratio D1 and the second duty ratio D2, so that the output voltage of the SWISS rectifier is constant.

[0063] In some embodiments, the equivalent duty ratio D max of the first DC voltage stabilizing circuit and the second DC voltage stabilizing circuit is calculated based on the line voltage peak value V dc , the actual voltage V dc of the load, the reference voltage V * of the load, and the damping coefficient R a1 . e

[0064] The reference current value i dc * of the first DC inductor L1 or the second DC inductor L2 is calculated based on the actual voltage V dc of the load and the reference voltage V L * of the load.

[0065] The equivalent duty ratio D max of the first DC voltage stabilizing circuit and the second DC voltage stabilizing circuit is calculated based on the line voltage peak value V dc , the actual voltage V a1 of the load, the damping coefficient R L , and the actual current i L and the reference current value i e * of the first DC inductor L1 or the second DC inductor L2.

[0066] In some embodiments, the reference current value i dc * of the first DC inductor or the second DC inductor is calculated based on the actual voltage V dc of the load and the reference voltage V L * of the load, and further comprising:

[0067]

[0068] wherein z1 is a tracking signal of the load voltage V dc , z2 is a differential form of z1, b0 is a gain estimation value of active disturbance rejection control, and k p is a proportional coefficient.

[0069] In some embodiments, the equivalent duty ratio D max of the first DC voltage stabilizing circuit and the second DC voltage stabilizing circuit is calculated based on the line voltage peak value V dc , the actual voltage V a1 of the load, the damping coefficient R L , and the reference current value i e * of the first DC inductor L1 or the second DC inductor L2., further comprising:

[0070] wherein,

[0071] In some embodiments, the first duty cycle D1 of the first DC voltage stabilizing circuit and the second duty cycle D2 of the second DC voltage stabilizing circuit are calculated based on the phase voltage maximum value V pmax , the phase voltage minimum value V pmin , the parameter K and the equivalent duty cycle D e .

[0072]

[0073] wherein, V N is the phase voltage amplitude of the three-phase AC source, V pmax is the phase voltage maximum value, V pmin is the phase voltage minimum value.

[0074] According to the embodiments of the present disclosure, a SWISS rectifier is also provided, which is controlled by the method according to the embodiments of the present disclosure.

[0075] Referring to Figure 4 , Figure 4 Fig. 6 shows a response curve schematic diagram when the load mutates according to the embodiments of the present disclosure. When the load mutates, (a) is the waveform curve of the output voltage V dc of the load R L , (b) is the waveform curve of the output current i L of the first DC inductor L1 / second DC inductor L2. At time 0.2s, the load R L mutates, and the resistance of the load R L changes from 7.5Ω to 15Ω; at time 0.25s, the resistance of the load R changes from 15Ω to 7.5Ω, and a comparative analysis is made by using PI control (for example, PI curve), separate passive control (for example, PBC curve) and passive combined active disturbance rejection control (for example, LADRC+PBC curve) according to the embodiments of the present application, respectively. It can be seen that the output voltage fluctuation values are 24V, 34V and 30V respectively, and the adjustment times are 0.035s, 0.04s and 0.01s respectively. Compared with PI control and separate passive control (PBC), the passive active disturbance rejection control (such as LADRC+PBC) method according to the embodiments of the present application has better dynamic response capability.

[0076] Those skilled in the art should understand that the above discussion of any embodiment is merely exemplary, and is not intended to be limiting of the scope of the disclosure (including claims) to these examples; the above embodiments or technical features among different embodiments can also be combined, steps can be implemented in any order, and there are many other variations of the aspects of the disclosed embodiments as described above, which are within the scope of the present disclosure, and for the sake of brevity, they are not described in detail. It is intended that every aspect contained in the disclosure, including the preferred embodiments, be embraced by the present disclosure.

[0077] In addition, to simplify the illustration and discussion, and so as not to make the embodiments of the present disclosure difficult to understand, the well-known power / ground connections of integrated circuit (IC) chips and other components can or can not be shown in the provided drawings. Furthermore, the apparatuses can be shown in block diagram form in order to avoid making the embodiments of the present disclosure difficult to understand, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform to be implemented (i.e., these details should be well within the understanding of those skilled in the art). Where specific details (e.g., circuitry) are set forth in order to describe an illustrative embodiment of the present disclosure, it will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details or with an equivalent arrangement. Therefore, these descriptions should be considered in a descriptive sense only and not limiting.

[0078] The embodiments of the present disclosure are intended to cover all such alternatives, modifications, and variations of the present disclosure falling within the broad scope of the appended claims. Accordingly, any and all such modifications, variations or equivalents that fall within the spirit and scope of the disclosed embodiments are intended to be included within the scope of the present disclosure.

Claims

1. A passive active disturbance rejection control method for a SWISS rectifier, characterized in that, The SWISS rectifier converts alternating voltage of a three-phase alternating current source into direct voltage and provides the direct voltage to a load; The SWISS rectifier includes a first direct-current stabilizing circuit and a second direct-current stabilizing circuit connected between a direct-current side of the SWISS rectifier and the load; the first direct-current stabilizing circuit includes a first direct-current inductor L1 connected between a first end of the direct-current side and the load and a second direct-current inductor L2 connected between a second end of the direct-current side and the load; The method includes: the three-phase line voltage v based on a three-phase ac source ab , v bc , v ca calculating the phase voltage maximum value v pmax , the phase voltage minimum value v pmin and the line voltage peak value v max ; Based on the peak line voltage V max Actual load voltage V dc The reference voltage V of the load dc * and damping coefficient R a1 The equivalent duty cycle D of the first DC voltage regulator circuit and the second DC voltage regulator circuit is calculated. e ; based on the phase voltage maximum value V pmax , the phase voltage minimum value V pmin , a preset parameter K and the equivalent duty ratio D e , the first duty ratio D1 of the first direct current voltage stabilizing circuit and the second duty ratio D2 of the second direct current voltage stabilizing circuit are calculated. controlling turn-on or turn-off of the first direct-current stabilizing circuit and the second direct-current stabilizing circuit based on the first duty ratio D1 and the second duty ratio D2, so that output voltage of the SWISS rectifier is constant; Among them, based on the peak line voltage V max Actual load voltage V dc The reference voltage V of the load dc * and damping coefficient R a1 The equivalent duty cycle D of the first DC voltage regulator circuit and the second DC voltage regulator circuit is calculated. e ,include: based on an actual voltage V of the load dc and a reference voltage V of the load dc a reference current value i of the first direct current inductance L1 or the second direct current inductance L2 is calculated L *; based on the line voltage peak value V max , the actual voltage V dc of the load, the damping coefficient R a1 , and the reference current value i L * of the first DC inductor L1 or the second DC inductor L2, the equivalent duty cycle D e of the first DC voltage stabilizing circuit and the second DC voltage stabilizing circuit is calculated. wherein a reference current value i dc * of the first DC inductor L1 or the second DC inductor L2 is calculated based on an actual voltage V L * of the load and a reference voltage Vdc* of the load, and further comprising: wherein z1 is a load voltage V dc , z2 is a differential form of z1, b0 is a gain estimation value of the active disturbance rejection control, k p is a proportional coefficient; based on the line voltage peak value V max , the actual voltage V dc of the load, the damping coefficient R a1 , and the reference current value i L of the first DC inductor L1 or the second DC inductor L2, to calculate the equivalent duty cycle D e of the first DC voltage stabilizing circuit and the second DC voltage stabilizing circuit, further comprising: wherein, Wherein, based on the phase voltage maximum V pmax , the phase voltage minimum V pmin , the preset parameter K and the equivalent duty cycle De, the first duty cycle D1 of the first direct current voltage stabilizing circuit and the second duty cycle D2 of the second direct current voltage stabilizing circuit are calculated, and further comprising: wherein the preset parameter V N is the phase voltage amplitude of the three-phase AC source.

2. A SWISS rectifier characterized by, The method is controlled by using the method according to claim 1.

3. The SWISS rectifier of claim 2, wherein, The method includes: an alternating current filtering circuit, an uncontrollable rectifying circuit, a harmonic injection circuit, a first direct-current stabilizing circuit, a second direct-current stabilizing circuit, and a direct-current capacitor; The alternating current filtering circuit is connected to the three-phase alternating current source and is used to filter out high-order harmonics of the three-phase alternating current source to obtain a filtered voltage; The uncontrollable rectifying circuit is connected to an output end of the alternating current filtering circuit and is used to rectify the filtered voltage to obtain a rectified voltage; The harmonic injection circuit is connected to the uncontrollable rectifying circuit and is used to perform dead-zone compensation on the uncontrollable rectifying circuit to achieve unit power factor; The first direct-current stabilizing circuit and the second direct-current stabilizing circuit are connected in cascade with the uncontrollable rectifying circuit and are used to output constant direct-current voltage based on the rectified voltage output by the uncontrollable rectifying circuit; the first direct-current stabilizing circuit is connected to a first end of the uncontrollable rectifying circuit, and the second direct-current stabilizing circuit is connected to a second end of the uncontrollable rectifying circuit.

4. The SWISS rectifier of claim 3, wherein, The alternating current filtering circuit includes a filtering inductor circuit and a filtering capacitor circuit; The filter inductance circuit comprises a first inductor L Fa , a second inductor L Fb and a third inductor L Fc , and the filter capacitance circuit comprises a first capacitor C Fa , a second capacitor C Fb and a third capacitor C Fc ; the first ends of the first inductor L Fa , the second inductor L Fb and the third inductor L Fc are connected to the three-phase alternating current source respectively; the second end of the first inductor L Fa is connected to the first end of the first capacitor C Fa , the second end of the second inductor L b is connected to the first end of the second capacitor C Fb , and the second end of the third inductor L Fc is connected to the first end of the third capacitor C Fc ; and the second ends of the first capacitor C Fa , the second capacitor C Fb and the third capacitor C Fc are connected to each other.

5. The SWISS rectifier of claim 4, wherein, The uncontrollable rectifying circuit includes first to sixth diodes D1 to D6; Wherein, the cathodes of the first diode D1, the second diode D2 and the third diode D3 are connected to each other at a first connection point p, the anode of the first diode D1 is connected to the first end of the first capacitor C Fa , the anode of the second diode D2 is connected to the first end of the second capacitor C Fb , and the anode of the third diode D3 is connected to the first end of the third capacitor C Fc ; the anodes of the fourth diode D4, the fifth diode D5 and the sixth diode D6 are connected to each other at a second connection point n, the cathode of the fourth diode D4 is connected to the first end of the first capacitor C Fa , the cathode of the fifth diode D5 is connected to the first end of the second capacitor C Fb , and the cathode of the sixth diode D6 is connected to the first end of the third capacitor C Fc .

6. The SWISS rectifier of claim 5, wherein, The harmonic injection circuit comprises a first switch unit SW1, a second switch unit SW2 and a third switch unit SW3; wherein a first end of the first switch unit SW1 is connected to a first end of a first capacitor C Fa , a first end of the second switch unit SW2 is connected to a first end of a second capacitor C Fb , and a first end of the third switch unit SW3 is connected to a first end of a third capacitor C Fc ; and second ends of the first switch unit SW1, the second switch unit SW2 and the third switch unit SW3 are connected to each other to a third connection point.

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