Resistance change type nonvolatile memory device and writing method thereof

Abstract

A resistance change type nonvolatile memory device includes a resistance change element (RSE) that can reversibly change to a high resistance state and a low resistance state, and a current supply circuit (24) that supplies a low-resistance current for changing the resistance change element from the high resistance state to the low resistance state to the resistance change element, a current waveform of the low-resistance current has a first period and a second period following the first period on a time axis, the low-resistance current applies a first current to the resistance change element in the first period and applies a second current smaller than the first current to the resistance change element in the second period, the first current at the end of the first period is not 0, and the second current at the start of the second period is not 0.

Description

TECHNICAL FIELD

[0001] The present application relates to a resistance change type nonvolatile memory device and a writing method thereof, which are constituted of a memory cell constituted of a resistance change type nonvolatile memory element whose resistance value reversibly changes based on an electric signal, and the like. BACKGROUND

[0002] In recent years, research and development of a resistance change type nonvolatile memory device having a memory cell constituted of a resistance change type nonvolatile memory element is being conducted. The resistance change type nonvolatile memory element refers to an element having a property that a resistance value reversibly changes based on an electric signal or the like, and capable of nonvolatilely storing data corresponding to the resistance value. As the resistance change type nonvolatile memory device, ReRAM based on a change in resistance value caused by a redox reaction, MRAM based on a change in magnetic resistance, PCRAM based on a change in resistance value caused by a phase change, and the like are known.

[0003] It is known that these resistance change type nonvolatile memory devices achieve control of the resistance value or stabilization of the operation by controlling the amount of current flowing through the resistance change type nonvolatile memory element or the applied voltage value in the rewriting operation thereof. For example, such a resistance change type nonvolatile memory device is disclosed in Patent Literature 1.

[0004] PRIOR ART DOCUMENT

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Patent Application Laid-Open No. 2012-27972 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] However, in the conventional resistance change type nonvolatile memory device, for example, in the case of low power consumption along with miniaturization of the resistance change element, if the writing current for changing the resistance change element from the high resistance state to the low resistance state is reduced, there is a problem that the initial operation window cannot be sufficiently ensured. Here, the operation window refers to a difference between a read current obtained in the high resistance state and a read current obtained in the low resistance state. If this difference is sufficiently large, stable read operation is ensured. In contrast, the smaller this difference, the greater the possibility of read error. Further, the operation window tends to deteriorate due to high cycling operation, that is, rewriting operation a plurality of times (for example, 100,000 times). Here, the initial operation window refers to the operation window at the time of rewriting operation immediately after manufacture (for example, several tens of times or several hundred times or so from the first time).

[0009] On the other hand, there is a problem that, when the above-described low-resistance writing current is increased, although the initial operation window can be ensured, the deterioration of the operation window caused by the high-cycle operation is significantly increased.

[0010] Therefore, an object of the present disclosure is to provide a resistance change type nonvolatile storage device capable of expanding the initial operation window and suppressing the deterioration of the operation window caused by the multiple rewriting operation, and a writing method thereof.

[0011] Means for solving the problem

[0012] A resistance change type nonvolatile storage device of one embodiment of the present disclosure includes a resistance change element that can be reversibly changed between a high-resistance state and a low-resistance state, and a current supply circuit that supplies a low-resistance current for changing the resistance change element from the high-resistance state to the low-resistance state to the resistance change element, the low-resistance current having a down staircase-shaped current waveform.

[0013] Effects of the invention

[0014] According to the resistance change type nonvolatile storage device of the present disclosure, the initial operation window can be expanded, and the deterioration of the operation window caused by the multiple rewriting operation can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1A FIG. 1 is a diagram illustrating a structure example of a main part of a resistance change type nonvolatile storage device in an embodiment.

[0016] Figure 1B FIG. 2 is a diagram illustrating an example of a current waveform of a low-resistance current.

[0017] Figure 2A FIG. 3 is a diagram illustrating a more detailed structure example of a main part of a resistance change type nonvolatile storage device in an embodiment.

[0018] Figure 2B FIG. 4 is a timing chart illustrating the operation of a constant current control circuit in an embodiment.

[0019] Figure 3 FIG. 5 is a diagram illustrating a circuit symbol and a cross section of a resistance change type nonvolatile storage element in an embodiment.

[0020] Figure 4 FIG. 6 is a diagram illustrating a processing flow for an experiment including a multiple rewriting process.

[0021] Figure 5 FIG. 7 is a normal expectation value dot plot illustrating the experimental results of a 1T1R memory cell as a comparative example.

[0022] Figure 6 FIG. 8 is a diagram illustrating a resistance change type nonvolatile storage device in an embodiment.Figure 2A A normal expectation value dot plot of a cell current distribution of the 1T1R memory cell in FIG. 1.

[0023] Figure 7 is a block diagram showing a structure example of a resistance change type nonvolatile memory device in an embodiment.

[0024] Figure 8 is a diagram showing a write circuit example of a resistance change type nonvolatile memory device in an embodiment.

[0025] Figure 9 is a diagram showing a column selection circuit example of a resistance change type nonvolatile memory device in an embodiment.

[0026] Figure 10 is a row selection circuit diagram of a resistance change type nonvolatile memory device in an embodiment.

[0027] Figure 11 is a timing chart of a resistance change type nonvolatile memory device in an embodiment.

[0028] Figure 12 is a bias diagram of a memory cell of a resistance change type nonvolatile memory device in an embodiment.

[0029] Figure 13 is a diagram showing a structure of a resistance change type nonvolatile memory device as a comparative example.

[0030] Figure 14 is a diagram showing a drive condition of a resistance change type nonvolatile memory device in an embodiment.

[0031] Figure 15 is a diagram showing a modification example of a main part of a resistance change type nonvolatile memory device in an embodiment.

[0032] Figure 16 is a diagram showing a modification example of a current waveform of a low resistance change current in an embodiment.

[0033] Figure 17 is a diagram showing another modification example of a current waveform of a low resistance change current in a modification example of an embodiment. DETAILED DESCRIPTION

[0034] (Insight that became the basis of the present invention)

[0035] The present inventors found that the following problems arise with respect to the resistance change type nonvolatile memory device described in the "BACKGROUND" section.

[0036] In Patent Literature 1, a drive circuit (pass transistor) and a drive method suitable for parallel driving of a low-resistance operation and a high-resistance operation in a memory device composed of 1T1R memory cells in which a resistance change type nonvolatile memory element and a transistor are connected are disclosed. The resistance change type nonvolatile memory element is composed of an insulator film of SiN, SiO2, Gd2O3, etc. and a conductor film of a metal film, an alloy film, a metal compound film, etc. containing a metal element of Cu, Ag, Zr, Al, etc.

[0037] Here, the resistance change type nonvolatile memory element can be set to a desired low-resistance value according to a value of a current driven. Further, when the driven current is limited so that an excess current does not flow into the resistance change type nonvolatile memory element, deterioration of the resistance change type nonvolatile memory element can be suppressed.

[0038] Incidentally, in recent years, resistance change type nonvolatile memory devices such as ReRAM have been actively researched so that a high-speed rewrite operation and a read operation can be performed compared to a flash memory, which has been mainstream as a nonvolatile memory device in the past. Further, although the number of rewrite times of the flash memory has been about 100,000 times in the past, with the progress of miniaturization and large capacity, the number of rewrite times has decreased to about several thousand times, and in this regard, ReRAM having a high rewrite performance is expected as a nonvolatile memory device to replace the flash memory.

[0039] However, the disclosure regarding the conventional resistance change type nonvolatile memory device is a method of setting the resistance change type nonvolatile memory element to a desired resistance value, or suppressing damage or deterioration of the resistance change type nonvolatile memory element by current limitation through a rewrite operation of the resistance change type nonvolatile memory element so that an excess current is not applied, and thus, a problem of giving consideration to both expansion of an operation window of a cell current between a low-resistance state and a high-resistance state for realizing stable operation and a high number of rewrite times is not disclosed, nor is it overcome.

[0040] Therefore, an object of the present disclosure is to provide a resistance change type nonvolatile memory device and a write method thereof capable of expanding an initial operation window and suppressing deterioration of the operation window caused by a multiple rewrite operation.

[0041] To solve the above problems, a resistance change type nonvolatile storage device of one embodiment of the present disclosure includes a resistance change element which can reversibly change between a high-resistance state and a low-resistance state, and a current supply circuit which supplies a low-resistance change current for changing the resistance change element from the high-resistance state to the low-resistance state to the resistance change element, a current waveform of the low-resistance change current has a first period and a second period which follows the first period on a time axis, the current supply circuit 24 applies a first current to the resistance change element in the first period and applies a second current smaller than the first current to the resistance change element in the second period, the first current at the end of the first period is not zero, and the second current at the start of the second period is not zero.

[0042] Thus, the initial operation window can be expanded, and deterioration of the operation window caused by multiple rewriting operations can be suppressed.

[0043] (Embodiment)

[0044] Hereinafter, embodiments will be specifically described with reference to drawings.

[0045] Note that each of the embodiments described below shows a general or specific example. Numerical values, shapes, materials, positions of constituent elements, connection modes of the constituent elements, steps, orders of steps, and the like shown in the following embodiments are examples, and are not intended to limit the present disclosure. In addition, the constituent elements in the following embodiments that are not described in the independent technical solutions of the embodiments of the present disclosure are described as arbitrary constituent elements. The embodiments of the present disclosure are not limited to the current independent technical solutions, and can be expressed by other independent technical solutions.

[0046] [1. Outline structure example]

[0047] Figure 1A is a diagram showing a structure example of main parts of the resistance change type nonvolatile storage device 2 in the embodiment. This diagram shows circuits related to a low-resistance write operation of changing the resistance change type nonvolatile storage element from a high-resistance state to a low-resistance state as a main structure of the present disclosure. Furthermore, in this diagram, circuits related to a high-resistance write operation which are not main parts of the present disclosure are omitted. The resistance change type nonvolatile storage device 2 shown in this diagram includes a storage unit 3, a LRization BL selection switch 13, a LRization SL selection switch 14, and a current waveform control circuit 24.

[0048] The memory cell 3 has a resistance change type nonvolatile memory element RSE and a memory cell transistor 1 connected in series. In addition, the memory cell 3 of the drawing is illustrated as one memory cell in a memory array composed of a plurality of memory cells 3 arranged in a matrix shape. Hereinafter, the resistance change type nonvolatile memory element RSE is sometimes referred to simply as a resistance change element RSE.

[0049] The resistance change element RSE is an element capable of reversibly changing to a high resistance state and a low resistance state, and functions as a read / write memory element by making the high resistance state and the low resistance state correspond to the binary of a number. One end of the resistance change type nonvolatile memory element RSE is connected to the source S of the memory cell transistor 1, and the other end is connected to the bit line BL.

[0050] The memory cell transistor 1 has a drain D, a source S, and a gate G. The drain D is connected to the source line SL. The gate G is connected to the memory cell gate terminal MG. The source S is connected to one end of the resistance change element RSE. In addition, the drain and the source of the transistor can be located on either side with the gate in between, but in the present specification, the side connected to the resistance change type nonvolatile memory element RSE is defined as the source S.

[0051] During the low resistance write operation, the voltage VwL illustrated in the drawing is applied to the memory cell gate MG. Thereby, the memory cell transistor 1 becomes in an on state.

[0052] The LRization BL selection switch 13 and the LRization SL selection switch 14 are both in an on state during the low resistance write operation.

[0053] The current waveform control circuit 24 is a current supply circuit that supplies a low resistance element LRIcell, which is a current for changing the resistance change element from a high resistance state to a low resistance state. The low resistance element LRIcell has a down-step current waveform. The current waveform control circuit 24 performs driving that reduces a constant current in a two-stage low resistance write operation by setting the low resistance element LRIcell to a down-step current waveform. This driving is referred to as constant current two-stage reduction driving. According to this driving, in the write operation from the high resistance state to the low resistance state, deterioration of the initial window can be suppressed, and deterioration of the operation window at the time of high cycles (for example, at the time of 100,000 times of rewriting) can be suppressed. For example, even in the case of miniaturization, a stable rewriting operation with high reliability can be achieved for a long period of time.

[0054] Next, a specific example of the current waveform of the low resistance element is described.

[0055] Figure 1B is a graph showing an example of the current waveform of the low resistance element. As Figure 1BAs shown, the down staircase current waveform has a first period and a second period subsequent to the first period. The current supply circuit, i.e., the current waveform control circuit 24 supplies the first constant current to the resistance change element RSE during the first period and supplies the second constant current, which is smaller than the first constant current, to the resistance change element RSE during the second period.

[0056] Therefore, the current supply circuit, i.e., the current waveform control circuit 24 includes the LRization current limiting element 26 as the first constant current source and the LRization current limiting element 27 as the second constant current source. The current waveform control circuit 24 generates the first constant current by superimposing the constant current from the first constant current source and the constant current from the second constant current source during the first period. Further, the current waveform control circuit 24 generates the second constant current by using the constant current from one of the first constant current source and the second constant current source during the second period.

[0057] Further, the current supply circuit, i.e., the current waveform control circuit 24 includes the first switch (i.e., the constant current control switch 31) connected in series to the first constant current source and the second switch (i.e., the constant current control switch 32) connected in series to the second constant current source. The current waveform control circuit 24 supplies the first constant current to the resistance change element RSE by bringing both the first switch and the second switch into the conductive state during the first period. Further, the current waveform control circuit 24 supplies the second constant current to the resistance change element RSE by bringing one of the first switch and the second switch into the non-conductive state and bringing the other into the conductive state during the second period.

[0058] Thus, since a higher current value is supplied to the resistance change element RSE during the first period than during the second period, the initial window can be sufficiently ensured. Since a lower current value is supplied to the resistance change element during the second period than during the first period, the window deterioration during the high cycle can be suppressed. Further, by the operation of the first switch and the second switch, the down staircase current waveform can be easily generated.

[0059] Further, as shown, Figure 1B The first period is shorter than the second period. For example, the first period can be 10% or less of the second period. In this way, the operation window is expanded during the first period in which the first constant current of a higher current is supplied, and the deterioration of the operation window due to the high cycle operation can be suppressed during the second period in which the second constant current of a lower current is supplied. Further, even if the first period is a period of a transient phenomenon of 10% or less of the second period, the operation window can be sufficiently expanded. More specifically, the first period can be 5 nsec or less and the second period can be 50 nsec or more. In this way, the write operation to the low resistance state can be performed at high speed.

[0060] In addition, the second constant current can also be 60% or less of the first constant current. In this way, the write operation to the low-resistance state can be made low power. More specifically, the first constant current can be 125 μA or more, and the second constant current can be 75 μA or less. In this way, the write operation to the low-resistance state can be made low power.

[0061] [1.1 Detailed Configuration Example]

[0062] Next, a more detailed configuration example of the resistance change type nonvolatile memory device 2 will be described.

[0063] Figure 2A is a view showing a detailed configuration example of the resistance change type nonvolatile memory device 2 in the embodiment.

[0064] Figure 2A In the detailed configuration example shown in FIG. 2, the circuit related to the high-resistance write operation that is omitted in FIG. 1 is shown, and a specific example of the current waveform control circuit 24 and the circuit around it is shown. Figure 1A

[0065] Figure 2A The resistance change type nonvolatile memory device 2 shown in FIG. 2 is provided with the memory cell 3, the bit line drive circuit 22b, and the source line drive circuit 23.

[0066] The memory cell 3 is the same as the one already described in FIG. 1, and thus will not be described here. Figure 1A

[0067] The bit line drive circuit 22b is provided with the LRization BL selection switch 13 and the HRization BL selection switch 16, and is connected to the memory cell 3 via the bit line BL.

[0068] The LRization BL selection switch 13 is a switch that connects the ground line and the bit line BL, and becomes an on state in the low-resistance operation.

[0069] The HRization BL selection switch 16 is a switch that connects the HRization power supply terminal 17 and the bit line BL, and becomes an on state in the high-resistance operation. That is, the HRization BL selection switch 16 is a switch for supplying the high-resistance current pulse for high-resisting the memory cell 3 to the memory cell 3.

[0070] The pulse voltage for high-resistance application VdH is applied to the HRization power supply terminal 17.

[0071] ​​The source line drive circuit 23 has the LRization power supply terminal 11, the LRization SL selection switch 14, the HRization SL selection switch 18, the current waveform control circuit 24, and the write pulse width control terminal 33. The source line drive circuit 23 is a circuit that supplies a low-resistance current to the resistance change element RSE. The low-resistance current is not a single rectangular pulse waveform, but has a current waveform that is stepped down.

[0072] A voltage VdL for generating a pulse current for low-resistance is applied to the LRization power supply terminal 11.

[0073] The LRization SL selection switch 14 connects the source line SL and the current supply terminal of the current waveform control circuit 24, and becomes an on state during the low-resistance operation. The current supply terminal of the current waveform control circuit 24 refers to the connection point of the constant current control switch 31 and the constant current control switch 32.

[0074] The HRization SL selection switch 18 is a switch that connects the ground line and the source line SL, and becomes an on state during the high-resistance operation.

[0075] The current waveform control circuit 24 indicates Figure 1A A more specific circuit example of the current supply circuit, that is, the current waveform control circuit 24, is shown. Figure 2A The current waveform control circuit 24 has a constant current control circuit 25, an LRization current limiting element 26, and an LRization current limiting element 27. The current waveform control circuit 24 is composed of the constant current control circuit 25 and the LRization current limiting elements 26 and 27 composed of PMOS transistors.

[0076] The constant current control circuit 25 is composed of a delay circuit 28 having a first delay time (for example, 5 ns) and a NAND circuit 29, an inverter 30, and constant current control switches 31 and 32 composed of PMOS transistors.

[0077] The write pulse width control terminal 33 is connected to the input of the delay circuit 28, the input terminal of the inverter 30, and the gate terminal of the constant current control switch 32. One input terminal of the NAND circuit 29 is connected to the output terminal of the delay circuit 28. The other input terminal of the NAND circuit 29 is connected to the output of the inverter 30. The output terminal of the NAND circuit 29 is connected to the gate terminal of the constant current control switch 31. In addition, the source terminals of the LRization current limiting elements 26 and 27 are connected to the LRization power supply terminal 11, and the drain terminals are connected to the source terminals of the constant current control switches 31 and 32, respectively. In addition, the drain terminals of the constant current control switches 31 and 32 are connected to the LRization SL selection switch 14.

[0078] LR current limiting element 26 is composed of a PMOS transistor, with a clamping voltage Vc1 (<VdL) applied to its gate terminal. LR current limiting element 27 is also composed of a PMOS transistor, with a clamping voltage Vc2 (<VdL) applied to its gate terminal. Therefore, due to the current saturation region characteristics of each LR current limiting element 26 and 27, LR current limiting elements 26 and 27 function as essentially constant current sources, capable of limiting currents to constant currents Iset1 (e.g., 100 μA) and Iset2 (e.g., 75 μA), respectively. Specifically, the transistor sizes and gate voltages are set so that the output currents of LR current limiting elements 26 and 27 can be limited to constant currents Iset1 and Iset2. For example, the PMOS transistors of LR current limiting elements 26 and 27 have the same length, and the ratio of the transistor widths of LR current limiting element 26 and 27 is set to 4:3. Thus, when Vc1 = Vc2, the ratio of Iset1 to Iset2 is 4:3.

[0079] The write pulse width control terminal 33 is a terminal to which a voltage Vi for designating the timing and pulse width of the resistance-lowering current for lowering the resistance (ie, the LR write pulse width) is input.

[0080] The constant current control switch 31 is a first switch connected in series with the LR current limiting element 26 , ie, the first current source, and is turned on for a first period according to the pulse voltage Vc.

[0081] The constant current control switch 32 is a second switch connected in series with the LR current limiting element 27 , ie, the second current source, and is turned on in the second period according to the pulse voltage Vi.

[0082] The circuit composed of the delay circuit 28, the NAND circuit 29 and the inverter 30 is a control circuit for controlling the conduction and non-conduction of the first switch, namely the constant current control switch 31. Figure 2B As shown in FIG. 1 , this circuit generates a negative logic pulse voltage Vc by differentiating the beginning of a negative logic pulse voltage Vi input from a write pulse width control terminal 33. The pulse width of the negative logic pulse voltage Vc determines the first period during which the constant current control switch 31 is turned on. Furthermore, the pulse width of the negative logic pulse voltage Vi determines the second period during which the constant current control switch 32 is turned on.

[0083] In the case of low-resistance change of the memory cell 3, the LR BL selection switch 13 and the LR SL selection switch 14 are controlled to be turned on for a prescribed period, and the HR BL selection switch 16 and the HR SL selection switch 18 are controlled to be turned off. Then, when a voltage pulse Vi of negative logic having a pulse width of a prescribed period (for example, 100 ns) is applied to the write pulse width control terminal 33, as shown in FIG. 8, the output voltage Va of the delay circuit 28 becomes a voltage pulse delayed by 5 ns from the voltage pulse Vi. Further, the output voltage Vb of the inverter 30 becomes a voltage pulse after logical inversion of the voltage pulse Vi. The output voltage Vc of the NAND circuit 29 is a NAND operation result of the output voltage Va and the output voltage Vb, and becomes a voltage pulse of negative logic having a pulse width of a first delay time (for example, 5 ns). Figure 2B

[0084] Thus, at the time of the start of low-resistance change at time t1, the constant current control switches 31 and 32 are activated to be in an on state for 5 ns, and the LR write current is limited to a constant current Isetl (100 μA) and a constant current Iset2 (75 μA) through both the LR-use current limiting elements 26 and 27. At time t2, the constant current control switch 32 is maintained in an on state, and the constant current control switch 31 is turned off. Thereafter, for the remaining period of 95 ns (t2 to t3), only the constant current control switch 31 is in an off state, and the LR write current is reduced to the constant current Iset2 (75 μA) through the LR-use current limiting element 27. In this way, the LR write current flows in the direction from the source line SL side to the bit line BL side while being controlled to be reduced in two stages. Thus, the current waveform control circuit 24 as a low-resistance change operation supplies a low-resistance change current having a downward stair-like current waveform as shown in FIG. 9 to the resistance change element RSE. Figure 2B

[0085] In the case of high-resistance change, the LR BL selection switch 13 and the LR SL selection switch 14 are controlled to be turned off, and the HR BL selection switch 16 and the HR SL selection switch 18 are controlled to be turned on for a prescribed period to flow a current in the direction from the bit line BL to the source line SL.

[0086] Next, a structure example of the resistance change type nonvolatile memory element RSE will be described.

[0087] Figure 3 is an explanatory view showing a circuit symbol and a cross-sectional structure of the resistance change type nonvolatile memory element RSE in the embodiment.

[0088] As shown in FIG. 10, the resistance change type nonvolatile memory element RSE includes a resistance change element RSE, a current waveform control circuit 24, and a write pulse width control terminal 33. Figure 3 ​​As shown in (a), in the resistance change type nonvolatile storage element RSE represented by a circuit symbol, a terminal on the side connected to the source S of the storage cell transistor 1 is set as a terminal A, and a terminal connected to the bit line BL is set as a terminal B.

[0089] Figure 3 The resistance change type nonvolatile storage element 3000a shown in (b) shows a structure before molding after manufacturing of the resistance change type nonvolatile storage element RSE.

[0090] The resistance change type nonvolatile storage element 3000a has a first electrode 81 (lower electrode) corresponding to the terminal A side, a second electrode 84 (upper electrode) corresponding to the terminal B side, and a resistance change layer 85 composed of a transition metal oxide of an oxygen deficiency type. The resistance change layer 85 is composed of a first transition metal oxide layer 82 composed of a transition metal oxide of an oxygen deficiency type and a second transition metal oxide layer 83 composed of a transition metal oxide having a smaller degree of oxygen deficiency than the first transition metal oxide layer 82, by laminating them.

[0091] Figure 3 The resistance change type nonvolatile storage element RSE shown in (c) shows a structure after molding. By applying an electric stress to the resistance change type nonvolatile storage element 3000a before molding, a minute filament 86 that becomes a conductive path is formed in a partial region of the second transition metal oxide layer 83. An oxidation-reduction reaction occurs in this minute filament 86, and the resistance value changes, whereby a resistance change phenomenon appears. Hereinafter, the resistance change operation explained in the present disclosure is an operation based on the structure of the resistance change type nonvolatile storage element RSE after molding.

[0092] In the present embodiment, as one example thereof, the first transition metal oxide layer 82 and the second transition metal oxide layer 83 use the same transition metal, and are composed of a first tantalum oxide layer (hereinafter referred to as a first Ta oxide layer) of an oxygen deficiency type as the first transition metal oxide layer 82 and a second tantalum oxide layer (hereinafter referred to as a second Ta oxide layer) as the second transition metal oxide layer 83, by laminating them. When the first Ta oxide layer is denoted as TaOx and the second Ta oxide layer is denoted as TaOy, x < y. The film thickness of the second Ta oxide layer is preferably 1 nm or more and 10 nm or less. Further, in the present embodiment, the first electrode 81 is composed of laminating titanium nitride (TiN) and tantalum nitride (TaN), and the second electrode 84 is composed of containing a noble metal material, for example, iridium (Ir).

[0093] Oxygen-deficient transition metal oxides are oxides with a lower oxygen content (atomic ratio: the ratio of oxygen atoms to the total number of atoms) than oxides with stoichiometric compositions. Generally, oxides with stoichiometric compositions are insulators or have very high electrical resistance. For example, when the transition metal is Ta, the stoichiometric oxide composition is Ta2O5, and the ratio of Ta to O atoms (O / Ta) is 2.5. Therefore, in oxygen-deficient Ta oxide, the atomic ratio of Ta to O is greater than 0 and less than 2.5.

[0094] Here, the oxygen content of the second Ta oxide layer as the second transition metal oxide layer 83 is higher than the oxygen content of the first Ta oxide layer as the first transition metal oxide layer 82. In other words, the oxygen deficiency of the second Ta oxide layer is less than that of the first Ta oxide layer. The so-called oxygen deficiency refers to the ratio of oxygen that is insufficient in each transition metal relative to the amount of oxygen that constitutes the oxide of its stoichiometric composition. For example, when the transition metal is tantalum (Ta), the stoichiometric oxide composition is Ta2O5, so it can be expressed as TaO 2.5 .TaO 2.5 The oxygen deficiency is 0%. For example, TaO 1.5 The oxygen deficiency degree of an oxygen-deficient tantalum oxide is (2.5-1.5) / 2.5 = 40%. The oxygen content refers to the ratio of oxygen atoms to the total number of atoms constituting the transition metal oxide. The oxygen content of Ta2O5, which is the ratio of oxygen atoms to the total number of atoms (O / (Ta+O)), is 71.4 atm%. Therefore, the oxygen content of oxygen-deficient tantalum oxide is greater than 0 and less than 71.4 atm%.

[0095] The metal constituting the resistance change layer 85 can also use a transition metal other than tantalum, or a portion of a metal. As the transition metal, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), or the like can be used, and as the metal, aluminum (Al), or the like can be used. The transition metal can take a variety of oxidation states, and thus different resistance states can be achieved through redox reactions. For example, in the case of using hafnium oxide, in the case where the composition of the first hafnium oxide layer as the first transition metal oxide layer 82 is set to HfOx, x is 0.9 or greater and 1.6 or less, and in the case where the composition of the second hafnium oxide layer as the second transition metal oxide layer 83 is set to HfOy, y is greater than the value of x, it is confirmed that the resistance value of the resistance change layer 85 is stably and rapidly changed. In this case, the film thickness of the second hafnium oxide layer is preferably 3 nm or greater and 4 nm or less. Further, in the case of using zirconium oxide, it is confirmed that if x is 0.9 or greater and 1.4 or less in the case where the composition of the first zirconium oxide layer as the first transition metal oxide layer 82 is set to ZrOx, and y is greater than the value of x in the case where the composition of the second zirconium oxide layer as the second transition metal oxide layer 83 is set to ZrOy, the resistance value of the resistance change layer 85 is stably and rapidly changed. In this case, the film thickness of the second zirconium oxide layer is preferably 1 nm or greater and 5 nm or less.

[0096] Further, in the above example, the resistance change layer 85 is provided in a two-layer stacked structure, but can also be constituted by a single-layer resistance change layer of a transition metal oxide layer of an oxygen deficiency type.

[0097] The second electrode 84 connected to the second transition metal oxide layer 83 having a smaller degree of oxygen deficiency is constituted by, for example, platinum (Pt), iridium (Ir), palladium (Pd), or the like having a higher standard electrode potential than the transition metal constituting the second transition metal oxide layer 83 and the material constituting the first electrode 81. By adopting such a constitution, a redox reaction selectively occurs in the second transition metal oxide layer 83 in the vicinity of the interface between the second electrode 84 and the second transition metal oxide layer 83, and thus a stable resistance change phenomenon can be achieved.

[0098] Further, as the resistance change layer 85, a stacked structure of a first transition metal oxide layer 82 constituted by a first transition metal and a second transition metal oxide layer 83 constituted by a second transition metal different from the first transition metal can also be used. The degree of oxygen deficiency of the second transition metal oxide layer is smaller than that of the first transition metal oxide layer. In other words, the resistance value of the second transition metal oxide layer 83 is higher than that of the first transition metal oxide layer 82.

[0099] In addition, in a case where the first transition metal and the second transition metal use mutually different materials, it is preferable that the standard electrode potential of the second transition metal be lower than the standard electrode potential of the first transition metal. For example, by using an oxygen-deficient tantalum oxide in the first transition metal oxide layer 82 and using a titanium oxide (TiO2) in the second transition metal oxide layer 83, stable resistance change operation can be achieved. Titanium (standard electrode potential = -1.63 eV) is a material having a lower standard electrode potential than tantalum (standard electrode potential = -0.6 eV). By disposing an oxide of a metal having a lower standard electrode potential than the first transition metal oxide layer 82 in the second transition metal oxide layer 83, redox reactions are more likely to occur in the second transition metal oxide layer 83.

[0100] In the above structure, with the first electrode 81 as a reference, when a positive voltage is applied to the second electrode 84, oxygen ions included in the first transition metal oxide layer 82 move into the filament 86, and thus oxidation reactions occur. As a result, it is considered that the resistance of the filament 86 increases and becomes a high resistance state.

[0101] On the other hand, with the first electrode 81 as a reference, when a negative voltage is applied to the second electrode 84, by pressing the oxygen ions in the filament 86 toward the first transition metal oxide layer 82 side, reduction reactions occur in the filament 86. As a result, it is considered that the resistance of the minute filament 86 decreases and becomes a low resistance state.

[0102] Meanwhile, the resistance value of the second transition metal oxide layer 83 having a higher resistance value than the first transition metal oxide layer 82 is formed to be, for example, several hundred MΩ to 1 GΩ. On the other hand, even when a high resistance state is obtained by oxidation reactions, the resistance value of the filament 86 is about several hundred kΩ to several MΩ.

[0103] Therefore, the voltage applied between the first electrode 81 and the second electrode 84 is divided by the first transition metal oxide layer 82 and the second transition metal oxide layer 83, and the higher the resistance value, the higher the second transition metal oxide layer 83 side, and the current path accompanying this is not uniform in the second transition metal oxide layer 83. The current is concentrated in the region of the filament 86 having a lower resistance value in the second transition metal oxide layer 83. Therefore, stable and continuous current and voltage control of the resistance change operation occurring in the filament 86 becomes important in the case of the resistance change type nonvolatile storage element operating by the filament model.

[0104] [2. Evaluation Experimental Results]

[0105] Next, the results of experiments performed in order to evaluate the resistance change type nonvolatile storage device 2 of Figure 2A will be described. In the experiments, in addition to the resistance change type nonvolatile storage device 2 of Figure 2A , as a comparative example,Figure 13 The resistance change type nonvolatile memory device shown is also an experimental object.

[0106] First, the resistance change type nonvolatile memory device of the comparative example is described.

[0107] Figure 13 is a view showing the structure of the resistance change type nonvolatile memory device as the comparative example. This comparative example is a circuit similar to the resistance change type nonvolatile memory device of Patent Document 1, and shows the circuit of the 1T1R memory cell and its periphery. Figure 13 (a) of shows the high-resistance change operation. The downward thick arrow line shows the current HRIcell that is passed to the resistance change type nonvolatile memory element RSE. In addition, Figure 13 (b) of shows the low-resistance change operation. The upward thick arrow line shows the current LRIcell that is passed to the resistance change type nonvolatile memory element RSE.

[0108] Figure 13 The resistance change type nonvolatile memory device of shows a difference from Figure 2A compared to the resistance change type nonvolatile memory device of the main difference is that the source line drive circuit 22a is provided instead of the source line drive circuit 23.

[0109] The source line drive circuit 22a is a circuit that passes a constant current rectangular wave pulse to the memory cell 3 at a time in the low-resistance change operation.

[0110] In the case of the high-resistance change, the LR change BL selection switch 13 and the LR change SL selection switch 14 are controlled to be off, the HR change BL selection switch 16 and the HR change SL selection switch 18 are controlled to be on for a prescribed period, and the current HRIcell is caused to flow through the memory cell 3 in the direction from the bit line BL to the source line SL.

[0111] In the case of the low-resistance change, the HR change BL selection switch 16 and the HR change SL selection switch 18 are controlled to be off, the LR change BL selection switch 13 and the LR change SL selection switch 14 are controlled to be on for a prescribed period, and the current LRIcell is caused to flow through the memory cell 3 in the direction from the source line SL to the bit line BL.

[0112] This evaluation circuit can evaluate the memory cell 3 in 1-bit units by supplying prescribed voltages to the respective terminals of the source line drive circuit 22a and the bit line drive circuit 22b, but in the case of constituting and evaluating an array of memory cells, the source line drive circuit 22a and the bit line drive circuit 22b are constituted in a form that is common to a plurality of memory cells 3. In this evaluation, a plurality of memory cells can be selectively evaluated, and rewriting evaluation can be performed in 1-bit units or in the array unit of memory cells.

[0113] Further, the LR BL selection switch 13, the LR SL selection switch 14, the HR BL selection switch 16, and the HR SL selection switch 18 are general selection circuits composed of transistors, but the transistor size, the transistor structure, and the gate voltage of each of these are set so that the voltage drop at each of these is as small as possible and the current is not limited (regulated).

[0114] In both the high-resistance operation and the low-resistance operation, the voltage VdL is stably supplied to the LR power supply terminal 11, the voltage Vclamp (< VdL) is stably supplied to the LR clamp control terminal 12, and the voltage VdH is stably supplied to the HR power supply terminal 17.

[0115] In the high-resistance operation, the voltage VwH is supplied to the storage cell gate terminal MG of the storage cell transistor 1, and the HR BL selection switch 16 and the HR SL selection switch 18 are controlled to be on for 100 ns. At this time, the LR BL selection switch 13 and the LR SL selection switch 14 are controlled to be off. By performing such a high-resistance operation, the current HRIcell flows from the bit line BL side to the source line SL side in the resistance change type nonvolatile storage element RSE, and the resistance change of the high-resistance operation is performed.

[0116] In the low-resistance operation, in the 1T1R storage cell 3 composed of the resistance change type nonvolatile storage element RSE and the storage cell transistor 1, the voltage VwL is supplied to the storage cell gate terminal MG of the storage cell transistor 1, and the LR BL selection switch 13 and the LR SL selection switch 14 are controlled to be on for 100 ns. At this time, the HR BL selection switch 16 and the HR SL selection switch 18 are controlled to be off. By performing such a low-resistance operation, the current LRIcell flows from the source line SL side to the bit line BL side in the resistance change type nonvolatile storage element RSE, and the resistance change of the low-resistance operation is performed. At this time, the constant current source composed of the PMOS transistor 10 can limit the current to the constant current Iset, and supply the gate voltage of the storage cell transistor 1 in such a manner that the impedance of the storage cell transistor 1 is sufficiently low. Therefore, the current Imos flowing in the storage cell transistor 1 and the current LRIcell flowing in the resistance change type nonvolatile storage element RSE are limited to Iset.

[0117] Next, the rewriting operation for evaluation performed in the experiment will be described.

[0118] Figure 4 is a diagram showing the processing flow of the experiment including multiple rewriting processes. The processing flow of this diagram is the same as that of the 1T1R storage cell 3 shown in Figure 13 the comparative example of the resistance change type nonvolatile storage device of Figure 2AThe resistance change type nonvolatile memory device 2 of each of the embodiments is described below.

[0119] In Figure 4 , first, a low resistance operation and a cell current measurement of a plurality of evaluation target bits (for example, about 1 kb) in the memory cell array are performed (S41, S42). Subsequently, a high resistance operation and a cell current measurement of the evaluation target bits are performed (S43, S44). The resistance change operation is repeated 100,000 times and ends (S45). The cell current measurement is to confirm whether the memory cell 3 can be brought to a desired resistance state by the resistance change operation, and the resistance change type nonvolatile memory element RSE applies a low voltage free from disturbance, and a current value is measured. Figure 14 is a graph showing a driving condition of the resistance change type nonvolatile memory device in the embodiment. The driving condition is applied to Figure 13 , and Figure 2A the resistance change type nonvolatile memory device 2.

[0120] In the low resistance operation and the high resistance operation, the voltage VdL of the LRization power supply terminal 11 is stably provided with 2.8 V, the voltage Vclamp of the LRization clamp control terminal 12 is stably provided with an intermediate voltage of 1.73 V, and the voltage VdH of the HRization power supply terminal 17 is stably provided with 1.7 V. Here, in order to constitute a constant current source of 175 μA, the voltage Vclamp is provided with 1.73 V, but by changing the voltage Vclamp, the set current value of the constant current source can be changed.

[0121] For example, in Figure 13 , in a case where a constant current source of 75 μA is desired to be constituted, the voltage Vclamp is provided with 1.86 V. Also, in the low resistance operation, the memory cell gate terminal MG of the memory cell transistor 1 is provided with 3.0 V by the voltage VwL, and the LRization BL selection switch 13 and the LRization SL selection switch 14 are subjected to on control for a period of 100 ns. The HRization BL selection switch 16 and the HRization SL selection switch 18 are set to off control.

[0122] In the high resistance operation, the memory cell gate terminal MG of the memory cell transistor 1 is provided with 1.8 V by the voltage VwH, and the HRization BL selection switch 16 and the HRization SL selection switch 18 are subjected to on control for a period of 100 ns. The LRization BL selection switch 13 and the LRization SL selection switch 14 are set to off control.

[0123] Also, in Figure 2AIn the low resistance change operation in FIG. 6, Vcl and Vc2 are both 1.73 V. The PMOS transistor lengths of the low resistance change current limiting elements 26 and 27 are the same, and the transistor width ratio of the low resistance change current limiting element 26 to the low resistance change current limiting element 27 is set to 4 to 3. As a result, the low resistance change current limiting element 26 generates a first constant current value of 100 μA, and the low resistance change current limiting element 27 generates a second constant current value of 75 μA.

[0124] Next, the evaluation results will be described.

[0125] First, the tendency will be described using a part of the measurement data of the resistance change in the first 100,000 times of use.

[0126] Figure 5 is a normal expectation value dot plot of the cell current distribution of the 1T1R memory cell of the comparative example of Figure 13

[0127] Figure 5 (a) of FIG. 7 is a normal expectation value dot plot of the cell current distribution (about 1 kb) of the high resistance state (HR) and the low resistance state (LR) of the initial state of the stable operation after molding, when the set current value of the constant current source is set to 75 μA. The white squares represent the cell current of the high resistance state, and the white circles represent the cell current of the low resistance state.

[0128] Figure 5 (b) of FIG. 7 is a normal expectation value dot plot of the cell current distribution (about 1 kb) of the high resistance state (HR) and the low resistance state (LR) of the initial state of the stable operation after molding, when the set current value of the constant current source is set to 175 μA. The white squares represent the cell current of the high resistance state, and the white circles represent the cell current of the low resistance state.

[0129] Figure 5 (c) of FIG. 7 is a transition of the normal expectation value dot plot of the cell current distribution (about 1 kb) of the high resistance state (HR) and the low resistance state (LR) of the initial state of the stable operation after molding, and after 100,000 times of rewriting, when the set current value of the constant current source is set to 175 μA. The white squares represent the cell current of the high resistance state of the initial state, the white circles represent the cell current of the low resistance state of the initial state, the black diamonds represent the cell current of the low resistance state after 100,000 times, and the black triangles represent the cell current of the high resistance state after 100,000 times.

[0130] ​In a memory device using a variable resistance nonvolatile memory element, a sense amplifier circuit reads the written low-resistance or high-resistance state to determine whether the data is "1" or "0." To achieve this, a difference (operating window) must exist between the minimum cell current value in the low-resistance state and the maximum cell current value in the high-resistance state.

[0131] like Figure 5 As shown in (a), when the LR write current is set to a low current of 75 μA, the LR cell current decreases, the operating window becomes smaller than the specified value and becomes very small, making it difficult to perform stable data discrimination by the readout amplifier circuit.

[0132] exist Figure 5 In (b), the LR write current is increased to 175 μA, thereby increasing the LR cell current. As a result, a sufficient operation window can be ensured.

[0133] However, if Figure 5 As shown in (c), when the number of rewrites is increased to 100,000 times, the degradation of the resistance change action caused by the rewrite (the deviation of the cell current distribution increases) becomes obvious, resulting in a high-resistance defective bit or a current reduction bit at the bottom of the LR cell current distribution, and the action window essentially disappears.

[0134] Figure 6 In the embodiment of the present disclosure Figure 2A Figure 1 shows the normal expected value plot of the cell current distribution of a 1T1R memory cell. The plot shows the transition of the cell current distribution (approximately 1 kb) in the initial state, the high resistance state (HR), and the low resistance state (LR) after 100,000 rewrite cycles, using the normal expected value plots of the constant current source, when the set current value was reduced from a total of 175 μA (current application time 5 ns) to 75 μA (current application time 95 ns). White squares represent the cell current in the initial high resistance state, white circles represent the cell current in the initial low resistance state, black diamonds represent the cell current in the low resistance state after 100,000 cycles, and black triangles represent the cell current in the high resistance state after 100,000 cycles.

[0135] By the high current short pulse (constant current 175 μA, 5 ns) of the 1st period, the pulse width is shorter than the conventional write current pulse (constant current 175 μA, pulse width 100 ns), the movement of oxygen ions from the filament 86 to the 1st Ta oxide layer as the 1st transition metal oxide layer 82, that is, the reduction reaction becomes insufficient, the central value of the LR cell current decreases, but it is also possible to ensure the initial window, by the low current pulse (constant current 75 μA, 95 ns) of the subsequent 2nd period, the filament 86 is annealed under the application of low current, the voids (defects) formed by the movement of oxygen ions from the filament 86 are uniformized / stabilized, it is possible to significantly reduce the degradation of the resistance change operation caused by the increase in the number of rewriting (increase in the deviation of the cell current distribution), it is possible to achieve stable and continuous operation of rewriting.

[0136] As described above, by performing the constant current two-stage reduction write of the present disclosure, it is possible to achieve both ensuring the initial window by the high current short pulse and suppressing the rewriting degradation by the low current pulse, and stabilization.

[0137] [3. Structure example of memory array including resistance change type nonvolatile storage device]

[0138] Next, as an embodiment of the present disclosure, the overall structure of a resistance change type nonvolatile storage device in which the resistance change element RSE described above and the 1T1R memory cell using the constant current two-stage reduction drive of the present disclosure are arranged in a matrix shape is described.

[0139] (Embodiment 1)

[0140] Figure 7 is a block diagram showing a structure example of a resistance change type nonvolatile storage device of an embodiment of the present disclosure.

[0141] The resistance change type nonvolatile storage device 4000 of the present embodiment has a memory main part 300 on a semiconductor substrate, the memory main part 300 has a memory array 301, a column selection circuit 302, a row selection circuit 303, a write circuit 304 for performing the writing of data, and a readout circuit 305 that detects the amount of current flowing through a selection bit line and determines whether the stored data is "1" or "0".

[0142] The peripheral circuit part 306 has a voltage generation circuit 308, a word line voltage switching circuit 316, an address input circuit 317, and an input / output circuit 318, and has a control circuit 307 that controls the operation of the memory main part 300 and the peripheral circuit part 306 based on a control signal input from the outside.

[0143] The voltage generation circuit 308 includes a low-resistance word line power supply 309, a high-resistance word line power supply 310, a read word line power supply 311, a low-resistance clamping power supply 312, a low-resistance pulse power supply 313, a high-resistance pulse power supply 314, and a pre-charge power supply 315.

[0144] These power supplies generate the voltages shown in the table below as inputs from the external power supply VDD, and the values shown in the table below are based on the voltages explained in the low-resistance constant current two-stage reduction type drive in the low-resistance state. Figure 14 Figure 1A

[0145] In addition, the output VwL of the low-resistance word line power supply 309, the output VwH of the high-resistance word line power supply 310, and the output Vr of the read word line power supply 311 are supplied to the word line voltage switching circuit 316. One of the output VwL through the low-resistance write instruction signal WEL, the output VwH through the high-resistance write instruction signal WEH, and the output Vr through the read instruction signal RE is selected as the output VRD of the word line voltage switching circuit 316, and is supplied to the row selection circuit 303.

[0146] The output Vc1 / Vc2 of the low-resistance clamping power supply 312, the output VdL of the low-resistance pulse power supply 313, and the output VdH of the high-resistance pulse power supply 314 are supplied to the write circuit 304. The output VPR of the pre-charge power supply 315 is supplied to the column selection circuit 302 and the write circuit 304. Each of the power supply circuits is configured by a general step-down circuit that generates each of the prescribed voltages by stepping down the external power supply VDD, and detailed explanation is omitted. In addition, each of the power supply circuits has a general trimming function to be able to trim the output voltage value in order to reflect manufacturing variations and the like, or to be set to an optimal operating point.

[0147] In addition, depending on the voltage value of the external power supply VDD, one or all of these power supply circuits can be configured to generate by stepping up the external power supply VDD.

[0148] In addition, one or all of these power supply circuits do not necessarily need to be provided within the resistance change type nonvolatile memory device 4000, and can be configured to supply prescribed voltages as external power supplies.

[0149] The address input circuit 317 receives an address signal input from the outside, and instructs the specified memory cell 3 of the memory array 301.

[0150] ​​The input / output circuit 318 accepts a data input signal Din inputted from the outside to the DQ terminal, supplies it to the memory main body 300 as a write signal, or accepts an output signal read from the memory main body 300, and outputs the output signal Dout to the outside via the DQ terminal.

[0151] In the memory array 301, the memory cells 3 explained above as the basis data of the present disclosure are arranged in a matrix of m rows and n columns. Here, the upper left is denoted as M11, and each memory cell is denoted as M11, M21,..., Mm1 in the row direction, and as M11, M12,..., M1n in the column direction.

[0152] A plurality of word lines WL1, WL2,..., WLm outputted in the row direction from the row selection circuit 303 are connected to the memory cell gate terminal MG of each memory cell 3.

[0153] A plurality of bit lines BL1, BL2,..., BLn and a plurality of source lines SL1, SL2,..., SLn outputted in the column direction from the column selection circuit 302 are alternately arranged in parallel, and are connected to the bit line BL and the source line SL of each memory cell 3.

[0154] The column selection circuit 302 and the write circuit 304 are arranged on the upper side and the lower side of the memory array 301, and control writing from both ends of the bit lines BL1, BL2,..., BLn and the source lines SL1, SL2,..., SLn.

[0155] This is arranged on both sides in order to reduce the influence of IR drop (IR-Drop) due to the wiring resistance of the bit lines and the source lines, but in a case where the influence of IR drop is small due to the number of arranged memory cells 3 and the wiring resistance value of the applied manufacturing process, it can be arranged on only the lower side, for example.

[0156] The writing operation to the memory cell 3 is the same as in the case of explaining the basis data of the present disclosure, and in a case where the bit line BL is set to a low potential and the source line SL is set to a high potential, low resistance is performed, and in a case where the bit line BL is set to a high potential and the source line SL is set to a low potential, high resistance is performed.

[0157] Figure 8 This is a diagram showing a circuit example of the write circuit 304.

[0158] The source line write circuit 330 and the bit line write circuit 336 are provided.

[0159] The source line write circuit 330 is connected to the source line input terminal SLin via the current waveform control circuit 24 and the PMOS transistor 333. The current waveform control circuit 24 inputs the output VdL of the pulse power supply 313 for medium and low resistance to the LR power supply terminal 11, and inputs the output Vc1 / Vc2 of the low resistance clamping power supply 312 to the gate terminals of the LR current limiting elements 26 and 27, and inputs the voltage pulse Vi for low resistance output from the control circuit 307 to the write pulse width control terminal 33. The PMOS transistor 333 is connected in series with the shared drain terminal of the constant current control switches 31 and 32 located therein, and uses the output of the inverter 332 with the low resistance write indication signal WEL as input as the gate input. The source line input terminal SLin is also connected to the following structures: NMOS transistor 334, with the high resistance write indication signal WEH as the gate input and the source being grounded; PMOS transistor 335, with the output VPR of the precharge power supply 315 as the source input and the precharge indication signal NPR as the gate input; and NMOS transistor 342, with the read indication signal RE as the gate input and the source being grounded.

[0160] The bit line write circuit 336 is composed of the following structure: a PMOS transistor 338, in which the output VdH of the high resistance pulse power supply 314 is connected to the source input, the output of the inverter 337 with the high resistance write indication signal WEH as input is connected to the gate input, and the bit line input terminal Blin is connected to the drain; an NMOS transistor 339, in which the bit line input terminal Blin is connected to the drain input, the low resistance write indication signal WEL is connected to the gate input, and the source is connected to the ground; a PMOS transistor 340, in which the precharge indication signal NPR is connected to the gate input, the output VPR of the precharge power supply 315 is connected to the source input, and the bit line input terminal Blin is connected to the drain input; and an NMOS transistor 341, in which the read indication signal RE is connected to the gate input, the bit line input terminal Blin is connected to the drain input, and the bit line output signal Blout is connected to the source.

[0161] The bit line output signal BLout is connected to the readout circuit 305 .

[0162] in addition, Figure 1A In the resistance change non-volatile memory device, the LR-SL selection switch 14 corresponds to the PMOS transistor 333, the LR-BL selection switch 13 corresponds to the NMOS transistor 339, and the HR-BL selection switch 16 corresponds to the PMOS transistor 338, and the HR-SL selection switch 18 corresponds to the NMOS transistor 334.

[0163] Figure 9 302 is a diagram showing a circuit example of the column selection circuit 302 .

[0164] The bit line selection circuit 350 includes an NMOS transistor 351 having one of a source and a drain connected to the bit line BLi (i = 1 to n) and the other connected to a bit line input terminal Blin, and a PMOS transistor 352 having one of a source and a drain connected to the same bit line BLi (i = 1 to n) and the other connected to the output VPR of the precharge power supply 315. The gates of both transistors are connected to the same column selection signal CLi (i = 1 to n).

[0165] The source line selection circuit 353 includes an NMOS transistor 354 having one of a source and a drain connected to the source line SLi (i = 1 to n) paired with the bit line BLi and the other connected to a source line input terminal SLin, and a PMOS transistor 355 having one of a source and a drain connected to the same source line SLi (i = 1 to n) and the other connected to the output VPR of the precharge power supply 315. The gates of both transistors are connected to the same column selection signal CLi (i = 1 to n).

[0166] Further, the bit line selection circuit 350 and the source line selection circuit 353 are arranged alternately.

[0167] Of the N column selection signals CLi (i = 1 to n), only one selected is set to a high level and the others are set to low levels. Only the selected pair of the bit line BLi and the source line SLi is connected to the bit line input terminal Blin and the source line input terminal SLin, and the remaining ones are precharged to VPR as non-selected bit lines BLi and source lines SLi.

[0168] Further, the high level of the column selection signal CLi (i = 1 to n) is the external power supply VDD, but it is also possible to provide a higher voltage only to the output of the signal or form a structure paired with a PMOS transistor so that the influence of the threshold voltage of the NMOS transistor 351 and the NMOS transistor 354 does not occur.

[0169] Figure 10 FIG. 4 is a diagram showing a circuit example of the row selection circuit 303.

[0170] The row selection circuit 303 includes a decoding circuit 370 that generates a decoding signal for specifying a selected row based on an address selection signal generated by the address input circuit 317, and a word line driver 371 connected to the decoding signal. The word line driver 371 has the number of word lines (m) as another input, and outputs the voltage VwL to the word line WLj (j = 1 to m) corresponding to the selected row during low-resistance writing, the voltage VwH to the word line WLj (j = 1 to m) corresponding to the selected row during high-resistance writing, and the voltage Vr to the word line WLj (j = 1 to m) corresponding to the selected row during readout operation.

[0171] The operation of the resistance change type nonvolatile memory device 4000 thus configured will be described with reference to the timing chart shown in FIG. 6. Figure 11

[0172] Here, the case where the resistance change type nonvolatile memory element is in the high-resistance state is defined as data "0", and the case where it is in the low-resistance state is defined as data "1". In addition, the amplitude level of the control signal to which no voltage symbol is attached has a high level of the external power supply VDD and a low level of 0 V.

[0173] An example of the operation for four periods, in which period Tl is low-resistance writing to the memory cell Ml l, period T2 is high-resistance writing to the memory cell M12, period T3 is readout of the low-resistance state of the memory cell Ml l, and period T4 is readout of the high-resistance state of the memory cell M12, will be described.

[0174] First, the low-resistance writing operation to the memory cell Ml l in period Tl will be described.

[0175] Initially, all the word lines WLj (j = 1 to m) and the column selection signals CLi (i = 1 to n) are 0 V, and any memory cell is in a non-selected state.

[0176] On the other hand, the precharge instruction signal NPR is a negative logic signal, and indicates precharge at 0 V. As a result, all the bit lines BLi, the source lines SLi (i = 1 to n), and the bit line input terminal BLin and the source line input terminal SLin are precharged to the voltage VPR.

[0177] Further, the input / output DQ terminal is set to the high level, and written as data "1".

[0178] Next, the precharge instruction signal NPR is set to the high level, and the precharge state of the bit line input terminal BLin and the source line input terminal SLin is released.

[0179] ​Next, accepting the selection indication of the address input circuit 317, the selection word line WL1 and the column selection signal CL1 as the selection column are set to the high level. At this time, the voltage of the word line WL1 is VwL for the low resistance writing. Further, the bit line BL1 and the source line SL1 as the selection column are released from the precharge, and are connected to the bit line input terminal BLin and the source line input terminal SLin. On the other hand, the non-selection bit lines and the non-selection source lines other than these are maintained in the precharge.

[0180] Next, corresponding to the data "1" writing indication of the input / output DQ terminal, the low resistance writing indication signal WEL is set to the high level for the period of 100 ns, and the voltage pulse Vi of the negative logic is set to the low level, and corresponding to this, the source line input terminal SLin is driven to the high potential side, and the bit line input terminal BLin is driven to the low potential side, and the constant current two-stage reduction low resistance writing operation as the basic data detailed description of the present disclosure is performed to the selection memory cell M11.

[0181] Next, accepting the end of the low resistance writing indication, the selection word line WL1 and the selection column selection signal CL1 are set to 0 V, the memory cell M11 becomes the non-selection state, and the precharge of the bit line BL1 and the source line SL1 is started.

[0182] Then, finally, the precharge indication signal NPR is set to 0 V, the precharge of the bit line input terminal BLin and the source line input terminal SLin is started, and the low resistance writing period is ended.

[0183] Next, the high resistance writing operation to the memory cell M12 of the period T2 is described.

[0184] Initially, all of the word lines WLj (j = 1 ~ m) and the column selection signals CLi (i = 1 ~ n) are 0 V, and any memory cell is in the non-selection state.

[0185] On the other hand, the precharge indication signal NPR is precharge indicated with 0 V, and the bit lines BLi, the source lines SLi (i = 1 ~ n), and the bit line input terminal BLin and the source line input terminal SLin are precharged to the voltage VPR.

[0186] Then, the input / output DQ terminal is set to the low level as the data "0" writing.

[0187] Next, the precharge indication signal NPR is set to the high level, and the precharge state of the bit line input terminal BLin and the source line input terminal SLin is released.

[0188] Next, the selection instruction to the address input circuit 317 is accepted, and the word line WL1 as the selection word line and the column selection signal CL2 as the selection column are set to the high level. At this time, the voltage of the word line WL1 becomes the high resistance writing VwH. Further, the bit line BL2 and the source line SL2 as the selection column are released from the precharge, and are connected to the bit line input terminal BLin and the source line input terminal SLin. On the other hand, the non-selection bit lines and the non-selection source lines other than these are maintained in the precharge.

[0189] Next, in correspondence with the data "0" writing instruction to the input / output DQ terminal, the high resistance writing instruction signal WEH is set to the high level during 100 ns, and the source line input terminal SLin is driven to the low potential side and the bit line input terminal BLin is driven to the high potential side in correspondence with this signal, and the high impedance writing operation as the basis data of the present disclosure is performed to the selected memory cell M12.

[0190] In addition, the cell current of this timing chart indicates the absolute value thereof, and the flow direction is opposite to the period T1.

[0191] Next, in correspondence with the end of the high resistance writing instruction, the selection word line WL1 and the selection column selection signal CL2 are set to 0 V, the memory cell M12 becomes the non-selection state, and the precharge of the bit line BL2 and the source line SL2 is started.

[0192] Then, finally, the precharge instruction signal NPR is set to 0 V, the precharge of the bit line input terminal BLin and the source line input terminal SLin is started, and the high resistance writing period ends.

[0193] Next, the reading operation of the low resistance state of the memory cell M11 in the period T3 is described.

[0194] Initially, all of the word lines WLj (j = 1 to m) and the column selection signals CLi (i = 1 to n) are 0 V, and any memory cell is in the non-selection state.

[0195] On the other hand, the precharge instruction signal NPR is precharge instructed with 0 V, and the bit lines BLi, the source lines SLi (i = 1 to n), and the bit line input terminal BLin and the source line input terminal SLin are precharged to the voltage VPR.

[0196] Next, the precharge instruction signal NPR is set to the high level, and the precharge state of the bit line input terminal BLin and the source line input terminal SLin is released.

[0197] Next, the selection instruction to the address input circuit 317 is accepted, and the word line WL1 as the selection word line and the column selection signal CL1 as the selection column are set to the high level. At this time, the voltage of the word line WL1 becomes Vr for readout. Further, the precharge of the bit line BL1 and the source line SL1 as the selection column is released, and is connected to the bit line input terminal BLin and the source line input terminal SLin. On the other hand, the non-selection bit line and the non-selection source line other than these are maintained in the precharge.

[0198] Next, the readout instruction signal RE is set to the high level during the readout operation period (here, 150 ns is set), the NMOS transistor 342 is turned on, the selection source line SL1 is driven to the low potential side via the source line input terminal SLin, and the NMOS transistor 341 is turned on, and the selection bit line BL1 is connected to the bit line output signal BLout via the bit line input terminal BLin. The bit line output signal BLout is connected to the readout circuit 305, and the data "1" or the data "0" is discriminated according to the amount of current flowing from the bit line BL side to the source line SL side. The storage unit M11 is written in the low resistance state, and more current flows compared with the case of the high resistance state, the readout circuit 305 determines the data "1", and outputs the high level from the input / output DQ terminal.

[0199] Next, the end of the readout instruction is accepted, the selection word line WL1 and the selection column selection signal CL1 are set to 0 V, the storage unit M11 becomes the non-selection state, and the precharge of the bit line BL1 and the source line SL1 is started.

[0200] Finally, the precharge instruction signal NPR is set to 0 V, the precharge of the bit line input terminal BLin and the source line input terminal SLin is started, and the readout operation period ends.

[0201] The readout operation of the storage unit M12 in the high impedance state in the period T4 is the same as the readout operation of the storage unit M12 in the high impedance state in the period T3 except that the selected storage unit M12 is written in the high impedance state unlike the selection column in the period T3, and the current is smaller compared with the case of the low impedance state, the readout circuit 305 determines the data "0" and outputs the low level from the input / output DQ terminal, and thus the detailed description thereof is omitted.

[0202] The above is the description of the operation of the resistance change type nonvolatile storage device 4000, and the case where the non-selection bit line and the non-selection source line are precharged to the prescribed voltage VPR is used Figure 12 The effect thereof is described.

[0203] Figure 12 is a bias chart of the storage unit of the resistance change type nonvolatile storage device in the embodiment.

[0204] Figure 12 The state of the memory cell shown in (a) is a state of a selected memory cell in which low-resistance writing is performed as explained in the present embodiment, which is illustrated by a schematic cross-sectional view, Figure 11 The state of the selected memory cell M11 in the period T1 explained in (b) is equivalent to that.

[0205] The memory cell transistor 402 is composed of a gate electrode 404 which is also a word line on the semiconductor substrate 401, a gate oxide film 405, a drain 406 which is an N-type diffusion layer connected to a source line SL, and a source 407 which is an N-type diffusion layer connected to a lower electrode of the resistance variable nonvolatile memory element RSE, with a bit line BL connected to an upper electrode.

[0206] In the low-resistance writing, the source line SL is applied with a substantially voltage VdL-α (α represents the amount of voltage drop caused by the current limiting elements 26, 27 for LR), the bit line is set to a low voltage of 0 V, and the word line is supplied with a voltage VwL. The memory cell transistor 402 is turned on, a channel 408 is formed, and current flows from the drain 406 to the source 407.

[0207] Generally, as the manufacturing process is refined, the memory cell is also refined, and higher integration can be achieved. In this case, as the planar size of the memory cell transistor 402 is reduced, the thinning of the gate oxide film 405 also progresses, and thus the maximum voltage that can be applied to the gate electrode 404 decreases as the refinement progresses.

[0208] Therefore, control to moderate the electric field applied to the gate oxide film 405 is important for the high reliability of the memory cell.

[0209] In the present embodiment, as the channel 408 is formed in the selected memory cell 400, the electric field between the gate electrode 404 and the channel 408 is substantially applied to the gate oxide film 405. In the case of low-resistance writing, the channel 408 near the source 407, which is lower in voltage, is the highest in the electric field applied to the gate oxide film 405. The bit line BL is 0 V, but the potential of the source 407 rises by the amount of the terminal voltage of the resistance variable nonvolatile memory element RSE (about 1 to 1.2 V or so) due to the current flowing in the resistance variable nonvolatile memory element RSE, and the potential difference between the gate electrode 404 and the channel 408 can be moderated to about 1.8 to 2.0 V or so.

[0210] Figure 12 The state of the memory cell shown in (b) is a state of a non-selected memory cell in the same row as the selected memory cell in which low-resistance writing is performed as explained in the present embodiment, which is illustrated by a schematic cross-sectional view, Figure 11The state of the non-selected memory cell M12 and the like in period T1 described above is equivalent to this. The source line SL and bit line BL of the non-selected column are precharged to voltage VPR (1.1V). Since the variable resistance non-volatile memory element RSE is conductive, the voltage of the source 407 of the N-type diffusion layer also becomes VPR together with the drain 406 of the N-type diffusion layer. At voltage VwL, the gate-source potential and the gate-drain potential of the gate electrode 404 used to select the row become greater than the threshold voltage of the memory cell transistor 402, and the memory cell transistor 402 turns on, forming a channel 411. The voltage of this channel 411 becomes VPR, which is the same as that of the bit line BL and source line SL. Therefore, the potential difference between the gate electrode 404 and the channel 411 can be relaxed to 1.9V.

[0211] on the other hand, Figure 12 The memory cell state shown in (c) of FIG. 1 illustrates the case where the bit line BL and source line SL of the non-selected memory cell in the same row as the selected memory cell to which the low resistance writing is performed are precharged to 0V as is conventionally done. In this case, the voltage of the channel 421 becomes 0V, which is the same as that of the bit line BL and source line SL. The potential difference between the gate electrode 404 and the channel 421 becomes 3.0V, which is higher than the voltage of the gate electrode 404 and the channel 421. Figure 12 The memory cell state of (b) is higher by 1 V or more, which is not preferable when applying a finer process.

[0212] Figure 12 (d) The memory cell state, with Figure 12 The memory cell state of (c) is opposite to that of the selected memory cell in the same row as the selected memory cell to which the low resistance writing is performed. This illustrates the state in which the bit line BL and the source line SL of the non-selected memory cell in the same row as the selected memory cell to which the low resistance writing is performed are precharged to the same voltage as the voltage VwL of the gate electrode 404. In this case, the memory cell transistor 402 is turned off and no channel is formed. Therefore, an electric field between the gate electrode 404 and the semiconductor substrate 401 is applied to the gate oxide film 405. Since the semiconductor substrate 401 is generally set to 0V, the gate oxide film 405 is substantially Figure 12 The electric field of the gate oxide film 405 in the memory cell state of (c) is also 3.0 V, which is not so preferable when a finer process is applied.

[0213] As described above, the precharge voltage VPR of the source line SL and bit line BL of the memory cells in the unselected column is set to a predetermined voltage lower than the voltage obtained by subtracting the threshold voltage Vtns of the memory cell transistor 402 from the voltage VwL of the selected word line, but higher than 0V, to form a channel and enable application in a more sophisticated process. Specifically, the precharge voltage VPR can be set as shown in the following equation.

[0214] 0V<VPR<VwL-Vtns

[0215] In this case, the precharge voltage VPR is a voltage smaller than VwL-Vtns, although it is preferable to set to a higher voltage from the aspect of reducing the electric field of the gate oxide film 405, but on the other hand, precharging all the non-selected bit lines and non-selected source lines to a prescribed voltage also brings about the opposite problem of an increase in power consumption.

[0216] In consideration of the balance of both, for example, VPR = (VwL-Vtns) / 2, or the like, the optimum precharge voltage VPR can be set.

[0217] Further, in the present embodiment, in order to perform constant current two-stage reduction of the low-resistance writing current, the current waveform control circuit 24 is provided on the LR-use power supply terminal 11 side, but of course a current waveform control circuit having the same function can be provided on the GND terminal side.

[0218] Further, in the present embodiment, the storage unit transistor is used as the switching element, but in order to reduce the cell area, a bidirectional diode can also be used.

[0219] In addition, in the present embodiment, tantalum oxide is used as the resistance change layer 85, but the same effect can be obtained by using tantalum-aluminum oxide (TaAlO) in which aluminum (Al) is added to tantalum oxide.

[0220] [3. Modification]

[0221] Next, a modification of the main part of the resistance change type nonvolatile storage device of the embodiment will be described.

[0222] Figure 15 is a view showing a modification of the main part of the resistance change type nonvolatile storage device in the embodiment. The resistance change type nonvolatile storage device 2 of this view is different from the resistance change type nonvolatile storage device 2 of the embodiment shown in FIG. 1 in that a current waveform control circuit 24a is provided instead of the current waveform control circuit 24. Hereinafter, for the same parts, description will be avoided in order to focus on the different parts. Figure 1A In comparison, the difference is that the current waveform control circuit 24a is provided instead of the current waveform control circuit 24. Hereinafter, for the same parts, description will be avoided in order to focus on the different parts.

[0223] The current waveform control circuit 24a has a waveform generation part 35, a DAC 36, and a transistor 37.

[0224] The waveform generation part 35 generates a digital signal, that is, waveform data Ctl, showing the current waveform of the low-resistance writing current. The waveform generation part 35 is constituted by, for example, a ROM storing sample values showing the time series of the waveform data Ctl or a dedicated circuit.

[0225] DAC 36 is a digital-analog conversion circuit that converts the waveform data Ctl from the waveform generation section 35 into an analog signal. The DAC 36 supplies the converted analog signal as a gate voltage Vgp to the gate of the transistor 37.

[0226] The transistor 37 is a pMOS transistor that functions as a current source that supplies a low-resistance conversion current having a waveform corresponding to the gate voltage Vgp to the storage unit 3 via the LR conversion SL selection switch 14.

[0227] Figure 16 is a graph showing a modification example of the current waveform of the low-resistance conversion current in the embodiment. (a) of the graph shows the gate voltage Vgp output from the DAC 36 to the gate of the transistor 37. The current of (b) of the graph shows the low-resistance conversion current output from the transistor 37. Since the transistor 37 is a pMOS transistor, the low-resistance conversion current has a waveform that reverses with respect to the change in the gate voltage Vgp.

[0228] The current waveform of the low-resistance conversion current has a first period and a second period following the first period on the time axis. A portion of the low-resistance conversion current corresponding to the first period is referred to as a first current. A portion of the low-resistance conversion current corresponding to the second period is referred to as a second current. In (b) of the graph, the first current is a triangular wave having a first peak current Ip1. The second current is substantially a constant current having a current value Ip2 smaller than the first peak current Ip1. In addition, the first current at the time t2 at the end of the first period is not 0, and the second current Ip2 at the time t2 at the start of the second period is not 0. That is, the first current does not decrease from the peak to 0 within the first period, and the second current is a value that is not 0 at the start of the second period.

[0229] The current waveform of the low-resistance conversion current is able to obtain the same effect as Figure 16 even if it is a waveform like that of (b) of Figure 1B .

[0230] Further modification examples of the current waveform of the low-resistance conversion current are described.

[0231] Figure 17 is a graph showing a further modification example of the current waveform of the low-resistance conversion current in the modification example of the embodiment.

[0232] In the example of (a) of the graph, the low-resistance conversion current has a current waveform having a sawtooth waveform shape in which the decrease is sharp in the first period. The time width of the first period, the time width of the second period, the peak Ip1 of the first current, and the second current Ip2 can be the same as Figure 1B .

[0233] In the example of (b) of the drawing, the low-resistance conversion current has a current waveform in which the sawtooth waveform has a rising steep in the 1st period.

[0234] The example of (c) of the drawing is the same as (b) of Figure 16 .

[0235] In the example of (d) of the drawing, the low-resistance conversion current has a current waveform of a triangular wave in the 1st period and a current waveform in which the 2nd current is stepped down in the 2nd period.

[0236] In the example of (e) of the drawing, the low-resistance conversion current has 2 or more groups of the 1st period and the 2nd period like (c) of the drawing. The time width of the 1st period, the time width of the 2nd period, the peak value Ip1 of the 1st current, and the 2nd current Ip2 can also be different from Figure 1B .

[0237] As explained above, the resistance change type nonvolatile storage device 2 of one way of the embodiment has: a resistance change element (RSE) that can be reversibly changed to a high resistance state and a low resistance state; and a current waveform control circuit 24a as a current supply circuit that supplies a low-resistance conversion current for changing the resistance change element from the high resistance state to the low resistance state, the current waveform of the low-resistance conversion current having a 1st period and a 2nd period following the 1st period on a time axis, the current waveform control circuit 24a applying a 1st current to the resistance change element in the 1st period and applying a 2nd current smaller than the 1st current to the resistance change element in the 2nd period, the 1st current at the end of the 1st period not being 0, and the 2nd current at the start of the 2nd period not being 0.

[0238] Thus, in writing from the high resistance state to the low resistance state, deterioration of the initial window can be suppressed, and deterioration of the operation window at the time of high cycles (for example, at the time of 100,000 times of rewriting) can be suppressed. For example, even in the case of miniaturization, a stable rewriting operation with high reliability can be realized for a long period of time.

[0239] Here, the 1st current can be a constant current.

[0240] Thus, as the current waveform control circuit 24a, a constant current source can be used.

[0241] Here, the 1st current can have a peak value larger than the 2nd current.

[0242] Thus, the current waveform control circuit 24a can use a waveform of a non-constant current as the 1st current.

[0243] Here, the low-resistance conversion current can have a down-step current waveform.

[0244] Thus, the current waveform control circuit 24a generates the first current and the second current as a down-staircase current waveform. Therefore, the deterioration of the initial window described above can be suppressed, and the deterioration of the operation window at the time of high cycles (for example, at the time of 100,000 times of rewriting) can be suppressed.

[0245] Here, the current waveform control circuit 24a as the current supply circuit can supply the first constant current to the resistance change element during the first period, and supply the second constant current, which is smaller than the first constant current, to the resistance change element during the second period.

[0246] Thus, in writing from a high resistance state to a low resistance state, driving in which the constant current is reduced in two stages is performed. This driving is referred to as constant current two-stage reduction driving. This driving is suitable for generating the down-staircase current waveform described above. In addition, the periods in which current is supplied are not limited to only the first period and the second period, and a third, fourth,... nth period can be further included.

[0247] Here, the current waveform control circuit 24 as the current supply circuit can include the LR-use current limiting element 26 as the first constant current source and the LR-use current limiting element 27 as the second constant current source, and the current supply circuit can generate the first constant current by superimposing the constant current from the first constant current source and the constant current from the second constant current source during the first period, and generate the second constant current by using the constant current from one of the first constant current source and the second constant current source during the second period.

[0248] Thus, a higher current value than the second period is supplied to the resistance change element during the first period, and thus the initial window can be sufficiently ensured. A lower current value than the first period is supplied to the resistance change element during the second period, and thus the deterioration of the window at the time of high cycles can be suppressed.

[0249] Here, the current waveform control circuit 24 as the current supply circuit can further include the constant current control switch 31 as the first switch connected in series to the first constant current source, and the constant current control switch 32 as the second switch connected in series to the second constant current source, and the current supply circuit can supply the first constant current to the resistance change element by making both the first switch and the second switch in an on state during the first period, and supply the second constant current to the resistance change element by making one of the first switch and the second switch in an off state and making the other in an on state during the second period.

[0250] Thus, by the operation of the first switch and the second switch, a down staircase current waveform can be easily generated.

[0251] Here, the first period can be shorter than the second period.

[0252] Thus, the operation window can be expanded during the first period of the first constant current with relatively high current supply, and the deterioration of the operation window due to high cycle operation can be suppressed during the second period of the second constant current with relatively low current supply.

[0253] Here, the first period can be 10% or less of the second period.

[0254] Thus, the operation window can be expanded during the first period of 10% or less of the second period.

[0255] Here, the first period can be 5 nsec or less, and the second period can be 50 nsec or more.

[0256] Thus, the writing operation to the low resistance state can be performed at high speed.

[0257] Here, the second constant current can be 60% or less of the first constant current.

[0258] Thus, the writing operation to the low resistance state can be performed at low power.

[0259] Here, the first constant current can be 125 μA or more, and the second constant current can be 75 μA or less.

[0260] Thus, the writing operation to the low resistance state can be performed at low power.

[0261] Here, the resistance change element RSE can have a first electrode 81, a second electrode 84 formed to face the first electrode 81, and a resistance change layer 85 interposed between the first electrode 81 and the second electrode 84, the resistance change layer 85 including a transition metal oxide.

[0262] Here, the transition metal oxide can include an oxide of at least one of tantalum and hafnium.

[0263] Here, the resistance change element can be formed on a semiconductor substrate, and the second electrode 84 can be formed to be farther from the semiconductor substrate than the first electrode 81.

[0264] Here, the resistance change type nonvolatile memory device can include a plurality of memory cells arranged in a matrix, each of the memory cells including a switching element and the resistance change element connected in series to the switching element.

[0265] In this case, the switching element can be an NMOS transistor or a diode.

[0266] Further, the writing method of the resistance change type nonvolatile storage device of the embodiment is a writing method of changing a resistance change element RSE from a high resistance state to a low resistance state in a resistance change type nonvolatile storage device having the resistance change element RSE capable of reversibly changing to the high resistance state and the low resistance state as a storage unit, and the writing method supplies a first current to the resistance change element in a first period, and supplies a second current smaller than the first current to the resistance change element in a second period subsequent to the first period.

[0267] Thus, in rewriting from the high resistance state to the low resistance state, deterioration of the initial window can be suppressed, and deterioration of the operation window at the time of high cycles can be suppressed. Therefore, miniaturization is suitable.

[0268] Further, a resistance change type nonvolatile storage device and a writing method thereof, which are implemented by various modifications conceived by those skilled in the art or by arbitrarily combining the constituent elements in the embodiments, are included in the present disclosure, without departing from the scope of the present disclosure.

[0269] Industrial Applicability

[0270] As explained above, in the present disclosure, in a resistance change type nonvolatile storage device having a storage unit composed of a resistance change element whose resistance value reversibly changes based on an electric signal and a switching element such as a transistor, the number of times of rewriting can be increased simply with a practical writing control method, circuit area, and without significantly increasing the array area, so it is useful in realizing a highly reliable memory.

[0271] Explanation of Reference Numerals

[0272] 1, 402 Storage unit transistor

[0273] 2 Resistance change type nonvolatile storage device

[0274] 3 Storage unit

[0275] 10, 333, 335, 338, 340, 352, 355 PMOS transistor

[0276] 11 LRization power supply terminal

[0277] 12 LRization clamping control terminal

[0278] 13 LRization BL selection switch

[0279] 14 LRization SL selection switch

[0280] 16 HR conversion BL selection switch

[0281] 17 HR conversion power terminal

[0282] 18 HR conversion SL selection switch

[0283] 22a, 23 source line driver circuit

[0284] 22b bit line driver circuit

[0285] 24, 24a current waveform control circuit (current supply circuit)

[0286] 25 constant current control circuit

[0287] 26 LR conversion current limiting element (1st constant current source)

[0288] 27 LR conversion current limiting element (2nd constant current source)

[0289] 28 delay circuit

[0290] 29 NAND circuit

[0291] 30, 332, 337 inverter

[0292] 31 constant current control switch (1st switch)

[0293] 32 constant current control switch (2nd switch)

[0294] 33 write pulse width control terminal

[0295] 35 waveform generation section

[0296] 36 DAC

[0297] 37 transistor

[0298] 81 1st electrode (lower electrode)

[0299] 82 1st transition metal oxide layer

[0300] 83 2nd transition metal oxide layer

[0301] 84 2nd electrode (upper electrode)

[0302] 85 resistance change layer

[0303] 86 filament

[0304] 300 memory main body section

[0305] 301 memory array

[0306] 302 column selection circuit

[0307] 303 row selection circuit

[0308] 304 write circuit

[0309] 305 readout circuit

[0310] 306 peripheral circuit section

[0311] 307 control circuit

[0312] 308 voltage generating circuit

[0313] 309 low-resistance word line power supply

[0314] 310 high-resistance word line power supply

[0315] 311 readout word line power supply

[0316] 312 low-resistance clamp power supply

[0317] 313 low-resistance pulse power supply

[0318] 314 high-resistance pulse power supply

[0319] 315 precharge power supply

[0320] 316 word line voltage switching circuit

[0321] 317 address input circuit

[0322] 318 input / output circuit

[0323] 330 source line write circuit

[0324] 334, 342, 339, 341, 351, 354 NMOS transistor

[0325] 336 bit line write circuit

[0326] 350 bit line selection circuit

[0327] 353 source line selection circuit

[0328] 370 decoding circuit

[0329] 371 word line driver

[0330] 400 selected memory cell

[0331] 401 semiconductor substrate

[0332] 404 gate electrode

[0333] 405 gate oxide film

[0334] 406 drain

[0335] 407 source

[0336] 408, 411, 421 channel

[0337] 520 ultra-high resistance state

[0338] 3000a resistance change type nonvolatile storage element

[0339] 4000 resistance change type nonvolatile storage device

[0340] RSE resistance change type nonvolatile storage element

Claims

1. A resistance variable nonvolatile memory device, wherein: have: a resistance change element capable of reversibly changing between a high resistance state and a low resistance state; and a current supply circuit for supplying a resistance-lowering current to the resistance variable element for changing the resistance variable element from the high-resistance state to the low-resistance state; The current waveform of the resistance-lowering current has a first period and a second period following the first period on the time axis. The current increases from 0 at the beginning of the first period and decreases to 0 at the end of the second period. The current supply circuit applies a first current as a constant current to the variable resistance element during the first period. During the second period, a second current smaller than the first current is applied to the variable resistance element as a constant current. The first current at the end of the first period is not zero, The second current at the start of the second period is not zero.

2. The resistance variable nonvolatile memory device according to claim 1, wherein The resistance-lowering current has a current waveform in a downward step shape.

3. The resistance variable nonvolatile memory device according to claim 1, wherein the current supply circuit, During the first period, a first constant current is passed through the variable resistance element. During the second period, a second constant current smaller than the first constant current is passed through the variable resistance element.

4. The resistance variable nonvolatile memory device according to claim 3, wherein: The current supply circuit comprises: a first constant current source; and The second constant current source, the current supply circuit, During the first period, the first constant current is generated by superimposing the constant current from the first constant current source and the constant current from the second constant current source. During the second period, a constant current from one of the first constant current source and the second constant current source is generated as the second constant current.

5. The resistance variable nonvolatile memory device according to claim 4, wherein: The current supply circuit comprises: a first switch connected to the first constant current source; and The second switch is connected to the second constant current source. the current supply circuit, By turning on both the first switch and the second switch during the first period, the first constant current flows through the variable resistance element. During the second period, one of the first switch and the second switch is placed in a non-conductive state and the other is placed in a conductive state, thereby passing the second constant current through the variable resistance element.

6. The resistance variable nonvolatile memory device according to claim 1, wherein The first period is shorter than the second period.

7. The resistance variable nonvolatile memory device according to claim 1, wherein The first period is less than or equal to 10% of the second period.

8. The resistance variable nonvolatile memory device according to claim 1, wherein The first period is less than 5 nanoseconds. The second period is 50 nanoseconds or longer.

9. The resistance variable nonvolatile memory device according to claim 3, wherein: The second constant current is less than or equal to 60% of the first constant current.

10. The resistance variable nonvolatile memory device according to claim 3, wherein The first constant current is greater than 125 μA. The second constant current is 75 μA or less.

11. The resistance variable nonvolatile memory device according to claim 1, wherein The resistance change element has: 1st electrode; a second electrode formed to face the first electrode; and a resistance variable layer interposed between the first electrode and the second electrode, The resistance variable layer includes a transition metal oxide.

12. The resistance variable nonvolatile memory device according to claim 11, wherein The transition metal oxide includes an oxide of at least one of tantalum and hafnium.

13. The resistance variable nonvolatile memory device according to claim 11, wherein The resistance change element is formed on a semiconductor substrate. The second electrode is formed farther from the semiconductor substrate than the first electrode.

14. The resistance variable nonvolatile memory device according to any one of claims 1 to 13, wherein: The resistance variable nonvolatile memory device includes a plurality of memory cells arranged in a matrix. The memory cell includes a switching element and the variable resistance element connected in series with the switching element.

15. The resistance variable nonvolatile memory device according to claim 14, wherein The switching element is an NMOS transistor or a bidirectional diode.

16. A method for writing data to a variable resistance nonvolatile memory device, comprising: in a variable resistance nonvolatile memory device having a variable resistance element as a memory cell that can reversibly change between a high resistance state and a low resistance state, causing the variable resistance element to change from the high resistance state to the low resistance state; A first current as a constant current is supplied to the variable resistance element during a first period, and the current increases from 0 at the start of the first period. In a second period subsequent to the first period, a second current serving as a constant current smaller than the first current is supplied to the variable resistance element, and the current decreases to zero at the end of the second period. The first current at the end of the first period is not zero, The second current is not zero when the second period starts.

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