Semiconductor structure and method for manufacturing the same

Abstract

The present application provides a semiconductor structure and a method for manufacturing the same. In the method for manufacturing the semiconductor structure, for a substrate, a semiconductor layer of a first conductivity type, a light-emitting layer, and a semiconductor layer of a second conductivity type that are sequentially distributed from bottom to top, the semiconductor layer of the second conductivity type, the light-emitting layer, and the semiconductor layer of the first conductivity type in the first predetermined area are removed to form a groove, and the semiconductor layer of the second conductivity type, the light-emitting layer, and the semiconductor layer of the first conductivity type in the second and third predetermined areas are retained. The layers retained in the second predetermined area form light-emitting units arranged in an array, and the layers retained in the third predetermined area form connecting columns connecting adjacent light-emitting units; in both row and column directions, the width of the third predetermined area is smaller than the width of the second predetermined area. In this way, for the hollowed-out semiconductor layer of the first conductivity type, the light-emitting layer, and the semiconductor layer of the second conductivity type, the substrate can be removed from the groove by wet etching, and a plurality of small-sized LED structures can be formed in large quantities.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Group III nitride semiconductor materials have the advantages of large bandgap width (0.7eV~6.2eV), high carrier saturation migration rate, high breakdown electric field, and good thermal conductivity. They are very suitable for the preparation of blue, green, and ultraviolet LED devices as well as high-frequency, high-power, and electromagnetic radiation-resistant integrated electronic devices.

[0003] LEDs based on III-nitride semiconductor materials can be divided into horizontal structures and vertical structures. In the horizontal structure, the P electrode and the N electrode are arranged on the same side of the light-emitting structure, and the conduction current flows in the horizontal direction (perpendicular to the thickness direction of the LED). In the vertical structure, the P electrode and the N electrode are arranged on both sides of the light-emitting structure, and the conduction current flows in the vertical direction (the thickness direction of the LED). LEDs with horizontal structures can be divided into upright structures and inverted structures. In the upright structure, the P electrode is located on the optical path of the light emitting structure. In the inverted structure, neither the P electrode nor the N electrode is located on the optical path of the light emitting structure.

[0004] The LED manufacturing method in the prior art is suitable for large-size chip categories and application markets, but not for small-size chips, resulting in low manufacturing efficiency of mini-level (50μm~100μm) and micro-level (<50μm) LED chips.

[0005] In view of this, it is necessary to provide a semiconductor structure and a manufacturing method thereof to improve the manufacturing efficiency of small-sized LED chips. Summary of the invention

[0006] To achieve the above object, the present invention provides a semiconductor structure, comprising:

[0007] The light-emitting units are arranged in an array, and adjacent light-emitting units are connected together by connecting columns. In the row direction, the width of the connecting column is smaller than the width of the light-emitting unit; in the column direction, the width of the connecting column is smaller than the width of the light-emitting unit.

[0008] Optionally, the connecting column includes a trunk and branches, the trunk includes a first trunk extending along the row direction and / or a second trunk extending along the column direction, and the branch connects the first trunk with the light-emitting unit, or connects the second trunk with the light-emitting unit.

[0009] Optionally, the light-emitting unit includes an N-type semiconductor layer, a P-type semiconductor layer and a light-emitting layer located between the N-type semiconductor layer and the P-type semiconductor layer, and the connecting column and the N-type semiconductor layer are located in the same layer or the connecting column and the P-type semiconductor layer are located in the same layer.

[0010] Optionally, the light emitting unit further includes a P electrode and an N electrode, the P electrode is electrically connected to the P-type semiconductor layer, and the N electrode is electrically connected to the N-type semiconductor layer.

[0011] Optionally, the P electrode is located on a side of the P-type semiconductor layer away from the light emitting layer, and the N electrode is located on a side of the N-type semiconductor layer away from the light emitting layer.

[0012] Optionally, the P electrode and the N electrode are both located on a side of the P-type semiconductor layer away from the light emitting layer.

[0013] Optionally, the P electrode and the N electrode are both located on a side of the N-type semiconductor layer away from the light emitting layer.

[0014] Optionally, the light-emitting unit further includes a current diffusion layer, and the current diffusion layer is located on a side of the P-type semiconductor layer away from the light-emitting layer.

[0015] Optionally, the light emitting unit further includes a light reflecting layer, and the light reflecting layer is located on a side of the N-type semiconductor layer away from the light emitting layer or on a side of the P-type semiconductor layer away from the light emitting layer.

[0016] Optionally, the material of the light-emitting layer includes single quantum well material or multi-quantum well material.

[0017] Optionally, the light-emitting unit includes one light-emitting sub-unit or multiple light-emitting sub-units.

[0018] Optionally, the material of the light-emitting unit includes a Group III nitride material.

[0019] Another aspect of the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0020] Providing a substrate, and sequentially forming a semiconductor layer of a first conductivity type, a light emitting layer, and a semiconductor layer of a second conductivity type on the substrate, wherein the first conductivity type is one of an N-type and a P-type, and the second conductivity type is the other of the N-type and the P-type;

[0021] The second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the first predetermined area are removed to form a groove, and the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the second predetermined area and the third predetermined area are retained, the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the second predetermined area form an array-arranged light emitting unit, and the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the third predetermined area form a connecting column connecting adjacent light emitting units; in the row direction, the width of the third predetermined area is smaller than the width of the second predetermined area; in the column direction, the width of the third predetermined area is smaller than the width of the second predetermined area;

[0022] The substrate is removed from the groove by wet etching, and the etching solution used in the wet etching has a removal rate of the substrate in a horizontal direction that is greater than a removal rate in a thickness direction.

[0023] Optionally, the third predetermined area includes a trunk area and a branch area, the trunk area includes a first trunk area extending along the row direction and / or a second trunk area extending along the column direction, and the branch area connects the first trunk area with the second predetermined area, or connects the second trunk area with the second predetermined area.

[0024] Optionally, when removing the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the first predetermined area, the second conductive type semiconductor layer and the light emitting layer in the third predetermined area are also removed, and the first conductive type semiconductor layer is retained to form the connecting column.

[0025] Optionally, after forming a semiconductor layer of the first conductive type, a light emitting layer and a semiconductor layer of the second conductive type, and before removing the semiconductor layer of the second conductive type, the light emitting layer and the first conductive type in the first predetermined area to form a groove, the method further includes: removing the second conductive type semiconductor layer and the light emitting layer in a partial area of ​​the first predetermined area to expose a partial area of ​​the semiconductor layer of the first conductive type; forming a first electrode on the exposed semiconductor layer of the first conductive type, and forming a second electrode on the semiconductor layer of the second conductive type.

[0026] Optionally, after removing the second conductive type semiconductor layer in the first predetermined area and forming a groove between the light emitting layer and the first conductive type semiconductor layer, and before removing the substrate by wet etching, the method further includes: removing the second conductive type semiconductor layer and the light emitting layer in a partial area of ​​the first predetermined area to expose a partial area of ​​the first conductive type semiconductor layer; forming a first electrode on the exposed first conductive type semiconductor layer, and forming a second electrode on the second conductive type semiconductor layer.

[0027] Optionally, if the first conductive type semiconductor layer is a P-type semiconductor layer, a current diffusion layer is first formed on the exposed first conductive type semiconductor layer before forming the first electrode; if the second conductive type semiconductor layer is a P-type semiconductor layer, a current diffusion layer is first formed on the second conductive type semiconductor layer before forming the second electrode.

[0028] Optionally, before forming the semiconductor layer of the first conductivity type on the substrate, a light reflection layer is first formed; or after forming the semiconductor layer of the second conductivity type, a light reflection layer is also formed.

[0029] Optionally, the material of the light-emitting layer includes single quantum well material or multi-quantum well material.

[0030] Optionally, the light-emitting unit includes one light-emitting sub-unit or multiple light-emitting sub-units.

[0031] Optionally, the material of the first conductivity type semiconductor layer, and / or the light emitting layer, and / or the second conductivity type semiconductor layer includes a Group III nitride material.

[0032] Optionally, the material of the substrate is single crystal silicon, and the etching solution is a mixture of hydrofluoric acid, nitric acid and acetic acid.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1) In the method for manufacturing the semiconductor structure of the present invention: for the substrate, the semiconductor layer of the first conductivity type, the light emitting layer and the semiconductor layer of the second conductivity type which are sequentially distributed from bottom to top, the semiconductor layer of the second conductivity type, the light emitting layer and the semiconductor layer of the first conductivity type in the first predetermined area are removed to form a groove, and the semiconductor layer of the second conductivity type, the light emitting layer and the semiconductor layer of the first conductivity type in the second predetermined area and the third predetermined area are retained, the semiconductor layer of the second conductivity type, the light emitting layer and the semiconductor layer of the first conductivity type in the second predetermined area form an array-arranged light emitting unit, and the semiconductor layer of the second conductivity type, the light emitting layer and the semiconductor layer of the first conductivity type in the third predetermined area form a connecting column connecting adjacent light emitting units; in the row direction, the width of the third predetermined area is smaller than the width of the second predetermined area; in the column direction, the width of the third predetermined area is smaller than the width of the second predetermined area. In this way, the substrate can be removed from the groove by wet etching, and a plurality of small-sized LED structures can be formed in large quantities.

[0035] 2) In the optional solution, when the second conductivity type semiconductor layer, the light emitting layer and the first conductivity type semiconductor layer in the first predetermined area are removed, the second conductivity type semiconductor layer and the light emitting layer in the third predetermined area are also removed, and the first conductivity type semiconductor layer is retained to form a connecting column. The thickness of the connecting column is relatively thin, which can facilitate subsequent cutting to form each discrete LED structure.

[0036] 3) In an optional solution, the third predetermined area includes a trunk area and a branch area, the trunk area includes a first trunk area extending in the row direction and / or a second trunk area extending in the column direction, and the branch area connects the first trunk area with the second predetermined area, or connects the second trunk area with the second predetermined area. The trunk area can facilitate identification of the arrangement of each light-emitting unit and improve the uniformity of force between each light-emitting unit.

[0037] 4) In the optional scheme, after forming the semiconductor layer of the first conductivity type, the light emitting layer and the semiconductor layer of the second conductivity type, before removing the semiconductor layer of the second conductivity type, the light emitting layer and the semiconductor layer of the first conductivity type in the first predetermined area to form the groove, it also includes: removing the semiconductor layer of the second conductivity type and the light emitting layer in a part of the first predetermined area to expose a part of the semiconductor layer of the first conductivity type; forming a first electrode on the exposed semiconductor layer of the first conductivity type, and forming a second electrode on the semiconductor layer of the second conductivity type. This scheme can form a number of positive or inverted LED structures in large quantities at one time.

[0038] 5) In the optional scheme, after removing the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the first predetermined area to form a groove, before removing the substrate by wet etching, it also includes: removing the second conductive type semiconductor layer and the light emitting layer in a part of the first predetermined area to expose a part of the first conductive type semiconductor layer; forming a first electrode on the exposed first conductive type semiconductor layer, and forming a second electrode on the second conductive type semiconductor layer. This scheme can also form a number of positive or inverted LED structures in large quantities at one time. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention;

[0040] Figures 2 to 4 yes Figure 1 Schematic diagram of the intermediate structure corresponding to the process in;

[0041] Figure 5 is a top view of a semiconductor structure according to a first embodiment of the present invention;

[0042] Figure 6 It is along Figure 5 Cross-sectional view of line CC in;

[0043] Figure 7 It is along Figure 5 A cross-sectional view of the DD line in FIG.

[0044] Figure 8 is a top view of a semiconductor structure according to a second embodiment of the present invention;

[0045] Fig. 9 It is along Figure 8 A cross-sectional view of line EE in FIG.

[0046] Fig.10 is a top view of a semiconductor structure according to a third embodiment of the present invention;

[0047] Fig.11 It is produced Fig.10 Schematic diagram of the intermediate structure corresponding to the semiconductor structure process in;

[0048] Fig.12 is a top view of a semiconductor structure according to a fourth embodiment of the present invention;

[0049] Fig.13 is a schematic cross-sectional view of a semiconductor structure according to a fifth embodiment of the present invention;

[0050] Fig.14 is a schematic cross-sectional view of a semiconductor structure according to a sixth embodiment of the present invention;

[0051] Fig.15is a schematic cross-sectional structural diagram of a semiconductor structure according to a seventh embodiment of the present invention;

[0052] Figures 16 to 19 It is produced Fig.15 Schematic diagram of the intermediate structure corresponding to the semiconductor structure process in;

[0053] Fig. 20 is a schematic cross-sectional view of a semiconductor structure according to an eighth embodiment of the present invention;

[0054] Fig.21 It is produced Fig. 20 Schematic diagram of the intermediate structure corresponding to the semiconductor structure process in FIG. For the convenience of understanding the present invention, all the reference numerals appearing in the present invention are listed below:

[0055] Semiconductor structure 1, 2, 3, 4, 5, 6, 7, 8 substrate 10

[0056] Light emitting unit 11 N-type semiconductor layer 11a

[0057] P-type semiconductor layer 11b Light emitting layer 11c

[0058] First predetermined area 1a Second predetermined area 1b

[0059] Third predetermined area 1c groove 1v

[0060] Connecting column 12 Trunk 12a

[0061] Branch 12b First trunk 12c

[0062] Second trunk 12d Trunk area 1d

[0063] Branch area 1e First trunk area 1f

[0064] Second trunk region 1g N electrode 13

[0065] P electrode 14 Current diffusion layer 15

[0066] Light reflecting layer 16 Protective layer 17

[0067] Insulation layer 18 DETAILED DESCRIPTION

[0068] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0069] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention; Figures 2 to 4 yes Figure 1 Schematic diagram of the intermediate structure corresponding to the process in . Figure 5is a top view of a semiconductor structure according to a first embodiment of the present invention; Figure 6 It is along Figure 5 Cross-sectional view of line CC in; Figure 7 It is along Figure 5 Cross-sectional view of line DD in FIG.

[0070] First, refer to Figure 1 Step S1 in Figure 2 and Figure 3 As shown, a substrate 10 is provided, and a semiconductor layer of a first conductivity type, a light emitting layer 11c, and a semiconductor layer of a second conductivity type are sequentially formed on the substrate 10, wherein the first conductivity type is one of N-type and P-type, and the second conductivity type is the other of N-type and P-type. Figure 3 It is along Figure 2 Sectional view along line AA.

[0071] The material of the substrate 10 may be sapphire, silicon carbide, silicon, diamond, GaN, or one of sapphire, silicon carbide, silicon, diamond and GaN thereon.

[0072] The first conductive type semiconductor layer may be an N-type semiconductor layer 11a, and its material may be, for example, an N-type III-group nitride material. The N-type doping element may include at least one of Si, Ge, Sn, Se, or Te. The III-group nitride material may include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.

[0073] The formation process of the N-type semiconductor layer 11a may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0074] The N-type semiconductor layer 11 a may include one or more layers.

[0075] The light emitting layer 11c may include at least one of a single quantum well structure, a multi-quantum well (MQW) structure, a quantum wire structure, and a quantum dot structure. The light emitting layer 11c may include a well layer and a barrier layer formed of a group III nitride material. The group III nitride material may include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.

[0076] For example, the well layer may include an AlxGa1-xN layer, where x is the percentage of the mass of the Al element to the sum of the mass of the Al element and the Ga element, 1≥x≥0; and / or the barrier layer may include an AlyGa1-yN layer, where y is the percentage of the mass of the Al element to the sum of the mass of the Al element and the Ga element, 1≥y≥0. The bandgap width of the well layer is smaller than the bandgap width of the barrier layer.

[0077] The formation process of the well layer and / or the barrier layer may refer to the formation process of the N-type semiconductor layer 11 a .

[0078] The well layer and / or barrier layer may be doped with Al or not doped with Al. Not doping with Al can improve the crystal quality of the layer itself, but doping with Al can reduce the resistance of the layer itself.

[0079] Multiple layers of well layers and barrier layers can be alternately formed into a multi-quantum well structure, further improving the luminous efficiency.

[0080] The second conductive type semiconductor layer may be a P-type semiconductor layer 11b, such as a P-type III-group nitride material. The P-type doping element may include at least one of Mg, Zn, Ca, Sr or Ba. The III-group nitride material may include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.

[0081] The formation process of the P-type semiconductor layer 11 b may refer to the formation process of the N-type semiconductor layer 11 a .

[0082] The P-type semiconductor layer 11 b may include one or more layers.

[0083] In some embodiments, the P-type semiconductor layer 11 b may be close to the substrate 10 , and the N-type semiconductor layer 11 a may be far away from the substrate 10 .

[0084] Next, refer to Figure 1 Step S2 in Figures 2 to 4As shown, the second conductive type semiconductor layer, the light emitting layer 11c and the first conductive type semiconductor layer of the first predetermined area 1a are removed to form a groove 1v, and the second conductive type semiconductor layer, the light emitting layer 11c and the first conductive type semiconductor layer of the second predetermined area 1b and the third predetermined area 1c are retained. The second conductive type semiconductor layer, the light emitting layer 11c and the first conductive type semiconductor layer of the second predetermined area 1b form an array-arranged light emitting unit 11, and the second conductive type semiconductor layer, the light emitting layer 11c and the first conductive type semiconductor layer of the third predetermined area 1c form a connecting column 12 connecting adjacent light emitting units 11; in the row direction, the width of the third predetermined area 1c is smaller than the width of the second predetermined area 1b; in the column direction, the width of the third predetermined area 1c is smaller than the width of the second predetermined area 1b. Wherein, Figure 4 It is along Figure 2 Cross-sectional view of line BB in .

[0085] In some embodiments, the removal of the second conductivity type semiconductor layer, the light emitting layer 11c and the first conductivity type semiconductor layer in the first predetermined area 1a is achieved by dry etching. The etching gas of the dry etching may include: a mixed gas of BCl3 and Cl2.

[0086] In some embodiments, the removal of the second conductivity type semiconductor layer, the light emitting layer 11c and the first conductivity type semiconductor layer in the first predetermined area 1a is achieved by wet etching. The wet etching solution is, for example, a KOH solution, which is corrosive on the N surface but non-corrosive on the Ga surface. Therefore, the N surface of the second conductivity type semiconductor layer, the light emitting layer 11c and the first conductivity type semiconductor layer can be controlled to face upward through the growth process. The N surface of the second conductivity type semiconductor layer, the light emitting layer 11c and the first conductivity type semiconductor layer facing upward means that: with the Ga-N bond parallel to the C axis (

[0001] crystal direction) as a reference, the N atom in each Ga-N bond is farther away from the semiconductor substrate 10. It can be understood that at this time, the lower surface of the second conductivity type semiconductor layer, the light emitting layer 11c and the first conductivity type semiconductor layer is the Ga surface.

[0087] Afterwards, refer to Figure 1 Step S3 in Figures 2 to 7 As shown, the substrate 10 is removed from the groove 1v by wet etching, and the etching liquid used in the wet etching has a removal rate of the substrate 10 in the horizontal direction greater than the removal rate in the thickness direction. Figure 5 is a top view of the semiconductor structure after the substrate is removed; Figure 6 It is along Figure 5 Cross-sectional view of line CC in; Figure 7 It is along Figure 5 Cross-sectional view of line DD in FIG.

[0088] When the material of the substrate 10 is single crystal silicon, one crystal orientation of the horizontal plane may be

[110] , and the crystal orientation in the thickness direction may be

[111] , and the etching liquid may be a mixture of hydrofluoric acid, nitric acid, and acetic acid. Since the removal rate of the etching liquid in the

[110] crystal orientation is greater than the removal rate in the

[110] crystal orientation, the silicon substrate 10 can be separated from the semiconductor structure 1 without being completely etched, thereby accelerating the rate of stripping the substrate 10.

[0089] For other substrate 10 materials, such as sapphire, silicon carbide, diamond or GaN, targeted solutions can also be used for stripping.

[0090] Reference Figure 5 As shown, the semiconductor structure 1 of the first embodiment of the present invention includes:

[0091] The light-emitting units 11 are arranged in an array, and adjacent light-emitting units 11 are connected together by connecting columns 12. In the row direction, the width w1 of the connecting column 12 is smaller than the width W1 of the light-emitting unit 11; in the column direction, the width w2 of the connecting column 12 is smaller than the width W2 of the light-emitting unit 11.

[0092] In the semiconductor structure 1 , a plurality of small-sized light-emitting units 11 are connected together by connecting pillars 12 , which can be easily transferred. When the semiconductor structure 1 is used, it can be cut at the connecting pillars 12 to form individual light-emitting units 11 .

[0093] Figure 8 is a top view of a semiconductor structure according to a second embodiment of the present invention; Fig. 9 It is along Figure 8 Cross-sectional view of line EE in FIG.

[0094] Reference Figure 8 and Fig. 9 As shown, the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, and the only difference is that the connection pillar 12 and the semiconductor layer of the first conductivity type are located in the same layer.

[0095] In other words, when the N-type semiconductor layer 11 a is close to the substrate 10 , the connecting pillar 12 is located at the same layer as the N-type semiconductor layer 11 a ; when the P-type semiconductor layer 11 b is close to the substrate 10 , the connecting pillar 12 is located at the same layer as the P-type semiconductor layer 11 b .

[0096] The thickness of the connecting column 12 is relatively thin, which can facilitate subsequent cutting to form individual light-emitting units 11 .

[0097] Correspondingly, the manufacturing method of the semiconductor structure 2 of the second embodiment is substantially the same as the manufacturing method of the semiconductor structure 1 of the first embodiment, with the only difference being that in step S2, when the second conductive type semiconductor layer, the light emitting layer 11c and the first conductive type semiconductor layer of the first predetermined area 1a are removed, the second conductive type semiconductor layer and the light emitting layer 11c of the third predetermined area 1c are also removed, and the first conductive type semiconductor layer is retained to form a connecting column 12.

[0098] Removing the second conductivity type semiconductor layer, the light emitting layer 11c and the first conductivity type semiconductor layer in the first predetermined area 1a and removing the second conductivity type semiconductor layer and the light emitting layer 11c in the third predetermined area 1c can be performed in different processes. In other words, mask layers with different patterns can be used for dry etching or wet etching respectively.

[0099] Fig.10 FIG. 4 is a top view of a semiconductor structure according to a third embodiment of the present invention. Fig.11 It is produced Fig.10 Schematic diagram of the intermediate structure corresponding to the semiconductor structure process.

[0100] Reference Fig.10 As shown, the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, with the only difference being that the connecting column 12 includes a trunk 12a and a branch 12b, the trunk 12a includes a first trunk 12c extending along the row direction and a second trunk 12d extending along the column direction, and the branch 12b connects the first trunk 12c and the light-emitting unit 11, or connects the second trunk 12d and the light-emitting unit 11.

[0101] In some embodiments, the trunk 12a may include a first trunk 12c extending along the row direction to connect a row of light emitting units 11 together; or the trunk 12a may include a second trunk 12d extending along the column direction to connect a column of light emitting units 11 together.

[0102] The trunk 12 a can facilitate identification of the arrangement of the light-emitting units 11 and can improve the force uniformity between the light-emitting units 11 in the semiconductor structure 3 .

[0103] Correspondingly, refer to Fig.11 As shown, the manufacturing method of the semiconductor structure 3 of the third embodiment is substantially the same as the manufacturing method of the semiconductor structures 1 and 2 of the first and second embodiments, with the only difference being that in step S2, the third predetermined region 1c includes a trunk region 1d and a branch region 1e, the trunk region 1d includes a first trunk region 1f extending along the row direction and / or a second trunk region 1g extending along the column direction, and the branch region 1e connects the first trunk region 1f with the second predetermined region 1b, or connects the second trunk region 1g with the second predetermined region 1b.

[0104] Fig.12 FIG. 4 is a top view of a semiconductor structure according to a fourth embodiment of the present invention.

[0105] Reference Fig.12 As shown, the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structure 2 of the second embodiment, with the only difference being that the connecting column 12 includes a trunk 12a and a branch 12b, the trunk 12a includes a first trunk 12c extending along the row direction and a second trunk 12d extending along the column direction, and the branch 12b connects the first trunk 12c with the light-emitting unit 11, or connects the second trunk 12d with the light-emitting unit 11.

[0106] In some embodiments, the trunk 12a may include a first trunk 12c extending along the row direction to connect a row of light emitting units 11 together; or the trunk 12a may include a second trunk 12d extending along the column direction to connect a column of light emitting units 11 together.

[0107] Fig.13 FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to a fifth embodiment of the present invention.

[0108] Reference Fig.13 As shown, the semiconductor structure 5 of the fifth embodiment is substantially the same as the semiconductor structures 1, 2, 3, and 4 of the first, second, third, and fourth embodiments, with the only difference being that the light-emitting unit 11 further includes a P electrode 14 and an N electrode 13, the P electrode 14 is electrically connected to the P-type semiconductor layer 11b, and the N electrode 13 is electrically connected to the N-type semiconductor layer 11a.

[0109] The material of the P-electrode 14 and the N-electrode 13 can be metal, such as Ti / Al / Ni / Au, Ni / Au and other existing conductive materials.

[0110] An ohmic contact is formed between the P-electrode 14 and the P-type semiconductor layer 11 b , and an ohmic contact is also formed between the N-electrode 13 and the N-type semiconductor layer 11 a .

[0111] After the semiconductor structure 5 is cut, individual LED structures are formed.

[0112] Correspondingly, the manufacturing method of the semiconductor structure 5 of the fifth embodiment is substantially the same as the manufacturing method of the semiconductor structures 1, 2, 3, and 4 of the first, second, third, and fourth embodiments, and the only difference is that: between step S1 and step S2 or between step S2 and step S3, the following is performed: removing the second conductive type semiconductor layer and the light emitting layer 11c in a partial area of ​​the first predetermined area 1a, exposing a partial area of ​​the first conductive type semiconductor layer, forming a first electrode on the exposed first conductive type semiconductor layer, and forming a second electrode on the second conductive type semiconductor layer.

[0113] When the first conductive type semiconductor layer is an N-type semiconductor layer 11 a , the first electrode is an N-electrode 13 ; when the second conductive type semiconductor layer is a P-type semiconductor layer 11 b , the second electrode is a P-electrode 14 .

[0114] When the semiconductor layer of the first conductivity type is a P-type semiconductor layer 11 b , the first electrode is a P-electrode 14 ; and when the semiconductor layer of the second conductivity type is an N-type semiconductor layer 11 a , the second electrode is an N-electrode 13 .

[0115] The method for forming the first electrode and the second electrode may include: firstly forming a whole-surface metal layer by physical vapor deposition or chemical vapor deposition, and then patterning the metal layer.

[0116] Fig.14 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to a sixth embodiment of the present invention.

[0117] Reference Fig.14 As shown, the semiconductor structure 6 of the sixth embodiment is substantially the same as the semiconductor structures 1, 2, 3, 4, and 5 of the first, second, third, fourth, and fifth embodiments, with the only difference being that the light-emitting unit 11 further includes a current diffusion layer 15, which is located on a side of the P-type semiconductor layer 11b away from the light-emitting layer 11c. The current diffusion layer 15 can improve the conductivity of the P-type semiconductor layer 11b.

[0118] The material of the current diffusion layer 15 may be ITO.

[0119] Correspondingly, the manufacturing method of the semiconductor structure 6 of the sixth embodiment is substantially the same as the manufacturing method of the semiconductor structure 5 of the fifth embodiment.

[0120] When the first type of semiconductor layer is an N-type semiconductor layer 11a and the second type of semiconductor layer is a P-type semiconductor layer 11b, the difference between the manufacturing methods of the semiconductor structure 6 and the semiconductor structure 5 is that before forming the second electrode, a current diffusion layer 15 is first formed on the second conductive type semiconductor layer.

[0121] In the case where the first type of semiconductor layer is a P-type semiconductor layer 11b and the second type of semiconductor layer is an N-type semiconductor layer 11a, the difference between the manufacturing methods of the semiconductor structure 6 and the semiconductor structure 5 is only that before forming the first electrode, a current diffusion layer 15 is first formed on the exposed first conductive type semiconductor layer.

[0122] Fig.15 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to a seventh embodiment of the present invention. Figures 16 to 19 It is produced Fig.15 Schematic diagram of the intermediate structure corresponding to the semiconductor structure process.

[0123] Reference Fig.15As shown, the semiconductor structure 7 of the seventh embodiment is substantially the same as the semiconductor structure 6 of the sixth embodiment, and the only difference is that: the current diffusion layer 15 has a light reflection layer 16 on the side away from the light emitting layer 11c, and the current diffusion layer 15 and the light reflection layer 16 are encapsulated in a protective layer 17; the protective layer 17, the upper surface of the P-type semiconductor layer 11b not covered by the protective layer 17, the side walls of the P-type semiconductor layer 11b and the light emitting layer 11c, and the upper surface of the N-type semiconductor layer 11a are covered with an insulating layer 18; the insulating layer 18 has an opening that exposes a portion of the protective layer 17 on the P-type semiconductor layer 11b and the N-type semiconductor layer 11a, so as to form a P electrode 14 and an N electrode 13 accordingly.

[0124] The material of the light reflection layer 16 may be silver, and is used to reflect the light emitted by the light emitting layer 11 c into the light emitting layer 11 c, so that the light is emitted from the side of the N-type semiconductor layer 11 a.

[0125] The material of the protection layer 17 can be titanium or copper, which can prevent the silver of the light reflection layer 16 from being oxidized on the one hand, and prevent the current diffusion layer 15 from emitting light on the side on the other hand.

[0126] Correspondingly, the manufacturing method of the semiconductor structure 7 of the seventh embodiment is substantially the same as the manufacturing method of the semiconductor structure 6 of the sixth embodiment.

[0127] In the case where the first type of semiconductor layer is an N-type semiconductor layer 11a and the second type of semiconductor layer is a P-type semiconductor layer 11b, the difference between the manufacturing methods of the semiconductor structure 7 and the semiconductor structure 6 is that: between step S1 and step S2 or between step S2 and step S3, the following are performed: forming a light reflecting layer 16 on the side of the current diffusion layer 15 away from the light emitting layer 11c; forming a protective layer 17 covering the current diffusion layer 15 and the light reflecting layer 16; forming an insulating layer 18 on the protective layer 17, the upper surface of the P-type semiconductor layer 11b not covered by the protective layer 17, the side walls of the P-type semiconductor layer 11b and the light emitting layer 11c, and the exposed upper surface of the N-type semiconductor layer 11a; forming openings in the insulating layer 18 that respectively expose partial areas of the protective layer 17 and the N-type semiconductor layer 11a on the P-type semiconductor layer 11b, and forming a P electrode 14 and an N electrode 13 on the insulating layer 18 inside and outside the opening, respectively.

[0128] In one embodiment, referring to Figures 16 to 18 As shown, the formation of the P electrode 14 and the N electrode 13 is performed between step S1 and step S2.

[0129] Specifically, refer to Fig.16As shown, the P-type semiconductor layer 11b and the light-emitting layer 11c in a partial area of ​​the first predetermined area 1a are first removed to expose a partial area of ​​the N-type semiconductor layer 11a; then, a current diffusion material layer is formed on the P-type semiconductor layer 11b, the side walls of the P-type semiconductor layer 11b and the light-emitting layer 11c, and the exposed N-type semiconductor layer 11a by physical vapor deposition or chemical vapor deposition, and the current diffusion material layer is patterned, and the current diffusion material layer in a partial area on the P-type semiconductor layer 11b is retained to form a current diffusion layer 15; then, a first leveling layer is formed on the N-type semiconductor layer 11a, and the upper surface of the first leveling layer is flush with the upper surface of the current diffusion layer 15.

[0130] The first leveling layer may be made of an organic material with good fluidity, such as photoresist.

[0131] Reference Fig.17 As shown, a light reflecting layer 16 is formed on the upper surface of the first leveling layer and the upper surface of the current diffusion layer 15 by sputtering or electrodeless plating; the first leveling layer is torn off, and the light reflecting layer 16 on the first leveling layer is taken away together.

[0132] Continue to refer to Fig.17 As shown, a second leveling layer is formed on the N-type semiconductor layer 11a, and the upper surface of the second leveling layer is flush with the upper surface of the light reflecting layer 16; the second leveling layer is patterned to form a gap between the side walls of the current diffusion layer 15 and the light reflecting layer 16; Fig.18 As shown, a protective layer 17 is formed on the upper surface of the second leveling layer, the upper surface of the light reflecting layer 16 and the gap by sputtering or electrodeless plating; the second leveling layer is torn off, and the protective layer 17 on the second leveling layer is taken away together.

[0133] Reference Fig.19 As shown, an insulating layer 18 is formed on the protective layer 17, the upper surface of the P-type semiconductor layer 11b not covered by the protective layer 17, the side walls of the P-type semiconductor layer 11b and the light-emitting layer 11c, and the upper surface of the exposed N-type semiconductor layer 11a; openings are formed in the insulating layer 18 to expose the protective layer 17 on the P-type semiconductor layer 11b and the partial regions of the N-type semiconductor layer 11a, respectively, and the P-electrode 14 and the N-electrode 13 are formed on the insulating layer 18 inside and outside the openings, respectively. After the P-electrode 14 and the N-electrode 13 are formed, the P-type semiconductor layer 11b, the light-emitting layer 11c, and the N-type semiconductor layer 11a in the first predetermined area 1a are removed to form the groove 1v; or after the P-type semiconductor layer 11b, the light-emitting layer 11c, and the N-type semiconductor layer 11a in the first predetermined area 1a are removed to form the groove 1v, the insulating layer 18, the P-electrode 14, and the N-electrode 13 are formed.

[0134] In the case where the first type of semiconductor layer is a P-type semiconductor layer 11b and the second type of semiconductor layer is an N-type semiconductor layer 11a, the difference between the manufacturing methods of the semiconductor structure 7 and the semiconductor structure 6 is that: between step S1 and step S2 or between step S2 and step S3, the following are performed: forming a light reflecting layer 16 on the N-type semiconductor layer 11a; forming a protective layer 17 covering the light reflecting layer 16; forming an insulating layer 18 on the protective layer 17, the N-type semiconductor layer 11a not covered by the protective layer 17, the side walls of the N-type semiconductor layer 11a and the light-emitting layer 11c, the current diffusion layer 15, and the upper surface of the P-type semiconductor layer 11b without the current diffusion layer 15; forming openings in the insulating layer 18 that respectively expose partial areas of the protective layer 17 on the N-type semiconductor layer 11a and the current diffusion layer 15 on the P-type semiconductor layer 11b, and forming an N electrode 13 and a P electrode 14 on the insulating layer 18 inside and outside the opening, respectively.

[0135] Fig. 20 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to an eighth embodiment of the present invention. Fig.21 It is produced Fig. 20 Schematic diagram of the intermediate structure corresponding to the semiconductor structure process.

[0136] Reference Fig. 20 and Fig.21 As shown, the semiconductor structure 8 and its manufacturing method of the eighth embodiment are substantially the same as the semiconductor structure 7 and its manufacturing method of the seventh embodiment, with the only difference being that the light-emitting unit 11 includes two light-emitting sub-units, and the first electrodes on the first type of semiconductor layer of adjacent light-emitting sub-units are connected together.

[0137] In some embodiments, when the semiconductor structure 8 is cut, it can be cut along the middle of the first electrode, so that each light-emitting sub-unit has one first electrode.

[0138] When the first type semiconductor layer is an N-type semiconductor layer 11 a , the first electrode is an N-electrode 13 . When the first type semiconductor layer is a P-type semiconductor layer 11 b , the first electrode is a P-electrode 14 .

[0139] In the semiconductor structures 5, 6, 7, and 8 of the fifth, sixth, seventh, and eighth embodiments, the first electrode is formed by removing a portion of the second type semiconductor layer and the light emitting layer 11c to expose a portion of the first type semiconductor layer. In some embodiments, a plurality of electrical connection structures may be formed in the first type semiconductor layer to form the first electrode on a side of the second type semiconductor layer away from the light emitting layer 11c.

[0140] In some embodiments, after removing the substrate 10 , a first electrode may be formed on a side of the first type semiconductor layer away from the light emitting layer 11 c .

[0141] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: Light-emitting units (11) are arranged in an array, adjacent light-emitting units (11) are connected together via connecting columns (12), and in the row direction, the width of the connecting column (12) is smaller than the width of the light-emitting unit (11); in the column direction, the width of the connecting column (12) is smaller than the width of the light-emitting unit (11); The connection column includes a semiconductor layer of a first conductivity type, and the semiconductor layer of the first conductivity type is an N-type group III nitride material.

2. The semiconductor structure according to claim 1, characterized in that: The connecting column (12) comprises a trunk (12a) and a branch (12b), the trunk (12a) comprises a first trunk (12c) extending along a row direction and / or a second trunk (12d) extending along a column direction, and the branch (12b) connects the first trunk (12c) and the light-emitting unit (11), or connects the second trunk (12d) and the light-emitting unit (11).

3. The semiconductor structure according to claim 1 or 2, characterized in that: The light-emitting unit (11) comprises an N-type semiconductor layer (11a), a P-type semiconductor layer (11b), and a light-emitting layer (11c) located between the N-type semiconductor layer (11a) and the P-type semiconductor layer (11b); the connecting column (12) and the N-type semiconductor layer (11a) are located in the same layer, or the connecting column (12) and the P-type semiconductor layer (11b) are located in the same layer.

4. The semiconductor structure according to claim 3, characterized in that: The light-emitting unit (11) further comprises a P electrode (14) and an N electrode (13); the P electrode (14) is electrically connected to the P-type semiconductor layer (11b); and the N electrode (13) is electrically connected to the N-type semiconductor layer (11a).

5. The semiconductor structure according to claim 4, characterized in that: The P electrode (14) is located on a side of the P-type semiconductor layer (11b) away from the light-emitting layer (11c), and the N electrode (13) is located on a side of the N-type semiconductor layer (11a) away from the light-emitting layer (11c); or the P electrode (14) and the N electrode (13) are both located on a side of the P-type semiconductor layer (11b) away from the light-emitting layer (11c); or the P electrode (14) and the N electrode (13) are both located on a side of the N-type semiconductor layer (11a) away from the light-emitting layer (11c).

6. The semiconductor structure according to claim 3, characterized in that: The light-emitting unit (11) further comprises a current diffusion layer (15), wherein the current diffusion layer (15) is located on a side of the P-type semiconductor layer (11b) away from the light-emitting layer (11c).

7. The semiconductor structure according to claim 3, characterized in that: The light-emitting unit (11) further comprises a light-reflecting layer (16), wherein the light-reflecting layer (16) is located on a side of the N-type semiconductor layer (11a) away from the light-emitting layer (11c) or on a side of the P-type semiconductor layer (11b) away from the light-emitting layer (11c).

8. The semiconductor structure according to claim 3, characterized in that: The material of the light-emitting layer (11c) includes single quantum well material or multi-quantum well material.

9. The semiconductor structure according to claim 1, characterized in that: The light-emitting unit (11) comprises one light-emitting subunit or a plurality of light-emitting subunits.

10. The semiconductor structure according to claim 1, wherein: The material of the light-emitting unit (11) includes a group III nitride material.

11. A method for manufacturing a semiconductor structure, characterized in that: include: A substrate (10) is provided, and a semiconductor layer of a first conductivity type, a light-emitting layer (11c), and a semiconductor layer of a second conductivity type are sequentially formed on the substrate (10), wherein the first conductivity type is one of an N-type and a P-type, and the second conductivity type is the other of an N-type and a P-type, wherein the materials of the semiconductor layer of the first conductivity type, the light-emitting layer (11c), and the semiconductor layer of the second conductivity type are group III nitride materials; The second conductive type semiconductor layer, the light emitting layer (11c) and the first conductive type semiconductor layer of the first predetermined area (1a) are removed to form a groove (1v), and the second conductive type semiconductor layer, the light emitting layer (11c) and the first conductive type semiconductor layer of the second predetermined area (1b) and the third predetermined area (1c) are retained; the second conductive type semiconductor layer, the light emitting layer (11c) and the first conductive type semiconductor layer of the second predetermined area (1b) and the first conductive type semiconductor layer form an array-arranged light emitting unit (11); the second conductive type semiconductor layer, the light emitting layer (11c) and the first conductive type semiconductor layer of the third predetermined area (1c) form a connecting column (12) connecting adjacent light emitting units (11); in the row direction, the width of the third predetermined area (1c) is smaller than the width of the second predetermined area (1b); in the column direction, the width of the third predetermined area (1c) is smaller than the width of the second predetermined area (1b); The substrate (10) is removed from the groove (1v) by wet etching, wherein the etching solution used in the wet etching has a removal rate of the substrate (10) in a horizontal direction that is greater than a removal rate in a thickness direction.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The third predetermined area (1c) includes a trunk area (1d) and a branch area (1e), the trunk area (1d) includes a first trunk area (1f) extending along the row direction and / or a second trunk area (1g) extending along the column direction, and the branch area (1e) connects the first trunk area (1f) and the second predetermined area (1b), or connects the second trunk area (1g) and the second predetermined area (1b).

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: When the second conductive type semiconductor layer, the light emitting layer (11c) and the first conductive type semiconductor layer of the first predetermined area (1a) are removed, the second conductive type semiconductor layer and the light emitting layer (11c) of the third predetermined area (1c) are also removed, and the first conductive type semiconductor layer is retained to form the connecting column (12).

14. The method for manufacturing a semiconductor structure according to claim 11, 12 or 13, characterized in that: After forming a semiconductor layer of a first conductivity type, a light-emitting layer (11c) and a semiconductor layer of a second conductivity type, before removing the semiconductor layer of the second conductivity type, the light-emitting layer (11c) and the semiconductor layer of the first conductivity type in a first predetermined area (1a) to form a groove (1v), or after removing the semiconductor layer of the second conductivity type, the light-emitting layer (11c) and the semiconductor layer of the first conductivity type in a first predetermined area (1a) to form a groove (1v), and before removing the substrate (10) by wet etching, the method further includes: removing the semiconductor layer of the second conductivity type and the light-emitting layer (11c) in a partial area of ​​the first predetermined area (1a) to expose a partial area of ​​the semiconductor layer of the first conductivity type; forming a first electrode on the exposed semiconductor layer of the first conductivity type, and forming a second electrode on the semiconductor layer of the second conductivity type.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: If the first conductive type semiconductor layer is a P-type semiconductor layer (11b), before forming the first electrode, a current diffusion layer (15) is first formed on the exposed first conductive type semiconductor layer; if the second conductive type semiconductor layer is a P-type semiconductor layer (11b), before forming the second electrode, a current diffusion layer (15) is first formed on the second conductive type semiconductor layer.

16. The method for manufacturing a semiconductor structure according to claim 11, 12 or 13, characterized in that: Before forming a semiconductor layer of the first conductivity type on the substrate (10), a light reflection layer (16) is first formed; or after forming a semiconductor layer of the second conductivity type, a light reflection layer (16) is also formed.

17. The method for manufacturing a semiconductor structure according to claim 11, 12 or 13, characterized in that: The material of the light-emitting layer (11c) includes single quantum well material or multi-quantum well material.

18. The method for manufacturing a semiconductor structure according to claim 11, 12 or 13, characterized in that: The light-emitting unit (11) comprises one light-emitting subunit or a plurality of light-emitting subunits.

19. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The material of the substrate (10) is single crystal silicon, and the etching liquid is a mixed liquid of hydrofluoric acid, nitric acid and acetic acid.

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