Packaged stress sensors based on functional devices

Abstract

The present disclosure relates to packaged stress sensors based on functional devices. A semiconductor-based stress sensor may include a bipolar transistor device having first and second collector terminals. An excitation circuit may provide an excitation signal to the emitter terminal of the bipolar transistor device and may provide an indicator of physical stress in the semiconductor based on a relationship between signals measured at the collector terminal in response to the excitation signal. These signals may indicate charge carrier mobility characteristics of the semiconductor, which can be used to indicate physical stress. In one example, the physical stress indicator is based on current deflection characteristics in the base region of the transistor device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application Serial No. 63 / 233096 (Attorney Docket No. 3867.802PRV), filed on August 13, 2021, entitled “Packaged Stress Sensor,” the entirety of which is incorporated herein by reference. Background Art

[0003] Semiconductors can be subject to mechanical stress, for example due to environmental influences such as temperature or humidity. Stress or changes in stress can affect the performance or sensitivity of semiconductor devices.

[0004] The Hall effect refers to the voltage difference that can be generated across a conductor in the presence of a magnetic field. The direction of the generated voltage can be transverse to the current in the conductor and perpendicular to the magnetic field. Hall sensors are magnetic field sensors based on the Hall effect.

[0005] In some instances, a Hall effect sensor can provide an electrical output signal proportional to the component of the magnetic field affecting the sensor. A Hall effect sensor can include a Hall effect element or element group and a processor for receiving and interpreting the signals from one or more elements. In some instances, a Hall effect sensor includes an integrated circuit enclosed in a housing, and the sensor or its packaging may be subject to mechanical stress. When using a Hall effect sensor to characterize a magnetic field, it is necessary to eliminate the effects of mechanical stress on the sensor itself. Similarly, when using a stress sensor to characterize stress or stress changes, it may be necessary to eliminate any Hall effect that could affect or damage the stress indicator. Summary of the Invention

[0006] The inventors have recognized, among other things, that a problem to be solved involves determining appropriate compensation for package stress on a packaged integrated circuit. The inventors have recognized that a solution may include or utilize a sensor configured to measure mechanical stress while mitigating the effects of magnetic fields that would otherwise corrupt the stress measurement. The solution may include characterizing both the direction and magnitude of the stress. In turn, information about the direction and magnitude of the stress can be used with other circuitry to counteract the effects of the stress on other circuit components or performance parameters. For example, information about the direction and magnitude of the stress can be used to counteract error terms in a voltage or current signal reference generator or to calibrate offset in a converter circuit.

[0007] In one example, the solution may include or utilize a semiconductor Hall plate-based sensor configured to provide information about package stress. In one example, the sensor may include a Hall plate and an excitation circuit. The excitation circuit may provide signals to respective pairs of nodes of the Hall plate. A measurement circuit may receive information about a first electrical signal at a first pair of nodes in response to a first portion of the excitation signal, and may receive information about a second electrical signal at a second pair of nodes in response to a second portion of the excitation signal. The first and second electrical signals may indicate charge carrier mobility characteristics of the semiconductor, which may be used to indicate physical stress on the sensor.

[0008] In an example, the solution may include or use a semiconductor-based stress sensor including a bipolar transistor device having multiple (e.g., first and second) collector terminals. An excitation circuit may provide an excitation signal to a base-emitter junction of the bipolar transistor device and may provide an indicator of physical stress in the semiconductor based on a relationship between signals measured at the collector terminals in response to the excitation signal. In an example, the physical stress indicator may be based on a current deflection characteristic of a base region of the transistor device.

[0009] This abstract is not intended to provide an exclusive or exhaustive explanation of the present invention. The detailed description is included to provide further information about the patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To facilitate identification of the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which the element is first introduced.

[0011] Figure 1 Examples of semiconductor wafers and their crystal planes are generally shown.

[0012] Figure 2A and Figure 2B An example of a rectangular Hall plate is generally shown.

[0013] Figure 3A and Figure 3B An example of mechanical stress on a Hall plate is generally shown.

[0014] Figure 4A and Figure 4B Examples of Hall plates with different orientations on the wafer are generally shown.

[0015] Figure 5 An example of a non-rectangular Hall plate for stress sensing is generally shown.

[0016] Figure 6 An aspect of the subject matter according to one embodiment is illustrated.

[0017] Figure 7AAn example of a top view of the physical layout of a first bipolar junction transistor is generally shown.

[0018] Figure 7B An example of a cross-sectional view generally illustrating the physical layout of a first bipolar junction transistor is shown.

[0019] Figure 7C An example of a schematic diagram of a differential signal measurement circuit is generally shown.

[0020] Figure 8A An example of a top view of the physical layout of a second bipolar junction transistor is generally shown.

[0021] Figure 8B An example of a cross-sectional view generally illustrates the physical layout of a second bipolar junction transistor.

[0022] Figure 9 An example of a reference generator circuit built on a semiconductor wafer is generally shown.

[0023] Figure 10 Generally shown are examples of methods that may include using bipolar transistor devices to provide a physical stress indicator.

[0024] Figure 11 An example of a reference generator circuit is generally shown that includes a bipolar junction transistor with a split collector.

[0025] Figure 12 is a block diagram illustrating an example computing device capable of performing aspects of the various techniques discussed herein. DETAILED DESCRIPTION

[0026] Integrated circuits (ICs) can be mounted or packaged to help protect sensitive integrated circuits from stress or environmental influences. However, this packaging or mounting can be a source of mechanical stress on the semiconductor materials that make up the IC. For example, mechanical stress can affect or change circuit behavior because it can alter the mobility and scattering factors of charge carriers (e.g., electrons or holes). Such changes can cause drift or shift in parameters such as resistance, magnetic sensitivity, transistor behavior, or piezoelectric-related effects. In some examples, mechanical stress can vary over time due to external environmental influences, or it can vary due to long-term drift and material aging.

[0027] To compensate for package stress, stress sensors can be configured to sense the stress experienced by devices on a particular chip or substrate. In one example, a transistor or bulk resistor can be used to sense stress by measuring changes in electron mobility (e.g., for n-type materials) or hole mobility (e.g., for p-type materials). However, such devices can be sensitive to the presence of magnetic fields, which can introduce errors in stress measurements. In other words, the Lorentz force can cause current in the sensor to deflect, for example, in the presence of a magnetic field. In addition, some pressure sensors are not configured to sense the direction of pressure. The inventors have recognized solutions to these and other problems.

[0028] The present inventors have recognized that a solution to the stress measurement problem may include or utilize a sensor configured to measure mechanical stress while mitigating the effects of magnetic fields that could disrupt stress measurements. This solution may include characterizing both the direction and magnitude of the stress. This information about the stress direction and magnitude can, in turn, be used with other circuits to counteract the effects of stress on other circuit components or performance parameters. For example, information about the stress direction and magnitude can be used to cancel error terms in voltage or current signal reference generators or to calibrate offsets in converter circuits.

[0029] In one example, the solution may include or use a Hall plate. Using the results of multiple measurements, the circuit can be used to eliminate errors caused by the magnetic field, or estimate sensitivity or drift, or provide a corresponding stress compensation signal. In one example, the solution can include or use multiple semiconductor layers, such as a bipolar transistor having multiple collectors (or a collector that is bifurcated or further separated to separate terminals). Information about the respective current densities in different collectors can be used to characterize the direction or magnitude of stress in a package that includes the transistor. In some examples, the transistor can include part of a reference generator circuit or can be used to provide an offset signal to correct different reference generator circuits.

[0030] The various solutions discussed in this article offer various advantages over existing strain sensors. For example, using off-diagonal measurements of the mobility components in the Hall plate provides more information about the magnitude and direction of the strain components, compared to measuring the absolute mobility as resistance or transistor current. Furthermore, first-order temperature compensation can be achieved by taking the ratio of the off-diagonal components to the absolute resistance. Furthermore, the effects of nearby magnetic fields can be offset by using two measurements to cancel the Hall-effect voltage.

[0031] Figure 1 An example of the Miller index of a crystal structure is generally described. For example, a semiconductor wafer including silicon can be cut from a silicon ingot so that the wafer surface coincides with a crystal plane. Figure 1A plan view of such a semiconductor wafer cut in a plane designated

[100] is shown and includes a "principal plane" that indicates a particular crystal orientation. Some wafers include auxiliary planes to indicate the doping of the wafer (e.g., as n-type or p-type). The principal crystallographic directions in the wafer plane are Figure 1 In an example, the circuit structure can be built on a wafer with circuit side edges or walls extending parallel or perpendicular to the wafer plane.

[0032] By convention, using the Miller indices, plane

[110] extends perpendicular to the main plane, and plane

[110] extends parallel to the main plane. Plane

[010] extends at an angle of +45° and plane

[100] extends at an angle of -45° relative to the

[110] direction.

[0033] exist Figure 1 In the example, the angle It is defined relative to the

[110] plane. Circuit structures built on

[100] wafers are usually positioned vertically. The horizontal structure extends in the direction of In this direction, the principal planes can be considered parallel to the x-axis, and the edges of the chip (or circuit structure) are generally parallel to the x- and y-axes. In this example, the crystal planes

[100] and

[010] correspond to the diagonal directions of the structure.

[0034] Generally, silicon crystals with a

[100] configuration are widely available and are often used in the fabrication of integrated circuit devices. Therefore, the following discussion assumes the use of

[100] -type materials unless otherwise specified. However, those skilled in the art will appreciate that other materials can be similarly used.

[0035] Conventional stress sensors, such as those comprising a resistive bridge, may be affected by magnetic fields, which may result in errors in the measured stress signal. The present inventors have recognized that a better method of measuring stress may include or use a Hall plate, such as one that may include a generally symmetrical crystal structure having multiple signal contacts or nodes. Different pairs of nodes may be excited or biased by corresponding signals, and response signals may be measured from the corresponding different pairs of nodes. The response signals may be analyzed together to determine the mobility or deflection characteristics of electrons (or holes) in the Hall plate. Using the determined deflection characteristics, more accurate information about package stress may be determined while eliminating any Hall effect effects or the effects of any magnetic field.

[0036] In one example, a Hall plate comprises a doped semiconductor device with a specific width, length, and thickness. Conventional Hall plates are typically rectangular or square in shape and include two pairs of contacts, or nodes: one for biasing and the other for sensing or measurement. The nodes are located at the corners of the rectangular plate. Typically, the Hall plate is symmetrical about each axis connecting a corresponding pair of nodes. Hall plates can have other non-rectangular shapes, such as a cross, hexagon, or other shapes that exhibit symmetry along multiple axes.

[0037] Figure 2A and Figure 2B An example of a generally rectangular first Hall plate 202 is shown. The first Hall plate 202 may include a crystalline structure, for example, may include epitaxial layers that may be grown or deposited on a substrate such as silicon. In general, the first Hall plate 202 may include one or more layers formed in a well-defined orientation relative to the orientation of the substrate or seed layer.

[0038] In an example and independent of mechanical stress effects, the effect of a magnetic field on a Hall plate can be modeled as a bridge. For example, in unstressed silicon, the Hall voltage measured across a Hall plate can be a function of the bias current applied to the plate and the resistive properties of the plate.

[0039] To illustrate, Figure 2A and Figure 2B Examples of the rectangular first Hall plate 202 under different bias conditions are shown. The first Hall plate 202 includes two pairs of oppositely oriented nodes at its corners, a first pair of nodes p1+ and p1-, and a second pair of nodes p2+ and p2-. Figure 2A shows a first Hall plate 202 biased by a current signal I applied between nodes p2+ and p2-, while Figure 2B A first Hall plate 202 is shown biased by a current signal I applied between nodes p1+ and p1 −.

[0040] When a Hall plate, such as the first Hall plate 202, is biased by an input signal, its sensitivity is a function of the bias signal amplitude, a correction factor defined by the geometry of the particular plate, and the plate's resistive properties. The plate's resistive properties, sometimes called the Hall coefficient, are a function of the electron concentration (for n-type semiconductors) and the Hall factor, which depends on, among other things, temperature and scattering.

[0041] In one example, an ideal Hall plate can be modeled as a balanced Wheatstone bridge, which provides a uniform output voltage under stable bias conditions in the absence of a magnetic field. However, a real Hall plate exhibits a differential output voltage due to an offset induced by a magnetic field. As further explained in this article, this offset can be measured and utilized to identify or characterize stress on the Hall plate.

[0042] In one example, the Hall plate voltage, Figure 2A and Figure 2B The example is V H , depends linearly on the bias signal amplitude and can be modeled as:

[0043]

[0044] Where V1 is the voltage between nodes p1+ and p1-, V2 is the voltage between nodes p2+ and p2-, I1 is the current applied between nodes p1+ and p1-, and I2 is the current applied between nodes p2+ and p2-. Therefore, the voltages V1 and V2 are the bias current input signals and the Hall coefficient or R that describes the behavior of the Hall plate resistance. Hxx In other words, the value of the Hall coefficient can be used as or can represent the effect of the external magnetic field on the Hall plate.

[0045] exist Figure 2A In the example, the Hall voltage V H =V1=R H12 I2. In Figure 2B In the example, V H =V2=R H21 I1. In the example of the first Hall plate 202, the impedance matrix describing the system is antisymmetric in the presence of a magnetic field, so the Hall coefficients corresponding to the orthogonal axes can be equal and opposite. That is, due to the Hall effect, R H12 =-R H21 .

[0046] In the example and independent of the magnetic field effect, the mechanical stress effect on the Hall plate can be similarly modeled as a bridge. Figure 3A and Figure 3B Graphs generally illustrate examples of mechanical stress on a Hall plate (e.g., the first Hall plate 202) and its effect on specific off-diagonal mobility characteristics of the Hall plate. The characteristics of the first Hall plate 202 can be optimized for stress sensitivity, for example, to match another IC device requiring stress compensation (e.g., in terms of doping or material type, physical dimensions, etc.).

[0047] In unstressed silicon, the electron mobility in the Hall plate can be modeled as a scalar function of the applied bias or electric field. That is,

[0048]

[0049] Where J is the electron mobility, E is the applied electric field, q is the electron charge, and μ is a constant based on the properties of silicon itself when it is unstressed. Under stress, the electron mobility can be described by a tensor relationship. For example,

[0050]

[0051] where μ corresponds to the off-diagonal mobility components of electrons (e.g., for n-type semiconductors) or holes (e.g., for p-type semiconductors), or the stress effect across the Hall plate. These off-diagonal mobility coefficients can be measured indirectly, for example, using a bridge model similar to that in Equation 1. That is,

[0052]

[0053] where R Sxx represents the coefficients of the resistance tensor that describe the behavior of the Hall plate under stress. Stress causes a shift in the carrier mobility tensor that describes the plate. That is, the plate's resistance can become directionally dependent, and the off-diagonal components of the mobility tensor can deflect the current.

[0054] In one example, the off-diagonal coefficients μ xx This provides information about the magnitude of the applied stress and the direction or sign of the applied stress. In addition, due to the reciprocity of electron mobility, it can be assumed that the off-diagonal coefficient μ 12 Equal to μ 21 , accordingly, R S12 Equal to R S21 This reciprocity relationship can be used to determine the magnitude and direction of mechanical stress.

[0055] In examples that include or use the first Hall plate 202 to characterize mechanical stress, multiple measurements of the first Hall plate 202 can be used to eliminate the effects of the magnetic field on the stress. For example, a first measurement can include using Figure 3A The configuration shown measures V1, and the second measurement may include using Figure 3B The configuration shown measures V2. The results of the first and second measurements can be processed together to eliminate the magnetic field indicating component and isolate the stress indicating component. For example,

[0056] R 12 =R S12 +R H12 (Equation 5)

[0057] R 21 =R S21 +R H21 (Equation 6)

[0058] According to the above discussion, R H12 =-R H21 , R S12 =R S21 Therefore, the stress indicator component can be expressed by R S12 =R S21 =R 12 +R 21In other words, the influence of any interfering magnetic field can be eliminated by adding the results of the first and second measurements, and the remaining stress coefficient can correspond to the magnitude of the stress. In addition, the information about the orientation of the Hall plate used in the first and second measurements and the stress indicating component R S12 The sign of can be used to characterize the direction of stress.

[0059] Stress sensitivity or the effects of stress can depend, at least in part, on the orientation of the Hall plate relative to the crystal orientation of the Hall plate substrate. In some examples, a Hall plate can be used to sense the magnitude and direction of mechanical stress along multiple different axes, or along multiple different axes, such as by using multiple plates with different orientations on a substrate. Thus, multiple Hall plates can be used together to provide more information about the overall stress characteristics of a particular package. Multiple measurements can be taken with each Hall plate to characterize package stress and eliminate the effects of any magnetic fields.

[0060] Figure 4A and Figure 4B An example is generally shown including Hall plates having different orientations on the same first wafer 402, for example including a doped silicon substrate. Figure 4A An example of a second Hall plate 404 having a first orientation on a first wafer 402 is illustrated, and Figure 4B An example of a third Hall plate 406 having a second orientation on the same first wafer 402 is shown. Figure 4A The third Hall plate 406 is omitted from the view of the first wafer 402 in FIG. Figure 4B The second Hall plate 404 is omitted from the view of the first wafer 402 in FIG. The second Hall plate 404 and the third Hall plate 406 may be disposed at any respective locations on the first wafer 402, however, they may preferably be located proximate to each other.

[0061] exist Figure 4A and Figure 4B In the example of FIG, the first wafer 402 has a specific crystal orientation, for example, the second Hall plate 404 and the third Hall plate 406 have different orientations relative to the plane

[100] of the first wafer 402. The second Hall plate 404 can be configured to measure the electron mobility deviation in one plane of the first wafer 402, and the third Hall plate 406 can be configured to measure the electron mobility deviation in a different plane of the first wafer 402. Therefore, the second Hall plate 404 and the third Hall plate 406 can be used together to provide information about the stress on the first wafer 402 in multiple different axes corresponding to different planes.

[0062] Figure 5An example of a stress sensor system 500 is generally shown, which includes an octagonal Hall plate 502 disposed on the

[100] plane of a wafer. The stress sensor system 500 can include a bias signal source coupled to the octagonal Hall plate 502 using a bias signal multiplexer circuit 504, and the stress sensor system 500 can include a measurement circuit coupled to the octagonal Hall plate 502 using a measurement signal multiplexer circuit 506.

[0063] The octagonal Hall plate 502 includes four pairs of nodes (e.g., p1+ / -, p2+ / -, p3+ / -, and p4+ / -), one for each side thereof. The nodes can be individually addressed by a bias signal multiplexer circuit 504 to receive their respective excitation signals, and the nodes can be individually addressed by a measurement signal multiplexer circuit 506 to measure their respective responses to the excitation signals. Multiple excitation signals can be provided and corresponding multiple response signals can be measured to characterize the mechanical stress of the octagonal Hall plate 502 in one or more directions, and any magnetic field effects or influences can be eliminated.

[0064] In one example, the off-diagonal stress resistance or stress coefficient in the first planar direction may be given by:

[0065] 2R S13 =R 13 +R 31 (Equation 7).

[0066] The off-diagonal stress resistance or stress coefficient for a second planar direction (e.g., rotated 45 degrees relative to the first planar direction) can be given by:

[0067] 2R S24 =R 24 +R 42 (Equation 8).

[0068] In one example, Equations 7 and 8 can be used together to characterize mechanical stress, regardless of the influence of the magnetic field, in any direction. For example, using the off-diagonal stress components determined by Equations 7 and 8, the stress in any direction can be used as C1R S13 +C2R S24 A linear combination of , where C1 and C2 are empirically determined coefficients, such as may be derived from a stress calibration procedure.

[0069] Figure 6An example of a first method 600 is generally shown, which can include using a Hall plate sensor to provide information about physical stress on the sensor or a semiconductor comprising the sensor. At block 602, the first method 600 includes providing an excitation signal to a first node of a Hall plate comprising the sensor. The Hall plate can include a crystalline structure (e.g., a doped semiconductor) disposed on or coupled to a substrate that is shared with one or more other components or assemblies whose stress is to be measured. The Hall plate can include a symmetrical structure about at least two axes. The first node can be disposed at opposite side edges or edge regions of the first axis, and the second node can be disposed at opposite side edges or edge regions of the second axis. In one example, the first axis and the second axis can be orthogonal.

[0070] At block 604 , the first method 600 may include measuring a first response signal at a second node of the Hall plate. In one example, blocks 602 and 604 are performed simultaneously such that the response is measured at block 604 while the excitation signal is provided at block 602 .

[0071] At block 606, the first method 600 includes providing an excitation signal to the second node of the Hall plate. At block 608, the first method 600 includes measuring a second response signal at the first node of the Hall plate. In one example, the same excitation signal can be used for blocks 602 and 606 at respective different times. That is, a voltage or current stimulus signal having first signal characteristics (e.g., amplitude, duration, waveform shape, etc.) can be provided to the first node to evoke a first response signal, and an excitation signal having the same first signal characteristics can be provided to the second node to evoke a second response signal from the Hall plate.

[0072] At block 610, the first method 600 may include determining a relationship between the first and second response signals measured at blocks 604 and 608. This relationship may provide information about the off-diagonal charge carrier mobility characteristics of the Hall plate, which in turn may be used as a proxy for stress on the Hall plate and the semiconductor comprising the Hall plate. In an example, block 610 includes determining an amplitude difference between the first and second response signals. In an example, block 610 includes summing the information about the amplitudes of the first and second response signals and determining a resistance characteristic of the Hall plate. The resistance characteristic may be a tensor that describes the nonlinear characteristics of the Hall plate.

[0073] At block 612 , the first method 600 may include determining a physical stress indicator of the Hall plate sensor or a semiconductor including the sensor based on the relationship determined at block 610 .

[0074] Hall sensors are typically optimized in terms of material composition or orientation to receive or capture magnetic fields. For example, a Hall sensor or Hall plate may include a semiconductor with high carrier mobility to help maximize sensitivity to the effects of small magnetic fields. However, the inventors have recognized that a stress sensor may not require or use materials with maximum mobility. Instead, it may be desirable to provide a stress sensor that is similar in shape or configuration to or identical to the device for which the effects of stress are desired. For example, for a particular functional device or IC, it may be desirable to use another device of the same or similar configuration (e.g., in terms of size, shape, material composition, die or wafer location, etc.) as a sensor to sense pressure.

[0075] In one example, layered semiconductors can be used as specialized devices and sensors. For example, bipolar transistor devices can be used. Deflections in layered devices can affect the magnitude or direction of current flow. This deflection can be sensed and used as a proxy or indicator of substrate mobility, which in turn can indicate mechanical stress.

[0076] For example, a bipolar transistor can be configured with a split collector or multiple collector terminals. Current deflection between the different collector terminals results in a voltage difference across the transistor's base region. This voltage difference manifests as a measurable current difference between the collector terminals, indicating the device's cross-mobility.

[0077] Figure 7A An example of a top view of the physical layout of a bipolar junction transistor or first BJT device 700 with a split collector is generally shown. Figure 7B An example of a cross-sectional view of a layout of a first BJT device 700 with a split collector is generally shown. Figure 7B The illustration in includes a schematic diagram of a first BJT device 700 showing a split collector. The PNP first BJT device 700 includes terminals for an emitter, a base, and two collectors (Collector 1 and Collector 2), as well as a terminal for a body bias signal (VDD). Figure 7A and Figure 7B In an example, the first BJT device 700 includes a deep p-well (DPW) connected to respective different collector terminals, and the device substrate is implemented with a high-voltage n-well (HVNW). The first BJT device 700 also includes an n-type buried layer (NBL) and various other n-well (NW) and p-well (PW) regions. In some examples, the DPW can include slits or other interruptions in the DPW layer between and separating the collector current paths.

[0078] Figure 8A An example of a top view of the physical layout of an NPN bipolar junction transistor or second BJT device 800 with a split collector is generally shown. Figure 8BAn example of a cross-sectional view of a layout of a second BJT device 800 with a split collector is generally shown. In the example of the second BJT device 800, the N-type buried layer can have a slit or interruption that increases the resistance between the collector terminals C1 and C2. In some examples, when the internal resistance between the collector terminals increases, a relatively less sensitive current sensing circuit can be used to measure the collector current.

[0079] In the presence of mechanical stress, cross-mobility behavior of the first BJT device 700 or the second BJT device 800 may be sensed as a differential signal between the collector terminals. Figure 7C Generally shown is a schematic diagram of an amplifier circuit that can be used to measure a differential signal as a voltage signal Vs. In other words, the stress-induced deflection current μ12 can cause a voltage difference or non-uniformity across (e.g., primarily across) the base region (e.g., in the horizontal plane of the BJT device). As a result, a corresponding base-emitter voltage difference exists, and current flows unevenly or non-uniformly to the different collector terminals, namely, collector 1 (C1) and collector 2 (C2).

[0080] In one example, the current signal or differential current signal may be relatively difficult to measure due to the slight difference between the signals at the respective collector terminals. A solution to the measurement problem may include providing a high resistance collector region. For example, the high resistance collector may be implemented by pinching off the deep p-well (DPW) region in the first BJT device 700, pinching off the N-type buried layer in the second BJT device 800, or increasing the width of the emitter region.

[0081] The base current behavior can be modeled using a tensor relationship between mobility and charge concentration. For example,

[0082]

[0083] where J1 is the current amplitude in the horizontal (deflection) direction, J2 is the current amplitude in the vertical (e.g., emitter to base region) direction, q is the electron charge, D is the diffusion constant, and μ ij is the charge carrier (electron or hole) mobility, N is the charge concentration, is the charge concentration gradient.

[0084] In this example, the charge is injected vertically downward from the emitter terminal towards the base region. Therefore, and For example, in the absence of stress on the first BJT device 700, the charge carrier mobility is zero (eg, μ 21= 0), and the current flows vertically (e.g., J1 = 0). However, under stress, the current deflects (e.g., J1 ≠ 0), and the difference in collector current in the first BJT device 700 can be detected at the Collector 1 and Collector 2 terminals (e.g., using Figure 7C differential sensor in ).

[0085] In an example, the first BJT device 700 or the second BJT device 800 or a variation thereof may include a portion of a reference generator circuit, such as a voltage reference generator or a current reference generator. The reference generator circuit may be used to provide a reference signal for use in various circuits. In an example, the reference signal may be used to provide a stable and accurate bias signal for use by various components or systems (e.g., an amplifier, a comparator, an analog-to-digital converter, a digital-to-analog converter, an oscillator, or a phase-locked loop, etc.).

[0086] Various different types of reference generator circuits can be provided. Some examples of the different types can include a bandgap reference generator, a MOS-Vth differential reference generator, and a work function differential reference generator. A bandgap reference generator can be provided using bipolar junction transistor (BJT) devices, such as the first BJT device 700 or the second BJT device 800. A bandgap generator can include voltage sources with respective positive and negative temperature coefficients, such that when the sources are added together, the temperature dependence of the device can be eliminated. However, bandgap reference generators may have some limitations, such as sensitivity to substrate noise or stress. When a multi-collector BJT device is used in the reference generator, any offset due to package stress can be detected and mitigated, for example, using information related to the differential current signal at the split collector terminals. In other words, the multi-collector BJT device can include one or more devices that include a bandgap reference generator and can sense information about the stress on the BJT device, for example in a time-multiplexed manner with the operation of the reference generator itself.

[0087] In other examples, a BJT-based reference generator circuit can include one or more transistors, and the first BJT device 700, the second BJT device 800, or other multi-collector BJT devices can be provided as clones or replicas of transistors of one or more further generator circuits. The BJT device can be constructed physically close to or adjacent to one or more transistors of the reference generator circuit so that stress information from the BJT device can be sensed in real time by operation of the reference generator circuit. In one example, multiple instances of the multi-collector BJT device can be physically constructed around or near different sides of other components of the reference generator. Each of the multiple instances can be used to individually characterize stress, for example, which may unequally affect the device comprising the generator circuit due to the different physical locations of the devices around a package or substrate comprising the generator.

[0088] In an alternative example for sensing stress in or around a bandgap reference signal generator circuit, current flowing through multiple paths in a pinch resistor can be used instead of a multi-collector BJT device. In this example, the pinch resistor can be made of the same material as the base region of the bipolar transistor in the generator circuit. That is, if the bandgap circuit uses an NPN transistor with a p-type base, the pinch resistor can be made of p-type material; if the bandgap circuit uses a PNP transistor with an n-type base, the pinch resistor can be made of n-type material.

[0089] Figure 9 An example layout 900 of a first IC die 902 is generally shown. The first IC die 902 may include a first reference generator circuit 904 and a second reference generator circuit 906. Each of the first reference generator circuit 904 and the second reference generator circuit 906 may include a transistor-based (e.g., bandgap-type) reference generator circuit that includes or uses a plurality of transistors, resistors, or other IC-based components to generate a reference current signal or a reference voltage signal. Portions of the first IC die 902 may be diced and individually packaged.

[0090] In an example, the first IC wafer 902 includes one or more stress sensor circuits configured to measure physical stress at various regions of the first IC wafer 902. For example, the first IC wafer 902 may include a first die 910 including a first stress sensor 908a proximate to a first reference generator circuit 904 and a second stress sensor 908b proximate to the first reference generator circuit 904. That is, the first reference generator circuit 904 may include or utilize multiple stress sensors having a shared or common substrate with the reference generator itself, such as on the same die. Figure 9In the example, first stress sensor 908a and second stress sensor 908b are positioned adjacent to respective sides or side regions of a circuit including first reference generator circuit 904. In one example, first reference generator circuit 904, first stress sensor 908a, and second stress sensor 908b comprise a portion of first IC die 902 that may be packaged together.

[0091] The first stress sensor 908a or the second stress sensor 908b may include a corresponding transistor device of the same size or shape as the transistor devices comprising the first reference generator circuit 904. That is, the first stress sensor 908a or the second stress sensor 908b may include a device that is a clone or duplicate of one or more devices in the first reference generator circuit 904. For example, the devices may have the same or substantially the same width, length, material type, or doping characteristics. The devices may be located near or adjacent to each other so that they are substantially identical with respect to any process-related variations or inconsistencies.

[0092] In one example, the first reference generator circuit 904 includes or can be coupled to a processor circuit configured to receive reference signal information from, for example, a bandgap-type reference generator and one or more correction signals from the first stress sensor 908a and the second stress sensor 908b. The processor circuit can use the one or more correction signals to update or adjust the reference signal information from the reference generator to provide a stress-corrected reference signal. The stress-corrected reference signal can include a voltage or current reference signal that is not affected by package stress or deformation of the first IC die 902 or the package that includes the first reference generator circuit 904, the first stress sensor 908a, and the second stress sensor 908b.

[0093] In one example, the second reference generator circuit 906 includes a third stress sensor 908c. The third stress sensor 908c may comprise a portion of the second reference generator circuit 906 itself. That is, the second reference generator circuit 906 may comprise a transistor-based reference generator circuit, and the third stress sensor 908c may comprise a transistor used by the second reference generator circuit 906 to generate a reference signal. In one example, the second reference generator circuit 906 includes a multiplexer circuit configured to generate a reference signal using the third stress sensor 908c and to generate a stress-indicating correction signal during various time intervals. The second reference generator circuit 906 may be configured to provide a stress-corrected reference signal based on information from the third stress sensor 908c regarding the stress on the third stress sensor 908c.

[0094] In other words, the reference circuit can be constructed in a variety of ways. In one example, the reference circuit can include components separate from the stress sensing circuit components. The stress-indicating signal generated by the stress sensing circuit can be used to compensate for the stress sensitivity of the reference circuit. In another example, the reference circuit can include a split-collector transistor that functions both as part of the reference signal generator itself and as part of the stress sensor. In a discrete-time implementation, the split-collector transistor can function as a stress sensor during certain time intervals and as a component in the reference signal generator at other intervals. In a continuous-time implementation, the split-collector transistor can function as both a reference generator and a stress sensor simultaneously or concurrently. In this example, the base-emitter voltage of the transistor can comprise part of the reference generator circuit, while the difference in collector current can be measured to generate a stress-indicating signal, which can in turn be used to compensate for stress effects on the generated reference signal.

[0095] Figure 10 An example of a second method 1000 is generally shown, which can include using a transistor device to provide a physical stress indicator. At block 1002, the second method 1000 includes providing a bipolar junction transistor (BJT) device having multiple collectors or a bifurcated collector. That is, block 1002 can include constructing a BJT device that includes a collector region coupled to two or more discrete terminals. Figure 7A and Figure 7B Examples of BJT devices with bifurcated or split collectors are provided in . BJT devices with bifurcated collectors may experience current deflection in the base region of the device, for example, when the device is under mechanical stress. Although sometimes referred to herein as "bifurcated," it should be understood that the collector can have more than two discrete branches.

[0096] At block 1004, the second method 1000 includes providing an excitation or drive signal to the emitter of the BJT device. Under appropriate bias conditions, the BJT device can turn on and conduct current from the emitter, through the base region, to each of the first and second collector regions and the corresponding first and second collector terminals. Although the examples discussed herein include BJT devices with two collectors, devices with more than two collectors can also be similarly used. For example, a bipolar transistor device with four collectors can be used to identify stress along two different axes.

[0097] At block 1006 and in response to the excitation signal, first and second response signals may be measured at the first and second collector terminals, respectively. Under the influence of package deformation or substrate stress, the current flowing through the base region of the BJT device may be interrupted or uneven. Therefore, the response signals may have different amplitude characteristics, which may be analyzed and utilized to provide information about the amplitude and / or direction of the package stress. For example, at block 1008, the second method 1000 may include determining a current amplitude difference between the first and second response signals. Based on the magnitude difference, a physical stress indicator may be provided. Based on the determined current amplitude difference, the second method 1000 may include providing a physical stress indicator for the BJT device at block 1010.

[0098] In an example, the BJT device in the second method 1000 can be used in or with a reference generator circuit, such as a voltage signal or current signal generator circuit. At block 1012, the second method 1000 can include providing a correction signal to the reference generator circuit based on the physical stress indicator from block 1010. That is, block 1012 can include using the physical stress indicator to provide information regarding correction of the reference generator circuit, where one or more components of the reference generator circuit are subjected to the same or similar stresses as the BJT device. In some examples, the BJT device is a clone or replica of one or more devices in the reference generator circuit and / or is physically constructed near one or more devices in the reference generator circuit.

[0099] In one example, the reference generator circuit may include or utilize the BJT device itself at block 1014. For example, the base-emitter voltage (Vbe) characteristic of the BJT device may be utilized, for example, along with Vbe characteristic information of a second device loaded with a different current density, to provide a reference signal, or may be utilized by the reference generator circuit to provide another component of a reference signal.

[0100] Figure 11 An example of a reference generator circuit 1100 is generally shown. The reference generator circuit 1100 includes a pressure-immune voltage reference generator having a PNP BJT device configured as a pressure sensor. The reference generator circuit 1100 includes a proportional-to-absolute-temperature (PTAT) voltage generator (left) and a PNP VBE generator (right). The reference generator circuit 1100 includes various amplifier circuits (labeled I0, I1, I2, I3) and a programmable gain amplifier (PGA), which can be chopped to improve accuracy and eliminate drift.

[0101] In one example, reference generator circuit 1100 includes a high-precision PTAT voltage generator comprising transistors Q1 and Q2, amplifier circuits I0, I1, and I2, transistors MN1, MN2, and MP1, and resistors R1-R6. Amplifier circuit I0 provides the PTAT voltage across R3 by forcing equal collector currents in transistors Q1 and Q2. The base current of Q1 is canceled by the loop established by amplifier circuit I1 and transistor MN2, so the voltage drop across R5 can be considered proportional to absolute temperature without base current errors. In this example, canceling Q1's base current eliminates errors caused by beta variations due to stress, temperature, and process variations. Amplifier circuit I2 is configured to force the collector currents of transistors Q1 and Q2 to be proportional to absolute temperature.

[0102] In this example, in addition to any packaging stress on the reference generator circuit 1100, silica particles in the molding compound filler used in the plastic package can induce point stresses on the device surface. In some cases, if the silica particles directly stress the transistor device Q1, the voltage reference may exhibit abnormal performance over temperature. To reduce the effects of these or other localized stresses, the PTAT voltage generator can use, for example, dynamic element matching (DEM) to alternate the position of transistor Q1.

[0103] The PNP VBE generator of reference generator circuit 1100 may include transistor Q3, which may, for example, include a PNP device with multiple collectors, such as those described in the examples of first BJT device 700, second BJT device 800, or other multi-collector BJT devices. The VBE generator may also include a control loop, including, for example, amplifiers I3 and I4. Individual collector currents in transistor Q3 can be detected via voltage drops across resistors R8-R10, and a PGA can amplify the difference between any two collector currents selected by a multiplexer (MUX). In this example, the output of the PGA can be proportional to a combination of stress effects and any initial device mismatch. The variation of these difference signals over time can be used to compensate for significant stress effects in the reference voltage. In this example, amplifier circuit I4 provides a virtual diode connection for transistor Q3 without injecting base current errors. The positive input of amplifier I4 can be implemented with a split MOS input pair to average all voltage drop signals across resistors R8-R10, for example, rather than the one shown in reference generator circuit 1100. The amplifier loop includes amplifier I3, and transistor MP2 can control the total collector current flowing into transistor Q3 and force it to be proportional to absolute temperature.

[0104] An analog-to-digital converter (ADC) circuit can be used to measure three differential signals: {VPTAT,AGND}, {PNPVBE+,PNPVBE-}, and {STRESS,AGND}, providing implicit voltage reference signals for system calibration. In some examples, adding the differential PNPVBE measurement to the scaled PTAT voltage produces a first-order temperature-compensated voltage that can be used to compensate for stress using the measured collector current differences.

[0105] Figure 12 1200 is a diagrammatic representation of a machine 1200 in which instructions 1208 (e.g., software, a program, an application, an applet, an application, or other executable code) may be executed to cause the machine 1200 to perform any one or more of the methodologies discussed herein. For example, the instructions 1208 may cause the machine 1200 to perform any one or more of the methodologies described herein, such as generating or providing an excitation signal, measuring a response signal, coordinate measurement timing or operation of a multiplexer circuit, calculating a tensor relationship, providing a physical stress indicator for a stress sensor, or generating a correction signal for a reference generator circuit, a converter circuit, or other circuit. The instructions 1208 transform a general-purpose, unprogrammed machine 1200 into a specific machine 1200 that is programmed to perform the functions described and illustrated in the manner described. The machine 1200 may operate as a standalone device or may be coupled (e.g., networked) to other machines, such as to coordinate actions or functions across different circuits. In some examples, mixed signal circuit implementations using analog-to-digital converter (ADC) and / or digital-to-analog converter (DAC) circuits can be used to measure and generate analog signals that can be used to control the reference and pressure sensing circuits discussed herein, such as when the majority of the signal processing is performed using digital techniques. In other examples, all required signal processing in the current, charge, and / or voltage domains can include or use analog signal processing techniques.

[0106] In a networked deployment, the machine 1200 may operate as a server or a client machine in a server-client network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine 1200 may include, but is not limited to, a server computer, a client computer, a personal computer (PC), a tablet computer, a laptop computer, a netbook computer, a set-top box (STB), a PDA, an entertainment media system, a cellular phone, a smartphone, a mobile device, a wearable device (such as a smartwatch), a smart home device (such as a smart appliance), other smart devices, a network device, a network router, a network switch, a network bridge, or any machine capable of executing instructions 1208, whether sequentially or otherwise, to perform actions specified by the machine 1200. Furthermore, while a single machine 1200 is illustrated, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute the instructions 1208 to perform any one or more of the methodologies discussed herein.

[0107] The machine 1200 may include a processor 1202, a memory 1204, and I / O components 1242, which may be configured to communicate with each other via a bus 1244. In an example embodiment, the processor 1202 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a radio frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, a processor 1206 that executes instructions 1208 and a processor 1210. The term "processor" is intended to include multi-core processors (sometimes referred to as "cores") that may include two or more independent processors that may execute instructions simultaneously. Although Figure 12 Multiple processors 1202 are shown, but the machine 1200 may include a single processor with a single core, a single processor with multiple cores (e.g., a multi-core processor), multiple processors with a single core, multiple processors with multiple cores, or any combination thereof.

[0108] The memory 1204 includes a main memory 1212, a static memory 1214, and a storage unit 1216, all of which are accessible to the processor 1202 via a bus 1244. The main memory 1204, the static memory 1214, and the storage unit 1216 store instructions 1208 that embody any one or more of the methodologies or functionality described herein. During execution by the machine 1200, the instructions 1208 may reside, completely or partially, within the main memory 1212, within the static memory 1214, within the machine-readable medium 1218 within the storage unit 1216, within at least one processor 1202 (e.g., within a processor's cache), or any suitable combination thereof.

[0109] The I / O components 1242 may include a variety of components to receive input, provide output, generate output, transmit information, exchange information, capture measurements, and the like. The specific I / O components 1242 included in a particular machine will depend on the type of machine. For example, a portable machine such as a mobile phone may include a touch input device or other such input mechanism, while a headless server machine may not include such a touch input device. It should be understood that the I / O components 1242 may include Figure 12 Many other components not shown in FIG. In various example embodiments, the I / O components 1242 may include output components 1228 and input components 1230. The output components 1228 may include visual components (e.g., displays such as plasma display panels (PDPs), light emitting diode (LED) displays, liquid crystal displays (LCDs), projectors, or cathode ray tubes (CRTs)), acoustic components (e.g., speakers), tactile components (e.g., vibration motors, resistive mechanisms), other signal generators or converters. The input components 1230 may include alphanumeric input components (e.g., keyboards, touch screens configured to receive alphanumeric input, optical keyboards, or other alphanumeric input components), point-based input components (e.g., mice, touchpads, trackballs, joysticks, motion sensors, or other pointer tools), tactile input components (e.g., physical buttons, touch screens that provide position and / or touch force or touch gestures, or other tactile input components), audio input components (e.g., microphones), and the like.

[0110] In another example embodiment, the I / O component 1242 may include various sensors, such as one or more of the biometric component 1232, the motion component 1234, the environmental component 1236, or the position component 1238, as well as a wide range of other components. For example, the biometric component 1232 includes components for detecting expressions (e.g., hand expressions, facial expressions, vocal expressions, body postures, or eye tracking), measuring biosignals (e.g., blood pressure, heart rate, body temperature, perspiration, muscle oxygenation, or brain waves), identifying people (e.g., voice recognition, retinal recognition, facial recognition, fingerprint recognition, or EEG-based recognition), etc. The motion component 1234 may include a motion sensor 324, such as an acceleration sensor component (e.g., an accelerometer), a gravity sensor component, a rotation sensor component (e.g., a gyroscope), etc. The environment component 1236 includes, for example, an illumination sensor component (e.g., a photometer), a temperature sensor component (e.g., one or more thermometers that detect ambient temperature), a humidity sensor component, a pressure sensor component (e.g., a barometer), an acoustic sensor component (e.g., one or more microphones that detect background noise), a proximity sensor component (e.g., an infrared sensor that detects nearby objects), a gas sensor (e.g., a gas detection sensor for detecting hazardous gas concentrations to ensure safety or to measure pollutants in the atmosphere), or other components that can provide indications, measurements, or signals corresponding to the surrounding physical environment. The position component 1238 includes a position sensor component (e.g., a GPS receiver component), an altitude sensor component (e.g., an altimeter or barometer that detects air pressure from which altitude can be derived), a direction sensor component (e.g., a magnetometer), etc.

[0111] A variety of technologies can be used to implement communications. The I / O components 1242 also include a communication component 1240 that is operable to couple the machine 1200 to the network 1220 or the device 1222 via a coupler 1224 and a coupler 1226, respectively. For example, the communication component 1240 may include a network interface component or another suitable device that interfaces with the network 1220. In further examples, the communication component 1240 may include a wired communication component, a wireless communication component, a cellular communication component, a near field communication (NFC) component, Components (e.g. Low Energy), Components and other communication components to provide communication through other means. Device 1222 can be another machine or any of a variety of peripheral devices (e.g., a peripheral device coupled via USB).

[0112] In addition, the communication component 1240 can detect an identifier or include a component operable to detect an identifier. For example, the communication component 1240 can include a radio frequency identification (RFID) tag reader component, an NFC smart tag detection component, an optical reader component (e.g., an optical sensor for detecting a one-dimensional barcode, such as a universal product code (UPC) barcode, a multi-dimensional barcode, and other optical codes), or an acoustic detection component (e.g., a microphone for identifying a tag audio signal). In addition, various information can be derived through the communication component 1240, such as a location via Internet Protocol (IP) geolocation, a location via Internet Protocol (IP), ... signal triangulation, location by detecting NFC beacon signals that may indicate a specific location, etc. Any of the above sensors, processors, or other components or circuits may include or use reference signal generator circuits and / or correction circuits as described herein.

[0113] Various memories (e.g., memory 1204, main memory 1212, static memory 1214, and / or memory of processor 1202) and / or storage unit 1216 may store one or more sets of instructions and data structures (e.g., software) that embody or are used by any one or more of the methods or functions described herein. These instructions (e.g., instructions 1208) when executed by processor 1202 cause various operations to implement the disclosed embodiments.

[0114] Instructions 1208 can be sent or received over network 1220 using a transmission medium via a network interface device (e.g., a network interface component included in communication component 1240), and using any of a number of well-known transmission protocols (e.g., Hypertext Transfer Protocol (HTTP)). Similarly, instructions 1208 can be sent or received to device 1222 using a transmission medium via coupling 1226 (e.g., a peer-to-peer coupling).

[0115] Various aspects of the present invention described herein as examples can help provide solutions to the package stress issues identified herein. For example, Example 1 is a method comprising: measuring a first electrical signal from a first node of a Hall plate, the first electrical signal responsive to a first stimulus and indicative of a carrier mobility characteristic of a semiconductor device in a first direction, and measuring a second electrical signal from a second node of the Hall plate, the second electrical signal responsive to a second stimulus and indicative of a carrier mobility characteristic of the semiconductor device in the same first direction; and determining a physical stress indicator for a semiconductor device including the Hall plate based on a relationship between the first electrical signal and the second electrical signal.

[0116] In Example 2, the subject matter of Example 1 can include providing a first stimulus at a second node of the Hall plate and, in response, measuring the first electrical signal; and providing a second stimulus at the first node of the Hall plate and, in response, measuring the second electrical signal.

[0117] In Example 3, the subject matter of Example 2 can include the Hall plate comprising a doped semiconductor symmetric about a first axis extending between the first nodes and symmetric about a second axis extending between the second nodes.

[0118] In Example 4, the subject matter of any one or more of Examples 2-3 may include: measuring a first electrical signal includes measuring a first voltage signal, and wherein the first stimulus includes a first current signal, and the first stimulus may include the first current signal; and measuring a second electrical signal includes measuring a second voltage signal, and the second stimulus may include a second current signal.

[0119] In Example 5, the subject matter of Example 4 can include providing the first and second current signals at respective different times, and the first and second current signals can have a common amplitude characteristic.

[0120] In Example 6, the subject matter of any one or more of Examples 4-5 can include: determining the physical stress indicator includes: summing information about the amplitudes of the first and second voltage signals to provide a voltage sum; and determining a resistance characteristic of a portion of the Hall plate using the voltage sum and the information about the amplitudes of the first and second current signals; and determining the physical stress indicator (e.g., including information about the magnitude of the physical stress on the Hall plate) using the determined resistance characteristic.

[0121] In Example 7, the subject matter of any one or more of Examples 2-6 may include: measuring the first electrical signal includes measuring a first current signal, and the first stimulation may include a first voltage signal; and measuring the second electrical signal may include measuring a second current signal, and the second stimulation may include a second voltage signal.

[0122] In Example 8, the subject matter of Example 7 can include providing the first and second voltage signals at respective different times.

[0123] In Example 9, the subject matter of any one or more of Examples 1-8 can include measuring the first and second electrical signals including measurement information about a same off-diagonal charge carrier mobility component of the Hall plate.

[0124] In Example 10, the subject matter of any one or more of Examples 1-9 can include providing a correction signal corresponding to a magnitude or direction of stress indicated by the physical stress indicator.

[0125] In Example 11, the subject matter of any one or more of Examples 1-10 may include: determining an absolute resistance characteristic of the Hall plate; and determining an off-diagonal resistance characteristic of the Hall plate based on the measured first and second electrical signals; and providing a temperature compensation signal based on a ratio of the off-diagonal resistance characteristic to the absolute resistance characteristic of the Hall plate.

[0126] Example 12 is a stress sensor comprising: a semiconductor device including a Hall plate having first and second pairs of signal nodes; an excitation circuit configured to provide an excitation signal to the Hall plate using the first or second pair of nodes; and a processor circuit configured to: receive information about a first electrical signal measured at the first pair of signal nodes and responsive to a first portion of the excitation signal, the first electrical signal indicating a charge carrier mobility characteristic of the semiconductor device in a first direction; and receive information about a second electrical signal measured at the second pair of signal nodes and responsive to a second portion of the excitation signal, the second electrical signal indicating a charge carrier mobility characteristic of the semiconductor device in the same first direction. Example 12 may include or utilize the processor circuit to determine a physical stress indicator for the semiconductor device based on a relationship between the first and second electrical signals.

[0127] In Example 13, the subject matter of Example 12 can include the Hall plate being symmetric about a first axis extending between the first pair of nodes and symmetric about a second axis extending between the second pair of nodes, and wherein the first axis is orthogonal to the second axis.

[0128] In Example 14, the subject matter of any one or more of Examples 12-13 can include the excitation circuit being configured to provide the first and second portions of the excitation signal at respective different times.

[0129] In Example 15, the subject matter of Example 14 can include the excitation circuit being configured to provide a first portion of the excitation signal at the second pair of nodes, and the excitation circuit being configured to provide a second portion of the excitation signal at the first pair of nodes.

[0130] In Example 16, the subject matter of Example 15 can include a multiplexer circuit configured to couple the excitation circuit to the Hall plate node.

[0131] In Example 17, the subject matter of any one or more of Examples 12-16 can include: the processor circuit being configured to: sum information about the amplitudes of the first and second electrical signals to provide a voltage sum; and using the voltage sum and information about the amplitude of the excitation signal, determine a resistance characteristic of a portion of the Hall plate; and using the determined resistance characteristic to determine a physical stress indicator (e.g., including information about the magnitude of physical stress on the Hall plate).

[0132] In Example 18, the subject matter of any one or more of Examples 12-17 may include the processor circuit being configured to provide a package stress compensation signal corresponding to a magnitude or direction of stress indicated by the physical stress indicator.

[0133] Example 19 is a non-transitory processor-readable medium comprising instructions that, when executed, cause a processor circuit to: control an excitation circuit to provide time-multiplexed first and second current signals to respective nodes of a Hall plate; and measure first and second voltage signals from the Hall plate nodes in response to the first and second current signals; and simultaneously determine an off-diagonal charge carrier mobility characteristic of the Hall plate using the measured first and second voltage signals; and provide a physical stress indicator regarding a magnitude and direction of physical stress on the Hall plate.

[0134] In Example 19, the subject matter of Example 19 can include instructions for causing a processor circuit to generate a stress compensation signal based on a physical stress indicator.

[0135] Example 21 is a method comprising providing an excitation signal to an emitter of a first bipolar transistor device, the transistor device comprising first and second different collectors coupled to a base region of the transistor device. In Example 21, the method may include measuring a first collector current from the first collector of the transistor device in response to the excitation signal, and measuring a second collector current from the second collector of the transistor device in response to the excitation signal, and determining a magnitude difference between the first and second collector currents. The magnitude difference may correspond to a carrier mobility characteristic of the base region of the transistor device, and the method may further include determining a physical stress indicator for the transistor device based on the magnitude difference between the first and second collector currents.

[0136] In Example 22, the subject matter of Example 21 can include simultaneously measuring the first and second collector currents in response to the same excitation signal.

[0137] In Example 23, the subject matter of Example 22 can include measuring the first and second collector currents, including measuring a carrier mobility characteristic of a first current flow direction through a base region of a transistor.

[0138] In Example 24, the subject matter of any one or more of Examples 21-21 can include using information about a base emitter voltage (Vbe or Vbe) of a transistor device to provide a voltage reference signal.

[0139] In Example 25, the subject matter of any one or more of Examples 21-24 may include determining a physical stress indicator, including determining a current deflection characteristic in a base region of a transistor device, the current deflection characteristic corresponding to a physical stress on a semiconductor comprising the transistor device.

[0140] In Example 26, the subject matter of any one or more of Examples 21-25 may include measuring first and second collector currents, including sensing base-emitter voltage information from a first side of a transistor device corresponding to the first collector, and sensing base-emitter stress information from a second side of the transistor device corresponding to the second collector, the voltage information representing a carrier mobility tensor describing deformation of the transistor device under stress.

[0141] In Example 27, the subject matter of any one or more of Examples 21-26 can include providing a reference voltage or current signal using a bandgap reference generator circuit including a transistor device.

[0142] In Example 28, the subject matter of Example 27 can include providing a signal indicative of a physical stress indicator in a time-multiplexed manner with a reference voltage or current signal.

[0143] In Example 29, the subject matter of any one or more of Examples 27-28 can include providing a signal indicative of a physical stress indicator concurrently with the reference voltage or current signal.

[0144] In Example 30, the subject matter of any one or more of Examples 21-29 can include providing a reference voltage or current signal using a bandgap-type reference generator circuit that includes a substrate that is shared (eg, at least partially shared) with a substrate of a transistor device.

[0145] Example 31 is a semiconductor stress sensor comprising: a bipolar transistor device including first and second collector terminals, and an excitation circuit configured to provide an excitation signal to a base-emitter junction of the bipolar transistor device, and a processor circuit configured to: receive information about a first collector signal measured at the first collector terminal, the first collector signal responsive to the excitation signal, and a first collector signal indicative of a carrier mobility characteristic of the bipolar transistor device in a first direction, and receive information about a second collector signal measured at the second collector terminal, the second collector signal responsive to the excitation signal, and a second collector signal indicative of a carrier mobility characteristic of the semiconductor device in the same first direction, and determine a physical stress indicator regarding the semiconductor device based on a relationship between the first and second collector signals.

[0146] In Example 32, the subject matter of Example 31 can include first and second collector signals indicative of carrier mobility characteristics in a base region of a bipolar transistor device.

[0147] In Example 31, the subject matter of any one or more of Examples 31-32 can include an emitter region, a base region, and a collector region of a bipolar transistor device layered in a second direction orthogonal to the first direction.

[0148] In Example 34, the subject matter of any one or more of Examples 31-31 may include a processor circuit configured to receive information about the first and second collector signals in response to a same stimulus signal.

[0149] In Example 35, the subject matter of any one or more of Examples 31-34 can include determining a physical stress indicator including determining a current signal amplitude difference between the first and second collector signals.

[0150] In Example 36, the subject matter of Example 35 can include an amplitude difference between first and second collector signals corresponding to a charge flow deflection in a base region of a bipolar transistor device.

[0151] In Example 37, the subject matter of any one or more of Examples 31-36 can include a reference signal generator circuit including a plurality of other transistors, and the plurality of other transistors and the bipolar transistor device include at least a portion of a shared substrate.

[0152] In Example 38, the subject matter of any one or more of Examples 31-37 can include a bipolar transistor device including a portion of a reference signal generator circuit, and the reference signal generator can be configured to provide a reference signal using information about a base emitter voltage (Vbe) of the bipolar transistor device.

[0153] In Example 39, the subject matter of any one or more of Examples 31-38 can include first and second collector terminals disposed on opposite sides of an emitter terminal of the bipolar transistor device.

[0154] In Example 40, the subject matter of any one or more of Examples 31-39 may include a surface of a bipolar transistor device comprising an emitter terminal surrounded by a base terminal, and first and second collector terminals are separated from the emitter terminal by the base terminal, and the first collector terminal and the second collector terminal are electrically decoupled on the surface.

[0155] Example 41 is a reference signal generator circuit comprising: a first bandgap reference generator circuit including a first portion of a semiconductor component and configured to provide an uncorrected reference voltage signal; a bipolar transistor device including first and second collector terminals, the bipolar transistor device having a substrate shared with the first portion of the semiconductor component; and an excitation circuit configured to provide an excitation signal to an emitter terminal of the bipolar transistor device. Example 41 may include a processor circuit configured to: receive information about a first collector signal measured at the first collector terminal, the first collector signal responsive to the excitation signal, and a first collector signal indicating a carrier mobility characteristic of the bipolar transistor device in a first direction; receive information about a second collector signal measured at the second collector terminal, the second collector signal responsive to the excitation signal, and a second collector signal indicating a carrier mobility characteristic of the semiconductor device in the same first direction; determine a physical stress indicator for the semiconductor device based on a relationship between the first and second collector signals; and provide a corrected voltage reference signal based on the uncorrected reference voltage signal and the physical stress indicator.

[0156] In Example 42, the subject matter of Example 41 can include a processor circuit configured to determine a physical stress indicator based on a current magnitude difference between the first and second collector signals.

[0157] In Example 41, the subject matter of any one or more of Examples 41-42 may include first and second collector signals indicative of carrier mobility characteristics in a base region of a bipolar transistor device, wherein the carrier mobility characteristics vary depending on mechanical stress applied to the semiconductor component.

[0158] In Example 44, the subject matter of any one or more of Examples 41-41 can include an uncorrected reference voltage signal based on a base-emitter voltage characteristic of a bipolar transistor device.

[0159] Example 45 is at least one machine-readable medium comprising instructions that, when executed by a processing circuit, cause the processing circuit to perform operations to implement any one or more of Examples 1-44.

[0160] Example 46 is a device comprising the device of any one or more of Examples 1-44.

[0161] Example 47 is a system of any one or more of Examples 1-44.

[0162] Example 48 is the method of any one or more of Examples 1-44.

[0163] Each of these non-limiting examples can stand on its own or can be combined in various permutations or combinations with one or more of the other examples or features discussed elsewhere herein.

[0164] This detailed description includes reference to the accompanying drawings that form a part of the detailed description. The accompanying drawings show specific embodiments in which the present invention can be implemented by way of illustration. These embodiments are also referred to as "examples" in this article. Such examples may include elements other than those shown or described. However, the inventors have also considered examples that only provide those shown or described elements. The inventors have considered examples using any combination or arrangement of those elements (or one or more aspects thereof) shown or described, or with respect to a specific example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0165] In this document, as is common in patent documents, the terms "a" or "some" are used to include one or more, independent of any other instances or uses of "at least one" or "one or more." In this document, the term "or" is used to represent a non-exclusive or, so that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In this document, the terms "including" and "in which" are used as synonyms for the respective terms "comprising" and "wherein."

[0166] In the following claims, the terms "including" and "comprising" are intended to be open-ended, meaning that systems, apparatus, articles, compositions, formulations, or processes that include elements in addition to the elements listed after the term in a claim are still considered to be within the scope of the claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0167] The method examples described herein may be implemented at least in part by a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions that are operable to configure an electronic device to perform a method or circuit operation or circuit configuration instruction as described in the above examples. The implementation of such a method may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, in an example, the code may be tangibly stored on one or more volatile, non-temporary or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, a hard disk, a removable disk, a removable optical disk (e.g., an optical disk and a digital video disk), a magnetic tape, a memory card or memory stick, a random access memory (RAM), a read-only memory (ROM), etc.

[0168] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by a person of ordinary skill in the art after reading the above description. The abstract is provided to enable the reader to quickly determine the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the disclosure. This should not be interpreted to mean that unclaimed disclosed features are essential to any claim. On the contrary, the subject matter of the invention may not lie in all the features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description as examples or embodiments, each claim existing independently as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or arrangements. The scope of the invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A method for providing a physical stress indicator using a bipolar transistor device, comprising: providing a drive signal to an emitter of a first bipolar transistor device, the transistor device including a first collector coupled to a base region of the transistor device and a different second collector; measuring a first collector current from a first collector of the transistor device in response to the stimulus signal; measuring a second collector current from a second collector of the transistor device in response to the excitation signal; determining a magnitude difference between the first collector current and the second collector current, wherein the magnitude difference corresponds to a carrier mobility characteristic of a base region of the transistor device; and The physical stress indicator for the transistor device is determined based on a difference in magnitude between the first collector current and a second collector current. 2 . The method for providing a physical stress indicator using a bipolar transistor device according to claim 1 , comprising measuring the first collector current and the second collector current simultaneously in response to a same stimulus signal.

3. The method for providing a physical stress indicator using a bipolar transistor device according to claim 2, wherein measuring the first collector current and the second collector current comprises measuring a carrier mobility characteristic of the first current flow direction through a base region of the transistor. 4 . The method for providing a physical stress indicator using a bipolar transistor device according to claim 1 , comprising using information about a base emitter voltage of the transistor device to provide a voltage reference signal.

5. The method for providing a physical stress indicator using a bipolar transistor device according to claim 1 , wherein determining the physical stress indicator comprises determining a current deflection characteristic in a base region of the transistor device, the current deflection characteristic corresponding to the physical stress on the semiconductor including the transistor device.

6. The method for providing a physical stress indicator using a bipolar transistor device according to claim 1 , wherein measuring the first collector current and the second collector current comprises sensing base-emitter voltage information from a first side of the transistor device corresponding to the first collector and sensing base-emitter voltage information from a second side of the transistor device corresponding to the second collector, the voltage information representing a carrier mobility tensor describing deformation of the transistor device under stress. 7 . The method for providing a physical stress indicator using a bipolar transistor device according to claim 1 , further comprising providing a reference voltage or current signal using a bandgap reference generator circuit including the transistor device. 8 . The method for providing a physical stress indicator using a bipolar transistor device according to claim 7 , further comprising providing a signal indicative of the physical stress indicator in a time multiplexed manner with the reference voltage or current signal. 9 . The method for providing a physical stress indicator using a bipolar transistor device according to claim 7 , further comprising providing a signal indicative of the physical stress indicator simultaneously with the reference voltage or current signal.

10. The method for providing a physical stress indicator using a bipolar transistor device according to claim 1, further comprising providing a reference voltage or current signal using a bandgap type reference generator circuit including a substrate common to a substrate of the transistor device.

11. A semiconductor stress sensor, comprising: a bipolar transistor device comprising a first collector terminal and a second collector terminal; a drive circuit configured to provide a drive signal to a base-emitter junction of the bipolar transistor device; and The processor circuit is configured to: receiving information about a first collector signal measured at a first collector terminal, the first collector signal being responsive to the stimulus signal and indicative of a carrier mobility characteristic of the bipolar transistor device in a first direction; receiving information about a second collector signal measured at a second collector terminal, the second collector signal being responsive to the stimulus signal and indicative of a carrier mobility characteristic of the bipolar transistor device in the same first direction; and A physical stress indicator for the bipolar transistor device is determined based on a relationship between the first collector signal and the second collector signal. 12 . The semiconductor stress sensor of claim 11 , wherein the first collector signal and the second collector signal are indicative of carrier mobility characteristics in a base region of a bipolar transistor device. 13 . The semiconductor stress sensor of claim 11 , wherein the emitter region, the base region, and the collector region of the bipolar transistor device are layered in a second direction orthogonal to the first direction. 14 . The semiconductor stress sensor of claim 11 , wherein the processor circuit is configured to receive information about the first collector signal and the second collector signal in response to a same excitation signal.

15. The semiconductor stress sensor of claim 11 , wherein determining the physical stress indicator comprises determining a current signal amplitude difference between a first collector signal and a second collector signal, and wherein the amplitude difference between the first collector signal and the second collector signal corresponds to a charge flow deflection in a base region of the bipolar transistor device. 16 . The semiconductor stress sensor of claim 11 , further comprising a reference signal generator circuit comprising a plurality of other transistors, wherein the plurality of other transistors and the bipolar transistor device comprise a shared substrate.

17. The semiconductor stress sensor of claim 11, wherein the bipolar transistor device comprises a portion of a reference signal generator circuit, and wherein the reference signal generator circuit is configured to provide a reference signal using information about a base-emitter voltage of the bipolar transistor device.

18. The semiconductor stress sensor of claim 11, wherein a surface of the bipolar transistor device includes an emitter terminal surrounded by a base terminal, and wherein the first collector terminal and the second collector terminal are separated from the emitter terminal by the base terminal, and the first collector terminal and the second collector terminal are electrically decoupled on the surface.

19. A reference signal generator circuit comprising: a first bandgap reference generator circuit comprising a first portion of semiconductor components and configured to provide an uncorrected reference voltage signal; a bipolar transistor device comprising a first collector terminal and a second collector terminal, the bipolar transistor device having a shared substrate with the first portion of the semiconductor assembly; a drive circuit configured to provide a drive signal to an emitter terminal of the bipolar transistor device; and The processor circuit is configured to: receiving information about a first collector signal measured at a first collector terminal, the first collector signal being responsive to the stimulus signal and indicative of a carrier mobility characteristic of the bipolar transistor device in a first direction; receiving information about a second collector signal measured at a second collector terminal, the second collector signal being responsive to the stimulus signal and indicative of a carrier mobility characteristic of the bipolar transistor device in the same first direction; determining a physical stress indicator for the bipolar transistor device based on a relationship between the first collector signal and the second collector signal; and A corrected voltage reference signal is provided based on the uncorrected reference voltage signal and the physical stress indicator. 20 . The reference signal generator circuit of claim 19 , wherein the processor circuit is configured to determine the physical stress indicator based on a current amplitude difference between the first collector signal and the second collector signal.

21. The reference signal generator circuit of claim 19, wherein the uncorrected reference voltage signal is based on a base-emitter voltage characteristic of the bipolar transistor device.

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