A dynamically configurable clock signal generation device
By dynamically configuring the clock signal generation device, using arbitration and selection units to combine sub-units with the same address into modules, and using a start signal for unified control, the problem of inflexible configuration of clock signal generation devices in the prior art is solved, and circuit simplification and resource optimization are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 无锡亚科鸿禹电子有限公司
- Filing Date
- 2022-12-13
- Publication Date
- 2026-04-24
AI Technical Summary
Existing clock signal generation devices cannot be flexibly configured, resulting in complex circuit design and low resource utilization, and the startup of multiple clock signal generation circuits is cumbersome.
A dynamically configurable clock signal generation device is adopted. The arbitration unit groups sub-units with the same address into a group of clock modules, and the start-up unit enables the sub-units of the same group of clock modules to start simultaneously. Combined with the selection unit, different types of clock signal generation units are selected to meet different needs.
It enables flexible configuration of clock signals, reduces circuit complexity and resource consumption, simplifies the startup process, and meets the flexible configuration requirements of multiple clock signal generation circuits.
Smart Images
Figure CN115933810B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of clock signal generation technology, and more specifically to a dynamically configurable clock signal generation device. Background Technology
[0002] In logic circuits, clock signals are the foundation of sequential logic, used to determine when the state in a logic unit is updated. They are semaphores with a fixed period and are independent of operation. As the complexity of SOCs (System-on-a-Chip) increases, and the circuits on the SOC become more complex, the SOC's requirements for the selectivity of clock quantity and frequency become increasingly demanding, especially when different circuits require clock signals of different frequencies.
[0003] If a traditional clock signal generation device is used, that is, the corresponding clock signal generation circuit is integrated on the SOC to generate the clock signal of the required frequency, it will increase the circuit design, thereby increasing the circuit complexity and reducing resource utilization.
[0004] However, if each clock signal generating circuit is configured to output a clock signal of a corresponding frequency, the existing clock signal circuits are configured individually, which is not flexible. For example, when multiple clock signal generating circuits are configured to output the same clock signal, these clock signal generating circuits are started by different start signals in actual use, which is cumbersome and cannot be flexibly configured. Summary of the Invention
[0005] In view of the shortcomings of the prior art, the present invention provides a dynamically configurable clock signal generating device. The technical problem to be solved is that when multiple clock signal generating circuits generate clock signals, each clock signal generating circuit requires a different start signal to start, which cannot be flexibly configured.
[0006] To solve the above technical problems, the present invention provides the following technical solution: a dynamically configurable clock signal generating device, comprising...
[0007] A clock signal generation unit, comprising N sub-units, where N is greater than 1 and is a positive integer;
[0008] The address setting unit is configured to set the address of the sub-unit of the clock signal generating unit;
[0009] The arbitration unit is configured to group the sub-units with the same address as the clock signal generation unit as a group of clock modules;
[0010] The startup unit is configured to input a clock startup signal for each subunit to the arbitration unit. After receiving the clock startup signal, the arbitration unit will simultaneously start all subunits in the clock module where the subunit to be started is located.
[0011] In one implementation, when one subunit of the clock module stops outputting a clock signal, the remaining subunits in the same clock module also stop outputting clock signals at the same time.
[0012] In one implementation, the address setting unit begins setting the address of the sub-unit of the clock signal generating unit according to the address configuration data only after receiving the start configuration data. The address setting unit stops configuring the address of the sub-unit of the clock signal generating unit after receiving the end configuration data. When the address setting unit receives the clear configuration data, it clears the address of the sub-unit of the clock signal generating unit.
[0013] In one embodiment, the present invention further includes a configuration unit, which is used to acquire configuration data, the configuration data including address configuration data and clock configuration data, the address configuration data being written to the address setting unit, the address setting unit setting the address of the sub-unit of the clock signal generating unit according to the address configuration data, the clock configuration data being written to the sub-unit, and the sub-unit outputting a clock signal according to the clock configuration data.
[0014] In one embodiment, the present invention further includes a selection unit and at least two clock signal generation units. The configuration data further includes selection configuration data, which is written to the selection unit. The selection unit selects a clock signal generation unit from all clock signal generation units based on the selection configuration data. The arbitration unit treats the sub-units with the same address as the selected clock signal generation unit as a group of clock modules. When a sub-unit of the clock module of the selected clock signal generation unit receives a clock start signal, each sub-unit of the clock module simultaneously outputs a clock signal.
[0015] In one embodiment, the clock signal generation unit is an equal frequency divider, an unbalanced frequency divider disabled mixer, or an unbalanced frequency divider enabled mixer.
[0016] In one embodiment, the present invention includes M clock signal generation units, where M is a positive integer and greater than 2;
[0017] The selection configuration data includes M states. When the selection configuration data is in the first state, the selection unit selects the first clock signal generating unit, when the selection configuration data is in the second state, the selection unit selects the second clock signal generating unit, and so on, when the selection configuration data is in the Mth state, the selection unit selects the Mth clock signal generating unit.
[0018] In one embodiment, the present invention further includes a configuration data generation unit, which includes N configuration sub-units, each of which is used to configure the configuration data of the N sub-units.
[0019] In one embodiment, the present invention further includes N OR processing units, wherein the starting unit includes a first starting unit and a second starting unit. The first starting unit includes N first starting signal output terminals, and the second starting unit includes N second starting signal output terminals. The N first starting signal output terminals are respectively connected to the first input terminals of the N OR processing units, and the N second starting signal output terminals are respectively connected to the second input terminals of the N OR processing units. The signal output terminals of the N OR processing units are electrically connected to the N sub-units and are configured to input clock start signals to the sub-units.
[0020] The beneficial effects of this invention compared with the prior art are as follows: This invention configures an address for each sub-unit of the clock signal generation unit and uses an arbitration unit to group sub-units with the same address into a clock module. After the sub-units in the same group of clock modules receive the clock start signal, the sub-units in the same group of clock modules also output clock signals simultaneously. When multiple clock signals need to be output, since the sub-units with the same address will be grouped into the same group of clock modules, it is only necessary to let one sub-unit of the clock module output a clock signal to enable all sub-units in the clock module to output clock signals, thereby facilitating the start of the sub-units.
[0021] In addition, when multiple clock signal generation units are set up, and the clock signal generation units are configured as equal frequency dividers, unbalanced frequency divider disabled mixers, or unbalanced frequency divider enabled mixers, different clock requirements can be met in actual use by selecting a clock signal generation unit to output the corresponding clock signal through the selection unit. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of the first structure of the present invention in the embodiments;
[0023] Figure 2 This is a schematic diagram of the clock signal generation unit in the embodiment;
[0024] Figure 3 This is a schematic diagram showing the connection between the startup unit and the processing unit in the embodiment.
[0025] Figure 4 This is a schematic diagram of the second structure of the present invention in the embodiments;
[0026] Figure 5 This is a schematic diagram of the third structure of the present invention as an example. Detailed Implementation
[0027] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.
[0028] like Figure 1-2 As shown, a dynamically configurable clock signal generating device includes...
[0029] Clock signal generation unit 1, which includes 16 sub-units 10;
[0030] Address setting unit 2 is configured to set the address of subunit 10 of clock signal generation unit 1;
[0031] Arbitration unit 3 is configured to use sub-unit 10 with the same address as clock signal generation unit 1 as a group of clock modules;
[0032] The startup unit 4 is configured to input a clock startup signal for each subunit 10 to the arbitration unit 3. After receiving the clock startup signal, the arbitration unit 3 will start all subunits 10 in the clock module where the subunit 10 to be started is located simultaneously.
[0033] In practical use, the number of sub-units 10 of the clock signal generation unit 1 is not limited to 16. The number of sub-units 10 can be increased or decreased according to the actual number of clock signals required.
[0034] Taking this embodiment as an example, since the clock signal generation unit 1 has 16 sub-units 10, when all sub-units 10 have the same address, the clock signals output by the 16 sub-units 10 are the same. Therefore, when the 16 sub-units 10 are used as the same group of clock modules, as long as one sub-unit 10 receives the clock start signal, the 16 sub-units 10 can output clock signals simultaneously. Alternatively, when the 16 sub-units 10 output different clock signals, the addresses of the 16 sub-units 10 are all different, and only then is it necessary for the start unit 4 to output sixteen clock start signals. Therefore, by setting the address of the sub-units 10 and making the sub-units 10 with the same address a group of clock modules, when starting all the sub-units 10 in the same group of clock modules, only one sub-unit in the group of clock modules needs to be input with a clock start signal, which can reduce the resources occupied by all sub-units 10 when starting.
[0035] In this embodiment, after the arbitration unit 3 generates clock modules for corresponding groups of all sub-units 10, the sub-units 10 in each clock module not only output clock signals simultaneously, but also all sub-units 10 stop outputting clock signals when one of the sub-units 10 needs to stop outputting clock signals.
[0036] like Figure 3 As shown, in this embodiment, the start unit 4 includes a first start unit 40 and a second start unit 41. The first start unit 40 includes sixteen first start signal output terminals, namely start signal output terminal o100, start signal output terminal o101...start signal output terminal o115. The second start unit 41 includes sixteen second start signal output terminals, namely start signal output terminal o200, start signal output terminal o201...start signal output terminal o215. The sixteen first start signal output terminals are respectively connected to the first input terminals of the sixteen OR processing units 8, and the sixteen second start signal output terminals are respectively connected to the second input terminals of the sixteen OR processing units 8. The signal output terminals of the sixteen OR processing units 8 are electrically connected to the arbitration unit 3 and are configured to input the clock start signal of each subunit 10 to the arbitration unit 3.
[0037] for Figure 3 For the sake of simplicity, Figure 3 The diagram shows only the connection of the start signal output terminal o100, the start signal output terminal o200, and the OR processing unit 8. The OR processing unit 8 has two input terminals, used to OR the clock start signal output from the first start unit 40 and the clock start signal output from the second start unit 41. In practical use, to enable the sub-units in the clock signal generation unit 1 to be started through multiple start methods, multiple start units can be set. For example, a start signal with logic "1" can be output by setting the corresponding hardware circuit, or an operation unit with an operation interface can be set. By setting the corresponding sub-unit 10 to output a clock signal on the operation interface, the operation unit can output a start signal with logic "1". As long as the OR processing unit 8 receives a start signal with logic "1", it can output a clock start signal to the arbitration unit 3.
[0038] In one implementation, when a new startup method is required, the OR processing unit 8 can be selected as a three-input OR processing unit 8, a four-input OR processing unit 8, or an OR processing unit 8 with more inputs.
[0039] for Figure 3The first start unit 40 and the second start unit 41 are equipped with 16 first start signal output terminals and 16 second start signal output terminals to match the 16 sub-units 10. In actual use, when the number of sub-units 10 increases or decreases, the number of first start signal output terminals, second start signal output terminals and / or processing units 8 also need to be changed accordingly.
[0040] Reference Figure 4 The present invention also includes a configuration unit 5 and a configuration data generation unit 6. The configuration data generation unit 6 includes sixteen configuration sub-units, each of which is used to configure configuration data of the sixteen sub-units. The configuration data includes address configuration data and clock configuration data. The generated configuration data is sent to the configuration unit 5.
[0041] After configuration unit 5 obtains configuration data, configuration unit 5 writes address configuration data to address setting unit 2. Address setting unit 2 sets the address of sub-unit 10 of clock signal generation unit 1 according to address configuration data. Configuration unit 5 writes clock configuration data to sub-unit 10. Sub-unit 10 outputs clock signal according to clock configuration data.
[0042] In practical use, the clock signal output by each subunit 10 is set through each configuration subunit. Furthermore, the number of configuration subunits needs to be adjusted accordingly when the number of subunits 10 increases or decreases.
[0043] Reference Figure 5 ,like Figure 5 The invention shown also includes a selection unit 7 and three clock signal generation units 1. The configuration data also includes selection configuration data. The configuration unit 5 writes the selection configuration data to the selection unit 7. The selection unit 7 selects one clock signal generation unit 1 from all the clock signal generation units 1 according to the selection configuration data. The arbitration unit 3 takes the sub-units 10 with the same address as the selected clock signal generation unit 1 as a group of clock modules. When a sub-unit 10 of the clock module of the selected clock signal generation unit 1 receives a clock start signal, each sub-unit 10 of the clock module simultaneously outputs a clock signal.
[0044] In actual use, the process of configuring the address of each subunit 10 by address setting unit 2 is as follows:
[0045] Address setting unit 2 only starts setting the address of sub-unit 10 of clock signal generation unit 1 according to the address configuration data after receiving the start configuration data. Address setting unit 2 stops configuring the address of sub-unit 10 of clock signal generation unit 1 after receiving the end configuration data. Address setting unit 2 clears the address of sub-unit 10 of clock signal generation unit 1 when receiving clear configuration data.
[0046] In practical applications, by setting multiple clock signal generation units 1 and allowing these units to select different types of clock generators, different types of clock signals can be generated, thus meeting complex clock signal requirements. The clock signal generation unit 1 can be an equalizer, an unbalanced divider with no enable mixer, or an unbalanced divider with enable mixer. Figure 5 The three clock signal generation units 1 are an equalizer, an unbalanced divider disable mixer, and an unbalanced divider enable mixer, respectively, through... Figure 5 The three clock signal generation units 1 shown can satisfy the dynamic allocation of groups for various frequency division methods such as integer, fractional, equal, and unbalanced.
[0047] In one implementation, the number of clock signal generation units 1 can be increased according to the demand for the generated clock signal, and other types of signal generators can be selected for the clock signal generation units 1.
[0048] for Figure 5 Since there are only three clock signal generation units 1, only two bits of binary data are needed to select the three clock signal generation units 1. Therefore, the selection configuration data is two bits of binary data. When the selection configuration data is in the first state, the selection unit 7 selects the equalizer; when the selection configuration data is in the second state, it selects the unbalanced divider disabled mixer; and when the selection configuration data is in the third state, it selects the unbalanced divider enabled mixer. Specifically, the selection configuration data is "01" when it is in the first state, "10" when it is in the second state, and "11" when it is in the third state.
[0049] In practical use, when the number of clock signal generation units 1 is 5 or more but less than 9, the selection configuration data is 3 bits of binary data, which generates 8 states of selection configuration data. In some implementations, the selection configuration data can be set to more bits of binary data depending on the number of clock signal generation units 1.
[0050] for Figure 5 In this embodiment, the clock configuration data, address configuration data, and selection configuration data generated by the configuration data generation unit 6 are 48-bit binary data. Bits 0-3 are address configuration data, bits 4-31 are clock configuration data, bits 32-33 are selection configuration data, and bits 34-47 are spare bits. In practical use, when it is necessary to increase the number of bits in the clock configuration data, address configuration data, and selection configuration data, the 48-bit binary data can be adjusted by using spare bits. When the 48-bit configuration data is insufficient, a higher number of bits can be used.
[0051] In summary, this invention configures an address for each subunit 10 of the clock signal generation unit 1 and uses the arbitration unit 3 to group subunits 10 with the same address into a group of clock modules. After receiving the clock start signal, the subunits 10 in the same group of clock modules also output clock signals simultaneously. When multiple clock signals need to be output, since subunits with the same address are grouped into the same group of clock modules, it is only necessary to let one subunit of the clock module output a clock signal to enable all subunits in the clock module to output clock signals, thereby facilitating the start of the subunits.
[0052] In addition, when multiple clock signal generation units are set up, and the clock signal generation units are configured as equal frequency dividers, unbalanced frequency divider disabled mixers, or unbalanced frequency divider enabled mixers, different clock requirements can be met in actual use by selecting a clock signal generation unit to output the corresponding clock signal through the selection unit.
[0053] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. A dynamically configurable clock signal generating device, characterized in that, include A clock signal generation unit, comprising N sub-units, where N is greater than 1 and is a positive integer; The address setting unit is configured to set the address of the sub-unit of the clock signal generating unit; The arbitration unit is configured to group the sub-units with the same address as the clock signal generation unit as a group of clock modules; The startup unit is configured to input a clock startup signal for each subunit to the arbitration unit. After receiving the clock startup signal, the arbitration unit will simultaneously start all subunits in the clock module where the subunit to be started is located. It also includes a configuration unit, which is used to acquire and distribute configuration data. The configuration data includes address configuration data and clock configuration data. The configuration unit writes the address configuration data to the address setting unit. The address setting unit sets the address of the sub-unit of the clock signal generating unit according to the address configuration data. The configuration unit writes the clock configuration data to the sub-unit. The sub-unit outputs a clock signal according to the clock configuration data. The address setting unit only begins setting the address of the sub-unit of the clock signal generating unit according to the address configuration data after receiving the start configuration data. The address setting unit stops configuring the address of the sub-unit of the clock signal generating unit after receiving the end configuration data. The address setting unit clears the address of the sub-unit of the clock signal generating unit when it receives the clear configuration data.
2. The dynamically configurable clock signal generating device according to claim 1, characterized in that, When one subunit in the clock module stops outputting a clock signal, the remaining subunits in the same clock module also stop outputting clock signals at the same time.
3. The dynamically configurable clock signal generating device according to claim 1, characterized in that, It also includes a selection unit, and the number of clock signal generation units is at least two. The configuration data also includes selection configuration data. The configuration unit writes the selection configuration data into the selection unit. The selection unit selects a clock signal generation unit from all clock signal generation units according to the selection configuration data. The arbitration unit takes the sub-units with the same address as the selected clock signal generation unit as a group of clock modules. When a sub-unit of the clock module of the selected clock signal generation unit receives a clock start signal, each sub-unit of the clock module outputs a clock signal simultaneously.
4. The dynamically configurable clock signal generating device according to claim 3, characterized in that, The clock signal generation unit is an equal frequency divider, an unbalanced frequency divider with no enable mixer, or an unbalanced frequency divider with enable mixer.
5. The dynamically configurable clock signal generating device according to claim 4, characterized in that, It includes M clock signal generation units, where M is a positive integer and greater than 2; The selection configuration data includes M states. When the selection configuration data is in the first state, the selection unit selects the first clock signal generating unit, when the selection configuration data is in the second state, the selection unit selects the second clock signal generating unit, and so on, when the selection configuration data is in the Mth state, the selection unit selects the Mth clock signal generating unit.
6. The dynamically configurable clock signal generating device according to claim 3, characterized in that, It also includes a configuration data generation unit, which comprises N configuration sub-units, each of which is used to configure the configuration data of its respective sub-unit.
7. The dynamically configurable clock signal generating device according to claim 1, characterized in that, It also includes N OR processing units. The startup unit includes a first startup unit and a second startup unit. The first startup unit includes N first startup signal output terminals, and the second startup unit includes N second startup signal output terminals. The N first startup signal output terminals are respectively connected to the first input terminals of the N OR processing units, and the N second startup signal output terminals are respectively connected to the second input terminals of the N OR processing units. The signal output terminals of the N OR processing units are electrically connected to the N sub-units and are configured to input clock startup signals to the sub-units.
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