A design method for an OPB bus to APB bus bridge

Abstract

This invention provides a design method for an OPB bus to APB bus bridge. The OPB bus to APB bus bridge converts signals conforming to OPB bus requests into APB-compliant signals using control signal conversion logic. Similarly, it converts signals conforming to the APB bus protocol into OPB-compliant signals using response signal conversion logic. Both the APB and OPB ends share the same clock. The APB bus protocol is the APB4 bus protocol. Both the write data conversion in the control signal conversion logic and the read data conversion in the response signal conversion logic support byte order conversion. The advantages of this invention are: by converting the OPB bus standard to the APB bus standard through the OPB bus to APB bus bridge, it enables the integration of an APB bus IP into an OPB bus system, enhancing the reusability of IP modules and accelerating system design and integration.

Description

Technical Field

[0001] This invention belongs to the field of register interfaces, and in particular relates to a design method for an OPB bus to APB bus bridge. Background Technology

[0002] The On-Chip Peripheral Bus (OPB) and Advanced Peripheral Bus (APB) are important register configuration interfaces in system-on-a-chip (SoC) modules. In fields with high system stability requirements, such as industrial control and aerospace, IBM's PowerPC processors have widespread application needs. These systems mostly adopt a PLB+OPB bus architecture, with low-speed IPs largely integrated on the OPB bus. In embedded SoCs, the AMBA bus architecture dominates, resulting in many IPs using AMBA interfaces. For low-speed IPs, most use the APB bus interface. Current technology cannot meet the need to integrate APB-interface IPs into a PLB+OPB bus architecture. Summary of the Invention

[0003] In view of this, the present invention aims to propose a design method for an OPB bus to APB bus bridge, in order to solve the problem that the existing technology cannot integrate the IP of the APB interface into the PLB+OPB bus architecture.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] First aspect: A design method for an OPB bus to APB bus bridge;

[0006] The OPB bus to APB bus bridge converts the received control signals, address signals, and write data signals that conform to the OPB bus request into control signals, address signals, and write data signals that conform to the APB bus protocol through control signal conversion logic.

[0007] The OPB bus to APB bus bridge converts the received acknowledgment signals and read data signals conforming to the APB bus protocol into acknowledgment signals and read data signals conforming to the OPB bus protocol through acknowledgment signal conversion logic.

[0008] The APB and OPB terminals share the same clock.

[0009] Both the write data conversion in the control signal conversion logic and the read data conversion in the response signal conversion logic support byte order conversion.

[0010] Furthermore, the control signal conversion logic performs state transitions through a state machine;

[0011] The states of the control signal conversion logic are: IDLE, Setup, Access, and Timeout.

[0012] Furthermore, the IDLE state is a state without bus transmission operation;

[0013] When the OPB bus request is valid, the state changes to Setup state; otherwise, it remains in IDLE state.

[0014] Furthermore, the Setup state is the APB bus transmission preparation state;

[0015] When in Setup state, the APB bus sets the bus select signal to 1 and records the data transmission SIZE for use by the response signal conversion logic.

[0016] Furthermore, the Access state refers to the APB bus transmission state;

[0017] When in Access state, APB writes or reads data and waits for the data transmission to complete. At the same time, it starts the transmission counter to begin counting, and the counting clock uses the module clock.

[0018] If data transmission ends, the state machine transitions to the IDLE state, and the transmission counter is cleared to zero.

[0019] If data transmission is not finished and the transmission counter is 10, the state machine transitions to the Timeout state.

[0020] Furthermore, the Timeout state is an APB bus transmission blocking state;

[0021] When in the Timeout state, if the APB device does not respond after 10 bus cycles, the OPB bus to the APB bus bridge will automatically respond, ensuring that the data transmission is complete and returning the bus transmission status as an error state. The state machine will then transition to the IDLE state.

[0022] Furthermore, if the state machine is in the Access state and the slave device ready signal at the APB end is 1, then the APB signal is converted into the OPB signal through the response signal conversion logic.

[0023] Furthermore, during the automatic response process, the APB bus protocol signal is converted into an OPB bus protocol signal recognizable by OPB through response signal conversion logic.

[0024] Second aspect: An electronic device including a processor and a memory communicatively connected to the processor and used to store processor-executable instructions, characterized in that: the processor is used to execute a design method for an OPB bus to APB bus bridge as described in any of the first aspects above.

[0025] Third aspect: A server, characterized in that: it includes at least one processor and a memory communicatively connected to the processor, the memory storing instructions executable by the at least one processor, the instructions being executed by the processor to cause the at least one processor to perform a design method for an OPB bus to APB bus bridge as described in any of the first aspects.

[0026] Compared with existing technologies, the design method of an OPB bus to APB bus bridge described in this invention has the following advantages:

[0027] The present invention discloses a design method for an OPB bus to APB bus bridge, which converts the OPB bus standard to the APB bus standard through the OPB bus to APB bus bridge, thereby integrating an APB bus IP into an OPB bus system, enhancing the reusability of IP modules and accelerating the system design and integration speed. Attached Figure Description

[0028] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0029] Figure 1 This is a schematic diagram of the OPB bus to APB bus bridge according to an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the control signal conversion logic state machine according to an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram illustrating the meaning of the OPB and APB read / write control signals according to an embodiment of the present invention.

[0032] Figure 4 This is a schematic diagram illustrating the meaning of the OPB write operation control signals according to an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram illustrating the meaning of the APB write operation control signals according to an embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of the pstrb generation logic described in an embodiment of the present invention;

[0035] Figure 7This is a schematic diagram of the pwdata generation logic according to an embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram of the generation logic of sin_xferack sin_dbusen according to an embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram of the sin_errack generation logic as described in an embodiment of the present invention;

[0038] Figure 10 This is a schematic diagram of the generation logic of sin_hwack and sin_fwack according to an embodiment of the present invention;

[0039] Figure 11 This is a schematic diagram of the sin_dbus generation logic according to an embodiment of the present invention. Detailed Implementation

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0041] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] Example 1:

[0043] like Figure 1 As shown: A design method for an OPB bus to APB bus bridge, which includes the following:

[0044] The OPB bus to APB bus bridge converts the received control signals, address signals, and write data signals that conform to the OPB bus request into control signals, address signals, and write data signals that conform to the APB bus protocol through control signal conversion logic.

[0045] The OPB bus to APB bus bridge converts the received acknowledgment signals and read data signals conforming to the APB bus protocol into acknowledgment signals and read data signals conforming to the OPB bus protocol through acknowledgment signal conversion logic.

[0046] The APB and OPB sides share the same clock.

[0047] Both the write data conversion in the control signal conversion logic and the read data conversion in the response signal conversion logic support byte order conversion.

[0048] The main function of the control signal conversion logic is to convert the OPB signals: opb_select, opb_rnw, opb_hwxfer, opb_fwxfer, opb_abus, opb_dbus and the timing number into APB signals: psel, penable, paddr, pwrite, pstrb, pwdata.

[0049] The main function of the response signal conversion logic is to convert the APB signals preready, prdata, pslverr and the timing number into OPB signals: sin_xferack, sin_hwack, sin_fwack, sin_errack, sin_dbus, and sin_dbusen.

[0050] like Figure 2 As shown: The control signal conversion logic uses a state machine to perform state transitions, with the states being: IDLE, Setup, Access, and Timeout.

[0051] like Figure 2 , Figure 3 As shown: IDLE represents the no-bus-transfer operation state. When an OPB bus request (opb_select) is valid, the state transitions to Setup; otherwise, it remains in IDLE. paddr equals opb_abus registers the first-level output, and paddr maintains word alignment. pwrite equals opb_rnw inverted and registers the first-level output.

[0052] For write operations, such as Figure 4 , Figure 5 , Figure 6 As shown: Functionally, pstrb is derived from the decoding of opb_hwxfer, opb_fwxfer, opb_rnw, and opb_abus[1:0]. In terms of timing, pstrb is the first-level output of the registers opb_hwxfer, opb_fwxfer, opb_rnw, and opb_abus.

[0053] like Figure 7 As shown: Functionally, pwdata is obtained by selecting opb_dbus from opb_hwxfer, opb_fwxfer, opb_rnw, opb_abus[1:0], and BE (endian control logic). In terms of timing, pwdata is equal to the first-level output of the opb_dbus register.

[0054] For read operations, pstrb is an invalid value, while pwdata can retain the value from the previous cycle.

[0055] like Figure 1 , Figure 2 As shown: Setup, is the preparatory state for APB bus transmission. In this state, psel=1 is output. In addition, paddr, pwrite, pwdata, and pstrb are also valid in this state. At the same time, the data transmission SIZE (word transmission, half-word transmission, byte transmission) should be recorded here for use by the response signal conversion logic (set as transfer_size).

[0056] Access is the transmission state of the APB bus. In this state, penable=1, psel, paddr, pwrite, pwdata, and pstrb remain unchanged from the previous cycle. During this phase, data is written to or read from the APB slave and the system waits for the data transmission to complete. At the same time, the transmission counter is started to count, and the counting clock uses the module clock.

[0057] If the state machine waits until apb_ready equals 1, it means that the APB slave data transmission is complete, the state machine returns to the IDLE state, and the transmission counter is cleared.

[0058] If the wait-to-transfer counter is 10 and apb_ready is not equal to 1, the state machine transitions to the TimeOut state.

[0059] TimeOut is the APB bus transmission blocking state. This state increases the robustness of the design. Its function is that if the APB device does not respond for a long time (set to 10 bus cycles), OPB2APB will automatically reply with a response and data to ensure the completion of the bus transmission and return the bus transmission status to the error state. The state machine will then jump to the IDLE state.

[0060] The state machine (FSM) is equal to Access and prepared is equal to 1, or the state machine (FSM) is equal to Timeout and the transmission counter is equal to 10. The APB end converts the APB signal into the OPB signal through the response signal conversion logic.

[0061] like Figure 8 As shown: pready_tout is the cycle of the state machine in the Timeout state and the transmission counter is equal to 10. When pready is equal to 1 or the state machine is in the Timeout state and the transmission counter is equal to 10, the next cycle sin_xferack and sin_dbusen are equal to 1.

[0062] like Figure 9 As shown: pslverr_tout is the cycle in which the state machine is in the Timeout state and the transmission counter is equal to 10. When pslverr is equal to 1 or the state machine is in the Timeout state and the transmission counter is equal to 10, the next cycle sin_errack is equal to 1.

[0063] like Figure 10 As shown: transfer_size is the data transfer size recorded by the state machine in the Setup state.

[0064] like Figure 11 As shown: sin_dbus is selected by opb_hwxfer, opb_fwxfer, opb_rnw, opb_abus[1:0], and BE (endian control logic) to obtain prdata.

[0065] Example 2: An electronic device includes a processor and a memory communicatively connected to the processor and used to store executable instructions of the processor. The processor is used to execute a design method for an OPB bus to APB bus bridge as described in any of Examples 1 above.

[0066] Example 3: A server includes at least one processor and a memory communicatively connected to the processor. The memory stores instructions executable by the at least one processor. The instructions are executed by the processor to cause the at least one processor to perform a design method for an OPB bus to APB bus bridge as described in any of Examples 1.

[0067] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0068] In the several embodiments provided in this application, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the division of units described above is merely a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The aforementioned units may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention according to actual needs.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A design method of an OPB bus to APB bus bridge, characterized in that: the OPB bus to APB bus bridge converts the received control signals, address signals and write data signals conforming to the OPB bus request into control signals, address signals and write data signals conforming to the APB bus protocol through control signal conversion logic; the OPB bus to APB bus bridge converts the received response signals and read data signals conforming to the APB bus protocol into response signals and read data signals conforming to the OPB bus protocol through response signal conversion logic; the APB end and the OPB end share the same clock; the write data conversion in the control signal conversion logic and the read data conversion in the response signal conversion logic both support byte sequence conversion; the control signal conversion logic converts the OPB signals: opb_select, opb_rnw, opb_hwxfer, opb_fwxfer, opb_abus, opb_dbus and timing number into the APB signals: psel, penable, paddr, pwrite, pstrb and pwdata; the response signal conversion logic converts the APB signals: pready, prdata, pslverr and timing number into the OPB signals: sin_xferack, sin_hwack, sin_fwack, sin_errack, sin_dbus and sin_dbusen; the control signal conversion logic performs state conversion through a state machine; the states of the control signal conversion logic are: IDLE, Setup, Access and Timeout; the IDLE state is a state without bus transmission operation; when the OPB bus request is valid, the state is converted to the Setup state, otherwise the IDLE state remains unchanged; the Setup state is an APB bus transmission preparation state; when in the Setup state, the APB bus sets the bus selection signal to 1 and records the data transmission SIZE for use by the response signal conversion logic; the Access state is an APB bus transmission state; when in the Access state, the APB performs write data or read data and waits for the completion of data transmission, while starting the transmission counter to count, with the clock being the module clock; if the data transmission is completed, the state machine jumps to the IDLE state, while the transmission counter is cleared; if the data transmission is not completed and the transmission counter counts to 10, the state machine jumps to the Timeout state; the Timeout state is an APB bus transmission blocking state; when in the Timeout state, if the APB device does not feed back the response after 10 bus cycles, the OPB bus to APB bus bridge automatically replies to the response, while ensuring the completion of data bus transmission and returning the bus transmission state to an error state, and the state machine jumps to the IDLE state.

2. The method of claim 1, wherein: when the state machine is in the Access state and the APB slave ready signal is 1, the APB signals are converted to OPB signals by response signal conversion logic.

3. The method of claim 1, wherein: during the automatic reply response, the APB bus protocol signals are converted to OPB bus protocol signals recognizable by the OPB bus by response signal conversion logic.

4. A processor configured to perform the method of any one of claims 1-3.

5. A computer program product, comprising at least one computer-readable storage medium having instructions stored thereon, the instructions executable by a computer to cause the computer to perform the method of any one of claims 1-3.

4. An electronic device, comprising a processor and a memory connected to the processor in communication, and configured to store executable instructions of the processor, characterized in that: ​ 5. A server, characterized by: ​

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