GOA Circuit and Display Panel

Abstract

The GOA circuit and display panel provided by the embodiments of the present application. The GOA circuit includes a plurality of cascaded GOA units. Except for the starting-level GOA unit, the GOA unit includes a first output control module, a second output control module, a first output module, and a second output module. Among them, the first output module is used to output the first local scan signal; the second output module is used to output the second local scan signal. By setting the first output module and the second output module, wherein the first output module and the second output module output scan signals with opposite phases respectively, the GOA circuit can realize the output of positive and negative scan signals through one-level GOA units, reducing the border space occupied by the GOA.

Description

Technical Field

[0001] This application relates to the field of display technology, and particularly to a GOA circuit and a display panel. Background Art

[0002] The Gate Driver On Array (GOA) is to use the existing thin-film transistor liquid crystal display array manufacturing process to fabricate the gate row scanning drive signal circuit on the array substrate, realizing the drive mode of scanning the gates row by row.

[0003] The existing GOA circuit adopts the low-temperature polycrystalline oxide display technology, which combines low-temperature polysilicon thin-film transistors and oxide thin-film transistors. Therefore, the display panel can simultaneously have the characteristics of strong driving ability and low power consumption. However, the low-temperature polycrystalline oxide display technology requires more cascaded GOA units to output positive and negative scanning signals, resulting in a wider border of the display panel.

[0004] With the increasing visual demand for narrower borders of displays, how to reduce the border space occupied by the GOA circuit to make the display panel have a narrower border or borderless design is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of the embodiments of this application is to provide a GOA circuit and a display panel to reduce the border space occupied by the GOA circuit.

[0006] On the one hand, the embodiments of this application provide a GOA circuit, including multiple cascaded GOA units. The GOA unit includes a first output control module, a second output control module, a first output module, and a second output module. The first output control module is electrically connected to the previous-level scanning signal input terminal and a first node, and the first output control module is used to control the potential of the first node. The second output control module is electrically connected to the previous-level scanning signal input terminal and a second node, and the second output control module is used to control the potential of the second node. The first output module is electrically connected to the first node, the second node, and a first local-level scanning signal output terminal, and the first output module is used to output a first local-level scanning signal. The second output module is electrically connected to the first node and a second local-level scanning signal output terminal, and the second output module is used to output a second local-level scanning signal. Wherein, the phases of the first local-level scanning signal and the second local-level scanning signal are opposite.

[0007] Optionally, in some embodiments of the present application, the second output module includes a first transistor and a second transistor. The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the reference high-level signal input terminal, and the second electrode of the first transistor is electrically connected to the second local scan signal output terminal. The gate of the second transistor is electrically connected to the first output module, the first electrode of the second transistor is electrically connected to the reference low-level signal input terminal, and the second electrode of the second transistor is electrically connected to the second electrode of the first transistor.

[0008] Optionally, in some embodiments of the present application, the gate of the second transistor is electrically connected to the first node.

[0009] Optionally, in some embodiments of the present application, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0010] Optionally, in some embodiments of the present application, the gate of the second transistor is electrically connected to the second node.

[0011] Optionally, in some embodiments of the present application, both the first transistor and the second transistor are P-type transistors.

[0012] Optionally, in some embodiments of the present application, the first output control module includes a third transistor. The gate of the third transistor is electrically connected to the first clock signal input terminal, the first electrode of the third transistor is electrically connected to the previous-stage scan signal input terminal, and the second electrode of the third transistor is electrically connected to the first node.

[0013] Optionally, in some embodiments of the present application, the second output control module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor. The gate of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the first clock signal input terminal, and the second electrode of the fourth transistor is electrically connected to the second node; the gate of the fifth transistor is electrically connected to the second clock signal input terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the reference low-level signal input terminal; the gate of the sixth transistor is electrically connected to the upper-level scan signal input terminal, the first electrode of the sixth transistor is electrically connected to the reference low-level signal input terminal, and the second electrode of the sixth transistor is electrically connected to the third node; the gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the reference low-level signal input terminal, and the second electrode of the seventh transistor is electrically connected to the second node; one end of the first capacitor is electrically connected to the first clock signal input terminal, and the other end of the first capacitor is electrically connected to the third node.

[0014] Optionally, in some embodiments of the present application, the first output module includes an eighth transistor, a ninth transistor, a tenth transistor, a second capacitor, and a third capacitor. The gate of the eighth transistor is electrically connected to the reference high-level signal input terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fourth node; the gate of the ninth transistor is electrically connected to the fourth node, the first electrode of the ninth transistor is electrically connected to the reference high-level signal input terminal, and the second electrode of the ninth transistor is electrically connected to the first local scan signal output terminal, wherein the first local scan signal output terminal is electrically connected to the lower-level scan signal input terminal; the gate of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the reference low-level signal input terminal, and the second electrode of the tenth transistor is electrically connected to the first local scan signal output terminal; one end of the second capacitor is electrically connected to the fourth node, and the other end of the second capacitor is electrically connected to the first local scan signal output terminal; one end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the reference low-level signal input terminal.

[0015] Optionally, in some embodiments of the present application, the first output module further includes an eleventh transistor. The gate of the eleventh transistor is electrically connected to the fourth node. The first electrode of the eleventh transistor is electrically connected to the second electrode of the ninth transistor. The second electrode of the eleventh transistor is electrically connected to the first local scan signal output terminal.

[0016] Optionally, in some embodiments of the present application, the first output control module includes a third transistor. The gate of the third transistor is electrically connected to the first clock signal input terminal. The first electrode of the third transistor is electrically connected to the upper-level scan signal input terminal. The second electrode of the third transistor is electrically connected to the first node. The second output control module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor. The gate of the fourth transistor is electrically connected to the third node. The first electrode of the fourth transistor is electrically connected to the reference low-level signal input terminal. The second electrode of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the second clock signal input terminal. The first electrode of the fifth transistor is electrically connected to the third node. The second electrode of the fifth transistor is electrically connected to the reference low-level signal input terminal. The gate of the sixth transistor is electrically connected to the upper-level scan signal input terminal. The first electrode of the sixth transistor is electrically connected to the reference low-level signal input terminal. The second electrode of the sixth transistor is electrically connected to the third node. The gate of the seventh transistor is electrically connected to the first node. The first electrode of the seventh transistor is electrically connected to the reference high-level signal input terminal. The second electrode of the seventh transistor is electrically connected to the second node. One end of the first capacitor is electrically connected to the reference low-level signal input terminal, and the other end of the first capacitor is electrically connected to the third node. The first output module includes an eighth transistor, a ninth transistor, a tenth transistor, a second capacitor, and a third capacitor. The gate of the eighth transistor is electrically connected to the reference low-level signal input terminal. The first electrode of the eighth transistor is electrically connected to the first node. The second electrode of the eighth transistor is electrically connected to the fourth node. The gate of the ninth transistor is electrically connected to the fourth node. The first electrode of the ninth transistor is electrically connected to the second clock signal input terminal. The second electrode of the ninth transistor is electrically connected to the first local scan signal output terminal. The gate of the tenth transistor is electrically connected to the second node. The first electrode of the tenth transistor is electrically connected to the reference high-level signal input terminal. The second electrode of the tenth transistor is electrically connected to the first local scan signal output terminal. One end of the second capacitor is electrically connected to the fourth node, and the other end of the second capacitor is electrically connected to the first local scan signal output terminal. One end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the reference high-level signal input terminal.

[0017] On the other hand, the present application provides a display panel, including a display area and the GOA circuit as described above integrally provided on the edge of the display area.

[0018] In the GOA circuit and display panel provided by the embodiments of the present application, the GOA circuit includes GOA units arranged in multiple levels in cascade. Except for the starting-level GOA unit, the GOA unit includes a first output control module, a second output control module, a first output module, and a second output module. Among them, the first output module is used to output the first local scan signal; the second output module is used to output the second local scan signal. By setting the first output module and the second output module, the GOA circuit can output positive and negative scan signals through one-level GOA units, reducing the border space occupied by the GOA, which is conducive to achieving a narrower border or borderless design. Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 Structural schematic diagram of the GOA circuit provided by the embodiments of the present application;

[0021] Figure 2 Structural schematic diagram of the first implementation manner of a GOA unit in the GOA circuit provided by the embodiments of the present application;

[0022] Figure 3 Circuit schematic diagram of the first implementation manner of a GOA unit in the GOA circuit provided by the embodiments of the present application;

[0023] Figure 4 Circuit schematic diagram of the second implementation manner of a GOA unit in the GOA circuit provided by the embodiments of the present application;

[0024] Figure 5 Circuit schematic diagram of the third implementation manner of a GOA unit in the GOA circuit provided by the embodiments of the present application;

[0025] Figure 6 For Figure 3 Signal timing diagram of a GOA unit in the GOA circuit provided in

[0026] Figure 7 Is Figure 3 Schematic diagram of the simulation result of the GOA circuit provided in

[0027] Figure 8 Structural schematic diagram of the display panel provided by the embodiments of the present application. Detailed Implementation Manner

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0029] The embodiments of the present application provide a GOA circuit and a display panel. The GOA circuit has a simple structure, can reduce the space of the circuit layout while ensuring the circuit function, increase the aperture ratio of the display panel, and meet the requirements of narrow borders and high resolution of the display panel. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms "first", "second", "third", etc. are only used as labels to distinguish different objects, rather than to describe a specific order.

[0030] The transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetric, their source and drain can be interchanged. In the embodiments of the present application, to distinguish the two poles of the transistor other than the gate, one of the source and the drain is called the first electrode, and the other of the source and the drain is called the second electrode. According to the form in the accompanying drawings, the middle input terminal of the switching transistor is defined as the gate, the signal input terminal is the first electrode, and the input terminal is the second electrode. In addition, the transistors used in the embodiments of the present application are P-type transistors or N-type transistors. Among them, the P-type transistor conducts when the gate is at a low potential and cuts off when the gate is at a high potential; the N-type transistor conducts when the gate is at a high potential and cuts off when the gate is at a low potential.

[0031] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the GOA circuit provided by the embodiments of the present application. As Figure 1 shown, the GOA circuit provided by the embodiments of the present application includes multiple cascaded GOA units. Figure 1 Taking the (N - 1)-th stage GOA unit GOA(n - 1), the N-th stage GOA unit GOA(n), and the (N + 1)-th stage GOA unit GOA(n + 1) in cascade as an example.

[0032] The (N-1)-th stage GOA unit GOA(n-1), the N-th stage GOA unit GOA(n), and the (N+1)-th stage GOA unit GOA(n+1) are respectively connected to the scan lines G(n-1), G(n), and G(n+1). Among them, the N-th stage GOA unit GOA(n) receives the first local scan signal PSCAN(n-1) output by the (N-1)-th stage GOA unit GOA(n-1). Correspondingly, the (N+1)-th stage GOA unit GOA(n+1) receives the first local scan signal PSCAN(n) output by the N-th stage GOA unit GOA(n), and so on. At the same time, the (N-1)-th stage GOA unit GOA(n-1) transmits the second local scan signal NSCAN(n-1) to the scan line G(n-1) connected to the (N-1)-th stage GOA unit GOA(n), the N-th stage GOA unit GOA(n) transmits the second local scan signal NSCAN(n) to the scan line G(n) connected to the N-th stage GOA unit GOA(n), and the (N+1)-th stage GOA unit GOA(n+1) transmits the second local scan signal NSCAN(n+1) to the scan line G(n+1) connected to the (N+1)-th stage GOA unit GOA(n+1), and so on.

[0033] It should be noted that in the embodiments of the present application, the first local scan signal may also be NSCAN(n), and the first local scan signal NSCAN(n) is output to the next-stage GOA unit; the second local scan signal is PSCAN(n), and the second local scan signal PSCAN(n) is transmitted to the scan line G(n) connected to the N-th stage GOA unit GOA(n).

[0034] Among them, the first-stage GOA unit GOA(1) transmits the second local scan signal NSCAN(1) to the first scan line G(1) connected to the first-stage GOA unit GOA(1) in response to the start signal STV; the first local scan signal PSCAN(1) is transmitted to the second-stage GOA unit GOA(2). It should be noted that the N-th stage GOA unit (N is a natural number greater than 1) can transmit the second local scan signal NSCAN(n) to the N-th scan line G(n); the first local scan signal PSCAN(n) is transmitted to the (N+1)-th stage GOA unit GOA(n+1).

[0035] The scan drive control signal includes a first clock signal CK and a second clock signal XCK. The first clock signal CK and the second clock signal XCK can be a set of reverse clock signals. That is, when the first clock signal CK is at a high potential, the second clock signal XCK is at a low potential, or when the first clock signal CK is at a low potential, the second clock signal XCK is at a high potential.

[0036] When the Nth-stage GOA unit operates, the second local scan signal NSCAN(n) output by the Nth-stage GOA unit GOA(n) is at a high potential, which is used to turn on the transistor switches of each pixel in a row of the display panel and charge the pixel electrodes in each pixel through the data signal; the first local scan signal PSCAN(n) is used to control the operation of the (N + 1)th-stage GOA unit; when the (N + 1)th-stage GOA unit operates, the second local scan signal NSCAN(n + 1) output by the (N + 1)th-stage GOA unit GOA(n + 1) is at a high potential, and at the same time, the second local scan signal NSCAN(n) output by the Nth-stage GOA unit GOA(n) is at a low potential.

[0037] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the first implementation manner of a GOA unit in the GOA circuit provided by the embodiment of the present application. As Figure 2 shown, this GOA unit is a non-starting-stage GOA unit, and this GOA unit includes: a first output control module 101, a second output control module 102, a first output module 103, and a second output module 104.

[0038] Specifically, the first output control module 101 is electrically connected to the previous-stage scan signal input terminal PSCAN(n - 1) / NSCAN(n - 1) and the first node Q, and the first output control module 101 is used to control the potential of the first node Q;

[0039] Specifically, the second output control module 102 is electrically connected to the previous-stage scan signal input terminal PSCAN(n - 1) / NSCAN(n - 1) and the second node P, and the second output control module 102 is used to control the potential of the second node P;

[0040] Specifically, the first output module 103 is electrically connected to the first node Q, the second node P, and the first local scan signal output terminal PSCAN(n - 1) / NSCAN(n - 1), and the first output module 103 is used to output the first local scan signal PSCAN(n - 1) / NSCAN(n - 1);

[0041] Specifically, the second output module 104 is electrically connected to the first node Q and the second local scan signal output terminal NSCAN(n - 1) / PSCAN(n - 1), and the second output module 104 is used to output the second local scan signal NSCAN(n - 1) / PSCAN(n - 1);

[0042] Among them, the phases of the first local scan signal PSCAN(n - 1) / NSCAN(n - 1) and the second local scan signal NSCAN(n - 1) / PSCAN(n - 1) are opposite. That is, when the first local scan signal is PSCAN(n - 1), the second local scan signal is NSCAN(n - 1); or when the first local scan signal is NSCAN(n - 1)P, the second local scan signal is SCAN(n - 1).

[0043] The GOA circuit provided by this application realizes outputting positive and negative scan signals through one - stage GOA units by setting the first output module 103 and the second output module 104, where the first output module 103 and the second output module 104 respectively output scan signals with opposite phases, reducing the border space occupied by the GOA and facilitating the realization of a narrower border or borderless design.

[0044] In the embodiment of this application, the second output module 104 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is electrically connected to the first node Q. The first electrode of the first transistor T1 is electrically connected to the reference high - level signal input terminal VGH. The second electrode of the first transistor T1 is electrically connected to the second local scan signal output terminal NSCAN(n); among them, the gate of the second transistor T2 is electrically connected to the first output module 103. The first electrode of the second transistor T2 is electrically connected to the reference low - level signal input terminal VGL. The second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1. Specifically, please refer to the following Figure 3 、 Figure 4 corresponding embodiments:

[0045] Please refer to Figure 3 , Figure 3 which is a schematic circuit diagram of the first implementation manner of a GOA unit in the GOA circuit provided by the embodiment of this application. As Figure 2 、 Figure 3 shown, the second output module 104 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is electrically connected to the first node Q. The first electrode of the first transistor T1 is electrically connected to the reference high - level signal input terminal VGH. The second electrode of the first transistor T1 is electrically connected to the second local scan signal output terminal NSCAN(n);

[0046] The gate of the second transistor T2 is electrically connected to the first node Q. The first electrode of the second transistor T2 is electrically connected to the reference low - level signal input terminal VGL. The second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1.

[0047] ​Specifically, the first output control module 101 includes a third transistor T3. The gate of the third transistor T3 is electrically connected to the first clock signal input terminal CK. The first electrode of the third transistor T3 is electrically connected to the upper-level scan signal input terminal PSCAN(n - 1). The second electrode of the third transistor T3 is electrically connected to the first node Q.

[0048] Specifically, the second output control module 102 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The gate of the fourth transistor T4 is electrically connected to the third node S. The first electrode of the fourth transistor T4 is electrically connected to the first clock signal input terminal CK. The second electrode of the fourth transistor T4 is electrically connected to the second node P;

[0049] The gate of the fifth transistor T5 is electrically connected to the second clock signal input terminal XCK. The first electrode of the fifth transistor T5 is electrically connected to the third node S. The second electrode of the fifth transistor T5 is electrically connected to the reference low-level signal input terminal VGL;

[0050] The gate of the sixth transistor T6 is electrically connected to the upper-level scan signal input terminal PSCAN(n - 1). The first electrode of the sixth transistor T6 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the sixth transistor T6 is electrically connected to the third node S;

[0051] The gate of the seventh transistor T7 is electrically connected to the first node Q. The first electrode of the seventh transistor T7 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the seventh transistor T7 is electrically connected to the second node P;

[0052] One end of the first capacitor C1 is electrically connected to the first clock signal input terminal CK. The other end of the first capacitor C1 is electrically connected to the third node S.

[0053] Specifically, the first output module 103 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2, and a third capacitor C3. The gate of the eighth transistor T8 is electrically connected to the reference high-level signal input terminal VGH. The first electrode of the eighth transistor T8 is electrically connected to the first node Q. The second electrode of the eighth transistor T8 is electrically connected to the fourth node N;

[0054] The gate of the ninth transistor T9 is electrically connected to the fourth node N. The first electrode of the ninth transistor T9 is electrically connected to the reference high-level signal input terminal VGH. The second electrode of the ninth transistor T9 is electrically connected to the first local-level scan signal output terminal PSCAN(n), where the first local-level scan signal output terminal PSCAN(n) is electrically connected to the next-level scan signal input terminal;

[0055] The gate of the tenth transistor T10 is electrically connected to the second node P, the first electrode of the tenth transistor T10 is electrically connected to the reference low-level signal input terminal VGL, and the second electrode of the tenth transistor T10 is electrically connected to the first-stage scan signal output terminal PSCAN(n);

[0056] One end of the second capacitor C2 is electrically connected to the fourth node N, and the other end of the second capacitor C2 is electrically connected to the first-stage scan signal output terminal PSCAN(n); One end of the third capacitor C3 is electrically connected to the second node P, and the other end of the third capacitor C3 is electrically connected to the reference low-level signal input terminal VGL.

[0057] Specifically, the first output module 103 further includes an eleventh transistor T11. The gate of the eleventh transistor T11 is electrically connected to the fourth node N, the first electrode of the eleventh transistor T11 is electrically connected to the second electrode of the ninth transistor T9, and the second electrode of the eleventh transistor T11 is electrically connected to the first-stage scan signal output terminal PSCAN(n).

[0058] Among them, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are all N-type transistors, and the first transistor T1 is a P-type transistor.

[0059] It should be noted that the previous-stage scan signal input terminal PSCAN(n - 1) receives the previous-stage scan signal, the first-stage scan signal output terminal PSCAN(n) outputs the first-stage scan signal PSCAN(n), the second-stage scan signal output terminal NSCAN(n) outputs the second-stage scan signal NSCAN(n), the first clock signal input terminal CK receives the first clock signal CK, the second clock signal input terminal XCK receives the second clock signal XCK, the reference high-level signal input terminal VGH receives the reference high-level signal VGH, and the reference low-level signal input terminal VGL receives the reference low-level signal VGL.

[0060] Specifically, please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a second implementation manner of a GOA unit in the GOA circuit provided by the embodiment of the present application. As Figure 2 、 Figure 4As shown, the second output module 104 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is electrically connected to the first node Q. The first electrode of the first transistor T1 is electrically connected to the reference high-level signal input terminal VGH. The second electrode of the first transistor T1 is electrically connected to the second local scan signal output terminal PSCAN(n). The gate of the second transistor T2 is electrically connected to the second node P. The first electrode of the second transistor T2 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1.

[0061] Specifically, the first output control module 101 includes a third transistor T3. The gate of the third transistor T3 is electrically connected to the first clock signal input terminal CK. The first electrode of the third transistor T3 is electrically connected to the previous-level scan signal input terminal NSCAN(n - 1). The second electrode of the third transistor T3 is electrically connected to the first node Q.

[0062] Specifically, the second output control module 102 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The gate of the fourth transistor T4 is electrically connected to the third node S. The first electrode of the fourth transistor T4 is electrically connected to the first clock signal input terminal CK. The second electrode of the fourth transistor T4 is electrically connected to the second node P.

[0063] The gate of the fifth transistor T5 is electrically connected to the second clock signal input terminal XCK. The first electrode of the fifth transistor T5 is electrically connected to the third node S. The second electrode of the fifth transistor T5 is electrically connected to the reference low-level signal input terminal VGL.

[0064] The gate of the sixth transistor T6 is electrically connected to the previous-level scan signal input terminal NSCAN(n - 1). The first electrode of the sixth transistor T6 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the sixth transistor T6 is electrically connected to the third node S.

[0065] The gate of the seventh transistor T7 is electrically connected to the first node Q. The first electrode of the seventh transistor T7 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the seventh transistor T7 is electrically connected to the second node P.

[0066] One end of the first capacitor C1 is electrically connected to the first clock signal input terminal CK. The other end of the first capacitor C1 is electrically connected to the third node S.

[0067] Specifically, the first output module 103 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2, and a third capacitor C3. The gate of the eighth transistor T8 is electrically connected to the reference high-level signal input terminal VGH. The first electrode of the eighth transistor T8 is electrically connected to the first node Q. The second electrode of the eighth transistor T8 is electrically connected to the fourth node N;

[0068] The gate of the ninth transistor T9 is electrically connected to the fourth node N. The first electrode of the ninth transistor T9 is electrically connected to the reference high-level signal input terminal VGH. The second electrode of the ninth transistor T9 is electrically connected to the first local scan signal output terminal NSCAN(n), where the first local scan signal output terminal NSCAN(n) is electrically connected to the next-level scan signal input terminal;

[0069] The gate of the tenth transistor T10 is electrically connected to the second node P. The first electrode of the tenth transistor T10 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the tenth transistor T10 is electrically connected to the first local scan signal output terminal NSCAN(n);

[0070] One end of the second capacitor C2 is electrically connected to the fourth node N. The other end of the second capacitor C2 is electrically connected to the first local scan signal output terminal NSCAN(n); One end of the third capacitor C3 is electrically connected to the second node P. The other end of the third capacitor C3 is electrically connected to the reference low-level signal input terminal VGL.

[0071] Among them, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are N-type transistors, and the first transistor T1, the second transistor T2, and the seventh transistor T7 are P-type transistors.

[0072] It should be noted that the upper-level scan signal input terminal NSCAN(n - 1) receives the upper-level scan signal NSCAN(n - 1), the first local scan signal output terminal NSCAN(n) outputs the first local scan signal NSCAN(n), the second local scan signal output terminal PSCAN(n) outputs the second local scan signal, the first clock signal input terminal CK receives the first clock signal CK, the second clock signal input terminal XCK receives the second clock signal XCK, the reference high-level signal input terminal VGH receives the reference high-level signal VGH, and the reference low-level signal input terminal VGL receives the reference low-level signal VGL.

[0073] Specifically, please refer to Figure 5 , Figure 5 which is a schematic structural diagram of a third implementation manner of a GOA unit in the GOA circuit provided by the embodiment of the present application. As Figure 2 ,Figure 5 As shown in the figure, the second output module 104 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is electrically connected to the first node Q. The first electrode of the first transistor T1 is electrically connected to the reference high-level signal input terminal VGH. The second electrode of the first transistor T1 is electrically connected to the second local scan signal output terminal PSCAN(n).

[0074] Specifically, the gate of the second transistor T2 is electrically connected to the first node Q. The first electrode of the second transistor T2 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1.

[0075] Specifically, the first output control module 101 includes a third transistor T3. The gate of the third transistor T3 is electrically connected to the first clock signal input terminal CK. The first electrode of the third transistor T3 is electrically connected to the previous stage scan signal input terminal NSCAN(n - 1). The second electrode of the third transistor T3 is electrically connected to the first node Q.

[0076] Specifically, the second output control module 102 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1. The gate of the fourth transistor T4 is electrically connected to the third node S. The first electrode of the fourth transistor T4 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the fourth transistor T4 is electrically connected to the second node P.

[0077] The gate of the fifth transistor T5 is electrically connected to the second clock signal input terminal XCK. The first electrode of the fifth transistor T5 is electrically connected to the third node S. The second electrode of the fifth transistor T5 is electrically connected to the reference low-level signal input terminal VGL.

[0078] The gate of the sixth transistor T6 is electrically connected to the previous stage scan signal input terminal NSCAN(n - 1). The first electrode of the sixth transistor T6 is electrically connected to the reference low-level signal input terminal VGL. The second electrode of the sixth transistor T6 is electrically connected to the third node S.

[0079] The gate of the seventh transistor T7 is electrically connected to the first node Q. The first electrode of the seventh transistor T7 is electrically connected to the reference high-level signal input terminal VGH. The second electrode of the seventh transistor T7 is electrically connected to the second node P.

[0080] One end of the first capacitor C1 is electrically connected to the reference low-level signal input terminal VGL. The other end of the first capacitor C1 is electrically connected to the third node S.

[0081] Specifically, the first output module 103 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2, and a third capacitor C3. The gate of the eighth transistor T8 is electrically connected to the reference low-level signal input terminal VGL. The first electrode of the eighth transistor T8 is electrically connected to the first node Q. The second electrode of the eighth transistor T8 is electrically connected to the fourth node N.

[0082] The gate of the ninth transistor T9 is electrically connected to the fourth node N. The first electrode of the ninth transistor T9 is electrically connected to the second clock signal input terminal XCK. The second electrode of the ninth transistor T9 is electrically connected to the first local scan signal output terminal NSCAN(n).

[0083] The gate of the tenth transistor T10 is electrically connected to the second node P. The first electrode of the tenth transistor T10 is electrically connected to the reference high-level signal input terminal VGH. The second electrode of the tenth transistor T10 is electrically connected to the first local scan signal output terminal NSCAN(n).

[0084] One end of the second capacitor C2 is electrically connected to the fourth node N. The other end of the second capacitor C2 is electrically connected to the first local scan signal output terminal NSCAN(n).

[0085] One end of the third capacitor C3 is electrically connected to the second node P. The other end of the third capacitor C3 is electrically connected to the reference high-level signal input terminal VGH.

[0086] Among them, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all P-type transistors, and the second transistor T2 is an N-type transistor.

[0087] It should be noted that the upper-level scan signal input terminal NSCAN(n - 1) receives the upper-level scan signal NSCAN(n - 1). The first local scan signal output terminal NSCAN(n) outputs the first local scan signal NSCAN(n). The second local scan signal output terminal PSCAN(n) outputs the second local scan signal. The first clock signal input terminal CK receives the first clock signal CK. The second clock signal input terminal XCK receives the second clock signal XCK. The reference high-level signal input terminal VGH receives the reference high-level signal VGH. The reference low-level signal input terminal VGL receives the reference low-level signal VGL.

[0088] Please refer to Figure 6 , Figure 6 for Figure 3 the signal timing diagram of a GOA unit in the GOA circuit provided in Figure 6Shown in the figure is a GOA circuit for a group of clock control signals within one frame of time. A high-frequency signal with a 50 / 50 duty cycle is adopted. In an actual display panel, clock signals with different duty cycles can be set according to needs to drive the GOA circuit, or multiple groups of high-frequency clock signals can be designed according to the load of the display panel. Specifically, the start signal STV is input into the first output control module 101 of the first-stage GOA unit and the first output module 103 of the last-stage GOA unit to charge the first node Q.

[0089] Specifically, the start signal STV of the GOA circuit is responsible for starting the first-stage GOA circuit, while the start signal STV of the (N + 1)-th stage GOA circuit is generated by the first local scan signal PSCAN(n) output from the first output module 103 of the N-th stage GOA circuit. In this way, the GOA driving circuit can be turned on stage by stage to achieve row scan driving.

[0090] Specifically, the first clock signal CK and the second clock signal XCK are a group of high-frequency clock signals with the same high and low potentials and opposite phases. The pulse width, period, and high and low potentials of the clock signals mainly depend on the design requirements of the scan signal waveform of the display panel. Therefore, in the actual application of the display panel, it is not necessarily a signal with a 50 / 50 duty cycle as shown in the figure, and sometimes different numbers of clock signals are used according to the design requirements of the panel to bear the load of different design requirements.

[0091] Among them, in the first output stage t1, the first clock signal CK writes a high potential, and the third transistor T3 is turned on. At this time, the first node Q writes the low potential of the start signal STV, making the first transistor T1 turn on; the second output module 104 outputs the second local scan signal NSCAN(n).

[0092] In the second output stage t2, the first clock signal CK writes a high potential, and the third transistor T3 is turned on. At this time, the first node Q writes the high potential of the start signal STV, charges the first node Q, and makes the first transistor T1 turn off; the reference high-level signal VGH with a high potential turns on the eighth transistor T8, and the high potential of the first node Q is transmitted to the second node N, making the ninth transistor T9 and the eleventh transistor T11 turn on. The first output module 103 outputs the first local scan signal PSCAN(n).

[0093] Please refer to Figure 7 , Figure 7 is Figure 3 a schematic diagram of the simulation result of the GOA circuit provided in Figure 7As shown, the potential changes of the first local scan signal PSCAN(n), the second local scan signal NSCAN(n), and the previous-stage scan signal PSCAN(n - 1) (or the start signal STV). The GOA circuit provided in this application realizes the output of positive and negative scan signals through one-stage GOA units, reduces the border space occupied by the GOA, enables the display panel to achieve a narrower border or borderless design, and can prevent the output of noise during the period when the scan signal is not output, thereby ensuring the driving stability.

[0094] Please refer to Figure 8 , Figure 8 , which is a schematic structural diagram of the display panel provided by the embodiment of this application. As Figure 8 shown, this application also provides a display panel, which includes a display area 100 and the above GOA circuit 10 integrally arranged on the edge of the display area; wherein, the structure and principle of this GOA circuit 10 are similar to those of the above GOA circuit 10, and will not be elaborated here.

[0095] In the GOA circuit and the display panel provided by the embodiment of this application, by setting the first output module 103 and the second output module 104, the GOA circuit can realize the output of positive and negative scan signals through one-stage GOA units, reduce the border space occupied by the GOA, and enable the display panel to achieve a narrower border or borderless design.

[0096] The above has introduced in detail a GOA circuit and a display panel provided by the embodiment of this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A GOA circuit, characterized in that, It includes GOA units arranged in multiple - stage cascades. The GOA unit includes a first output control module, a second output control module, a first output module, and a second output module; The first output control module is electrically connected to the input terminal of the previous - stage scan signal and a first node, and the first output control module is used to control the potential of the first node; The second output control module is electrically connected to the input terminal of the previous - stage scan signal and a second node, and the second output control module is used to control the potential of the second node; The first output module is electrically connected to the first node, the second node, and the first output terminal of the current - stage scan signal, and the first output module is used to output the first output terminal of the current - stage scan signal; The second output module is electrically connected to the first node and the second output terminal of the current - stage scan signal, and the second output module is used to output the second output terminal of the current - stage scan signal; Wherein, the phases of the first output terminal of the current - stage scan signal and the second output terminal of the current - stage scan signal are opposite; The second output control module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor. The gate of the fourth transistor is electrically connected to a third node S, the first electrode of the fourth transistor is electrically connected to the first clock signal input terminal, and the second electrode of the fourth transistor is electrically connected to the second node; The gate of the fifth transistor is electrically connected to the second clock signal input terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the reference low - level signal input terminal; The gate of the sixth transistor is electrically connected to the input terminal of the previous - stage scan signal, the first electrode of the sixth transistor is electrically connected to the reference low - level signal input terminal, and the second electrode of the sixth transistor is electrically connected to the third node; The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the reference low - level signal input terminal, and the second electrode of the seventh transistor is electrically connected to the second node; One end of the first capacitor is electrically connected to the first clock signal input terminal, and the other end of the first capacitor is electrically connected to the third node.

2. The GOA circuit according to claim 1, wherein The second output module includes a first transistor and a second transistor. The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the reference high - level signal input terminal, and the second electrode of the first transistor is electrically connected to the second output terminal of the current - stage scan signal; The gate of the second transistor is electrically connected to the first output module, the first electrode of the second transistor is electrically connected to the reference low - level signal input terminal, and the second electrode of the second transistor is electrically connected to the second electrode of the first transistor.

3. The GOA circuit according to claim 2, wherein The gate of the second transistor is electrically connected to the first node.

4. The GOA circuit according to claim 3, characterized in that, The first transistor is a P - type transistor, and the second transistor is an N - type transistor.

5. The GOA circuit according to claim 4, wherein The first output control module includes a third transistor. The gate of the third transistor is electrically connected to the first clock signal input terminal. The first electrode of the third transistor is electrically connected to the previous-stage scan signal input terminal. The second electrode of the third transistor is electrically connected to the first node. The second output control module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor. The gate of the fourth transistor is electrically connected to the third node. The first electrode of the fourth transistor is electrically connected to the reference low-level signal input terminal. The second electrode of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the second clock signal input terminal. The first electrode of the fifth transistor is electrically connected to the third node. The second electrode of the fifth transistor is electrically connected to the reference low-level signal input terminal. The gate of the sixth transistor is electrically connected to the previous-stage scan signal input terminal. The first electrode of the sixth transistor is electrically connected to the reference low-level signal input terminal. The second electrode of the sixth transistor is electrically connected to the third node. The gate of the seventh transistor is electrically connected to the first node. The first electrode of the seventh transistor is electrically connected to the reference high-level signal input terminal. The second electrode of the seventh transistor is electrically connected to the second node. One end of the first capacitor is electrically connected to the reference low-level signal input terminal, and the other end of the first capacitor is electrically connected to the third node. The first output module includes an eighth transistor, a ninth transistor, a tenth transistor, a second capacitor, and a third capacitor. The gate of the eighth transistor is electrically connected to the reference low-level signal input terminal. The first electrode of the eighth transistor is electrically connected to the first node. The second electrode of the eighth transistor is electrically connected to the fourth node. The gate of the ninth transistor is electrically connected to the fourth node. The first electrode of the ninth transistor is electrically connected to the second clock signal input terminal. The second electrode of the ninth transistor is electrically connected to the first local scan signal output terminal. The gate of the tenth transistor is electrically connected to the second node. The first electrode of the tenth transistor is electrically connected to the reference high-level signal input terminal. The second electrode of the tenth transistor is electrically connected to the first local scan signal output terminal. One end of the second capacitor is electrically connected to the fourth node, and the other end of the second capacitor is electrically connected to the first local scan signal output terminal. One end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the reference high-level signal input terminal.

6. The GOA circuit according to claim 2, wherein The gate of the second transistor is electrically connected to the second node.

7. The GOA circuit according to claim 6, wherein Both the first transistor and the second transistor are P-type transistors.

8. The GOA circuit according to claim 1, wherein The first output control module includes a third transistor. The gate of the third transistor is electrically connected to the first clock signal input terminal. The first electrode of the third transistor is electrically connected to the previous-stage scan signal input terminal. The second electrode of the third transistor is electrically connected to the first node.

9. The GOA circuit according to claim 1, wherein The first output module includes an eighth transistor, a ninth transistor, a tenth transistor, a second capacitor, and a third capacitor. The gate of the eighth transistor is electrically connected to the reference high-level signal input terminal. The first electrode of the eighth transistor is electrically connected to the first node. The second electrode of the eighth transistor is electrically connected to the fourth node. The gate of the ninth transistor is electrically connected to the fourth node. The first electrode of the ninth transistor is electrically connected to the reference high-level signal input terminal. The second electrode of the ninth transistor is electrically connected to the first in-stage scan signal output terminal. Among them, the first in-stage scan signal output terminal is electrically connected to the next-stage scan signal input terminal. The gate of the tenth transistor is electrically connected to the second node. The first electrode of the tenth transistor is electrically connected to the reference low-level signal input terminal. The second electrode of the tenth transistor is electrically connected to the first in-stage scan signal output terminal. One end of the second capacitor is electrically connected to the fourth node. The other end of the second capacitor is electrically connected to the first in-stage scan signal output terminal. One end of the third capacitor is electrically connected to the second node. The other end of the third capacitor is electrically connected to the reference low-level signal input terminal.

10. The GOA circuit according to claim 9, wherein, The first output module further includes an eleventh transistor. The gate of the eleventh transistor is electrically connected to the fourth node. The first electrode of the eleventh transistor is electrically connected to the second electrode of the ninth transistor. The second electrode of the eleventh transistor is electrically connected to the first in-stage scan signal output terminal.

11. A display panel, characterized in that, It includes a display area and a GOA circuit as described in any one of claims 1-10 integrally provided on the edge of the display area.

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