A memory testing method, device and apparatus

Abstract

The present application relates to the technical field of dynamic memories, and discloses a memory testing method, device and apparatus. The memory testing method, device and apparatus convert commands that cannot be directly decoded into corresponding control signals, and then perform a memory testing operation according to the control signals. The present application can be applied to the debugging and testing of backend memory products, has low cost and high flexibility, and simultaneously supports test instructions that cannot be directly decoded.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a method, device, and apparatus for testing a memory. Background Art

[0002] Currently, the testing of memories mainly relies on a machine for testing, but the machine testing method is costly and inflexible.

[0003] In related technologies, an SLT test (system-level test) is also used to enter the memory test mode, which uses a CPU motherboard to test the memory. However, for test instructions that cannot be directly decoded in the memory test mode, such as test instructions that do not meet the JEDEC (Joint Electron Device Engineering Council) specification, the CPU motherboard cannot perform the test. Summary of the Invention

[0004] Embodiments of this application provide a method, device, and apparatus for testing a memory, which can be applied to the debugging and testing of backend memory products, with low cost and high flexibility, and at the same time support instructions that cannot be directly decoded.

[0005] According to some embodiments, a first aspect of this application provides a method for testing a memory, the method including:

[0006] Receiving a test instruction, where the test instruction includes a control command;

[0007] Analyzing the command type to which the control command belongs;

[0008] When it is analyzed that the command type to which the control command belongs belongs to a first command type, converting the control command into a corresponding control signal;

[0009] According to the control signal, outputting corresponding first data in a preset storage area to corresponding pins of the memory to be tested at the falling edge of a command clock; and / or, reading second data of corresponding pins of the memory to be tested into the preset storage area.

[0010] According to an implementable manner of the first aspect of this application, the first command type is a command that does not meet the JEDEC specification.

[0011] According to an implementable manner of the first aspect of this application, the converting the control command into a corresponding control signal specifically includes:

[0012] Searching for signal generation data corresponding to the control command in a stored command list, and generating a control signal according to the signal generation data.

[0013] According to an implementable manner of the first aspect of the present application, the method further includes:

[0014] If multiple signal generation data corresponding to the control command are found in the stored command list, select the signal generation data corresponding to the type identifier of the memory under test to generate control signals.

[0015] According to an implementable manner of the first aspect of the present application, the method further includes:

[0016] When the signal generation data corresponding to the control command cannot be found according to the stored command list, output information for prompting that the test instruction is an error instruction.

[0017] According to an implementable manner of the first aspect of the present application, the method further includes:

[0018] When it is parsed that the command type to which the control command belongs belongs to the second command type, decode the control command to obtain the corresponding control signal.

[0019] According to an implementable manner of the first aspect of the present application, the second command type is a command that meets the JEDEC specification.

[0020] According to an implementable manner of the first aspect of the present application, the test instruction further includes the first data, and the method further includes:

[0021] Store the first data in the preset storage area.

[0022] According to an implementable manner of the first aspect of the present application, the first data includes address data and control data, the address data includes a storage cell array address, a group address, a row address, and a column address, the preset storage area includes a first sub-storage area, a second sub-storage area, and a third sub-storage area, and the method includes:

[0023] Store the storage cell array address in the first sub-storage area therein, and store the group address, row address, and column address in the second sub-storage area therein;

[0024] Store the control data in the third sub-storage area.

[0025] According to an implementable manner of the first aspect of the present application, the preset storage area includes a fourth sub-storage area, and the method includes:

[0026] Read the data of the corresponding pin of the memory into the fourth sub-storage area.

[0027] According to an implementable manner of the first aspect of the present application, the first sub-storage area, the second sub-storage area, the third sub-storage area, and the fourth sub-storage area are all FIFO storage areas.

[0028] According to an implementable manner of the first aspect of the present application, the memory to be tested is a DRAM chip.

[0029] The second aspect of the present application provides a memory test device, and the device includes:

[0030] A receiving module, configured to receive a test instruction, where the test instruction includes a control command;

[0031] An analysis module, configured to analyze the command type to which the control command belongs;

[0032] A conversion module, configured to convert the control command into a corresponding control signal when the analysis module analyzes that the command type to which the control command belongs belongs to the first command type;

[0033] An execution module, configured to output corresponding first data in a preset storage area to corresponding pins of the memory to be tested at a falling edge of a command clock according to the control signal; and / or, read second data of corresponding pins of the memory to be tested into the preset storage area.

[0034] According to an implementable manner of the second aspect of the present application, the first command type is a command that does not meet the JEDEC specification.

[0035] According to an implementable manner of the second aspect of the present application, the conversion module is specifically configured to:

[0036] Search for signal generation data corresponding to the control command in a stored command list, and generate a converted control signal according to the signal generation data.

[0037] According to an implementable manner of the second aspect of the present application, the conversion module is further specifically configured to:

[0038] If multiple pieces of signal generation data corresponding to the control command are found in the stored command list, select the signal generation data corresponding to the type identifier of the memory to be tested from them for control signal generation.

[0039] According to an implementable manner of the second aspect of the present application, the device further includes:

[0040] A first prompt module, configured to output information for prompting that the test instruction is an incorrect instruction when the signal generation data corresponding to the control command cannot be found in the stored command list.

[0041] According to an implementable manner of the second aspect of the present application, the device further includes:

[0042] A decoding module, configured to decode the control command to obtain a corresponding control signal when the parsing module parses that the command type to which the control command belongs belongs to the second command type.

[0043] According to an implementable manner of the second aspect of the present application, the second command type is a command that meets the JEDEC specification.

[0044] According to an implementable manner of the second aspect of the present application, the test instruction further includes the first data, and the device further includes:

[0045] A storage module, configured to store the first data in the preset storage area.

[0046] According to an implementable manner of the second aspect of the present application, the first data includes address data and control data, the address data includes a storage cell array address, a group address, a row address, and a column address, the preset storage area includes a first sub-storage area, a second sub-storage area, and a third sub-storage area, and the storage module specifically includes:

[0047] A first storage unit, configured to store the storage cell array address in the first sub-storage area therein;

[0048] A second storage unit, configured to store the group address, the row address, and the column address in the second sub-storage area therein;

[0049] A third storage unit, configured to store the control data in the third sub-storage area.

[0050] According to an implementable manner of the second aspect of the present application, the preset storage area includes a fourth sub-storage area, and the reading unit is specifically configured to:

[0051] Read the data of the corresponding pin of the memory into the fourth sub-storage area.

[0052] According to an implementable manner of the second aspect of the present application, the first sub-storage area, the second sub-storage area, the third sub-storage area, and the fourth sub-storage area are all FIFO storage areas.

[0053] According to an implementable manner of the second aspect of the present application, the memory to be tested is a DRAM chip.

[0054] The third aspect of the present application provides a memory test device, the device includes the memory test device described in any one of the above, and the device further includes:

[0055] An instruction sending device for sending the test instruction to the memory test device.

[0056] According to an implementable manner of the third aspect of the present application, the instruction sending device is a CPU.

[0057] According to an implementable manner of the third aspect of the present application, the device further includes a universal asynchronous receiver-transmitter;

[0058] The CPU is connected to the user terminal through the universal asynchronous receiver-transmitter to receive the operation information corresponding to the test instruction input by the user terminal.

[0059] The embodiments of the present application can / at least have the following beneficial technical effects:

[0060] The present application parses the control command in the received test instruction. When it is parsed that the command type to which the control command belongs is the first command type, the control command is converted into a corresponding control signal, and then the memory is tested under the drive of the control signal. The present application can parse and convert the control command that cannot be directly decoded, so it can implement the corresponding test instruction, such as a test instruction that does not meet the JEDEC specification. For other conventional test instructions, the memory can be directly tested according to the test instruction without the need for control command conversion operations. The present application can be applied to the debugging and testing of backend memory products, with low cost and high flexibility. In addition to being able to implement the test instructions required by the JEDEC specification, it can also implement all test instructions that do not meet the JEDEC specification. Description of the Drawings

[0061] Figure 1 is a schematic flowchart of an embodiment of the memory test method provided by the present application;

[0062] Figure 2 is a schematic diagram of the timing relationship of an embodiment of the Read Chipid instruction provided by the present application;

[0063] Figure 3 is a schematic diagram of the data flow of an embodiment of the memory test device provided by the present application;

[0064] Figure 4 is a schematic diagram of the structural connection of an embodiment of the memory test device provided by the present application.

[0065] Reference Signs:

[0066] 1. Receiving module; 2. Parsing module; 3. Converting module; 4. Executing module. Detailed Embodiments

[0067] This application describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope of the embodiments described in this application. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0068] This application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented alone or in any suitable combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes can be made within the scope of the protection of the appended claims.

[0069] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of steps described. As will be understood by those of ordinary skill in the art, other step orders are possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can vary and still remain within the spirit and scope of the embodiments of this application.

[0070] The memory test mode is a super mode that can only be accessed by the original factory and is usually not open to customers for use. For example, for DRAM (Dynamic Random Access Memory) chips, after the DRAM chips are fabricated and packaged, the internal DFT registers of the DRAM chips can be accessed and modified by entering the DRAM chip test mode, thereby changing some of the power supply voltages, I / O timings, and interface parameters for debugging inside the DRAM chips. This is beneficial to improving the debugging efficiency of DRAM chips, accelerating error location, and enabling the entire DRAM chip test process to converge quickly.

[0071] In the related art, the SLT test (system-level test) method is adopted to enter the memory test mode. By installing the memory on the CPU motherboard, the CPU motherboard tests the memory. This method requires the complete underlying code of the CPU motherboard and the control code that can correctly modify the PHY (physical layer) of the memory, resulting in too high costs. Moreover, some of the test instructions in the memory test mode cannot be directly decoded. For example, the test instructions that do not meet the JEDEC specification, that is, the test instructions not defined in the JEDEC specification. The CPU motherboard cannot implement these test instructions. For example, for DRAM chips, in the test mode, the information output by the DRAM chip externally is usually implemented using the DQ pins, without the transition of the DQS signal. This leads to the inability to perform operations such as reading the chip ID after entering the DRAM chip test mode using the CPU motherboard.

[0072] An embodiment of the present application provides a memory test method, and this method is as Figure 1 shown, including the following steps:

[0073] S1 Receive a test instruction, and the test instruction includes a control command.

[0074] Among them, the test instruction can be an instruction that can be directly decoded by the device executing this method, such as a test instruction defined in the JEDEC specification, or an instruction that cannot be directly decoded, such as a test instruction not defined in the JEDEC specification. The test instructions that do not meet the JEDEC specification are generally test instructions customized by the original memory manufacturer for functions such as debugging and testing. For example, the Read Chipid (read chip identification) instruction is not defined in the JEDEC specification and is used to read the ID of the DRAM chip. The ID stores information such as the production date and packaging and testing manufacturer of the DRAM chip. When the test instruction is a test instruction defined in the JEDEC specification, the control command in the test instruction is the command defined by the JEDEC specification. Otherwise, it is considered that the control command is not the command defined by the JEDEC specification.

[0075] S2 Analyze the command type to which the control command belongs.

[0076] When it is parsed that the command type to which the control command belongs belongs to the first command type, convert the control command into a corresponding control signal.

[0077] S4 Output the corresponding first data in the preset storage area to the corresponding pins of the memory to be tested at the falling edge of the command clock according to the control signal; and / or, read the second data of the corresponding pins of the memory to be tested into the preset storage area.

[0078] When performing step S4, specifically, when the test operation corresponding to the test instruction only needs to output relevant data to the memory under test, the corresponding first data in the preset storage area is output to the corresponding pin of the memory under test at the falling edge of the command clock according to the corresponding control signal;

[0079] When the test operation corresponding to the test instruction only needs to read data from the memory under test, the second data of the corresponding pin of the memory under test is read into the preset storage area;

[0080] When the test operation corresponding to the test instruction needs to output relevant data to the memory under test and read data from the memory under test, the corresponding first data in the preset storage area is output to the corresponding pin of the memory under test at the falling edge of the command clock according to the corresponding control signal, and the second data of the corresponding pin of the memory under test is read into the preset storage area.

[0081] According to some embodiments, the first command type is a command that cannot directly decode to obtain the corresponding control signal, for example, a command that does not meet the JEDEC standard, and such a control command needs to be converted / interpreted.

[0082] To implement the parsing of commands that do not meet the JEDEC standard, the command information corresponding to the test instructions that do not meet the JEDEC standard can be pre-stored, and the type of the control command can be parsed according to the stored command information. By converting the commands that do not meet the JEDEC standard into the corresponding control signals, and then performing the test operation on the memory according to the control signals, the embodiments of the present application can implement the corresponding operations for the test instructions that do not meet the JEDEC standard.

[0083] In some embodiments, the conversion of the control command into the corresponding control signal specifically includes:

[0084] Search for the signal generation data corresponding to the control command in the stored command list, and generate the converted control signal according to the signal generation data.

[0085] Wherein, the command list includes a plurality of preset control commands, each control command corresponds to one or more signal generation data, and the signal generation data is used to generate the corresponding control signal.

[0086] Specifically, in one implementation manner, if multiple signal generation data corresponding to the control command are found in the stored command list, the test instruction further includes the type identifier of the memory under test. Thus, after receiving the test instruction, the signal generation data that conforms to the type of the memory under test can be selected from the multiple signal generation data according to the type identifier of the memory under test carried by the test instruction, so as to generate the corresponding control signal.

[0087] Among them, the type identifier is used to distinguish different memories to be tested, for example, to distinguish different types of memories or different models of the same type of memory.

[0088] In another embodiment, when multiple signal generation data are found, information for prompting to select the type of the memory to be tested may be output, and the signal generation data is determined according to the type identifier of the memory to be tested selected by the tester.

[0089] In some embodiments, the method further includes:

[0090] When the signal generation data corresponding to the control command cannot be found according to the stored command list, information for prompting that the test instruction is an incorrect instruction is output. This embodiment can implement the legality detection of the test instruction.

[0091] In some embodiments, the method further includes:

[0092] When it is parsed that the command type to which the control command belongs belongs to the second command type, the control command is decoded to obtain the corresponding control signal.

[0093] In some embodiments, the second command type is a command that complies with the JEDEC specification.

[0094] This application embodiment directly decodes the command that complies with the JEDEC specification, and realizes the test operation of the test instruction that complies with the JEDEC specification.

[0095] In some embodiments, the first data is local data pre-stored in a preset storage area to shorten the processing duration of the test instruction.

[0096] In other embodiments, the first data is received together with the control command, that is, the test instruction further includes the first data, and the device stores the first data in the preset storage area when receiving the control command.

[0097] When executing the test instruction, corresponding address data and / or control data are generally input to the pins of the memory. This application embodiment stores the first data in partitions according to different data types.

[0098] In some embodiments, the first data includes address data.

[0099] Among them, the address data includes a storage cell array address, a group address, a row address, and a column address, the preset storage area includes a first sub-storage area and a second sub-storage area, and the method includes:

[0100] Store the memory cell array address in the first sub-storage area therein, and store the group address, row address, and column address in the second sub-storage area therein.

[0101] Among them, the memory cell array address is the bank address. Usually, each memory has multiple memory cell arrays (i.e., banks), and each data bit is independently stored in a memory cell addressed by a row address and a column address in a specified bank.

[0102] In some embodiments, the pre-set storage area further includes a third sub-storage area, the first data further includes control data, and the method further includes:

[0103] Store the control data in the third sub-storage area.

[0104] In some embodiments, the pre-set storage area includes a fourth sub-storage area, and the method includes:

[0105] Read the second data of the corresponding pin of the memory into the fourth sub-storage area.

[0106] In some embodiments, the first sub-storage area, the second sub-storage area, the third sub-storage area, and the fourth sub-storage area are storage areas composed of memories that can be read and written at any time. This memory can be a first-in-first-out (FIFO) memory, a BRAM memory, etc. The embodiments of the present application are not limited thereto.

[0107] In an alternative implementation, the first sub-storage area, the second sub-storage area, the third sub-storage area, and the fourth sub-storage area are all FIFO storage areas.

[0108] The FIFO storage area is a storage area composed of first-in-first-out memories. According to the method of the above embodiments, the execution device of this method, under the drive of a control signal, will control to read data from the first sub-storage area, the second sub-storage area, and the third sub-storage area and output them to the memory pins at the same time until the first sub-storage area, the second sub-storage area, and the third sub-storage area are empty.

[0109] During the implementation of each test instruction, since the clocks of the device that sends the test instruction and the device that controls the memory according to the test instruction are different, the first sub-storage area, the second sub-storage area, the third sub-storage area, and the fourth sub-storage area are all asynchronous first-in-first-out memories. By using this asynchronous first-in-first-out memory to cache the data corresponding to the test instruction, the timing of the device that sends the test instruction and the device that controls the memory according to the test instruction will not affect the memory.

[0110] In some embodiments, when data is output to the memory pin, the output data is a waveform signal. The output of this waveform signal is preferably implemented using RTL (Register Transfer Level), which can balance the timing accuracy and flexibility of the output waveform.

[0111] In the above embodiments, the memory to be tested is a DRAM chip, and it can also be other memory devices capable of storing information, such as SRAM (Static Random Access Memory).

[0112] In some exemplary embodiments, the method of the above embodiments of the present application can be executed by an FPGA or other programmable logic devices. It should be noted that an FPGA (Field Programmable Gate Array) is a further developed product based on programmable devices such as PAL, GAL, and CPLD. It should be noted that the above preset storage area is set in the execution device of the method of the present application.

[0113] In some exemplary embodiments, the test instruction is sent by the CPU. It should be noted that the CPU here refers to a processor capable of software development using high-level languages such as C language, including but not limited to the central processing unit, MPU (Microprocessor), MCU (Microcontroller Unit), DSP (Digital Signal Processing), GPU (Graphics Processing Unit), and the CPU core inside the FPGA, etc. In the CPU, C language code is used to write the relevant control program for the memory. The CPU can receive the relevant operation information input by the user through the serial port terminal software from the serial port parsing unit, and then generate the test instruction using C language code. Preferably, the CPU is provided with a corresponding serial port command parsing module for receiving the relevant operation information. The CPU is also provided with a corresponding communication module for sending down the test instruction information. When the memory test method is executed by the FPGA, the communication module can include a communication unit with the FPGA, and the communication unit with the FPGA is used to send down the test instruction to the FPGA according to the communication method agreed with the FPGA, and then the FPGA receives the test instruction through the interface communicating with the CPU.

[0114] The method of the above embodiments of the present application enters the test mode of the memory by setting a corresponding device (such as an FPGA) between the device sending the test instruction (such as the CPU) and the memory, and further realizes the parsing of non-standard commands. By converting the test instruction into an applicable control signal, and then testing the memory under the drive of the control signal, it is possible to complete the modification / regulation of the relevant parameters of the memory, such as adjusting the voltage and / or timing inside the memory, modifying the parameters of the interface available for debugging of the memory, and so on.

[0115] To better understand the present invention application, in this embodiment, it is assumed that the device executing the method is an FPGA, and the execution of the above method is analyzed by taking the example of the CPU sending a Read Chipid instruction to the FPGA. The Read Chipid instruction, as described above, is an instruction for reading the ID of a DRAM chip, and information such as the production date and packaging and testing manufacturer of the DRAM chip is stored in the ID. The timing diagram of the Read Chipid instruction is as Figure 2 shown. Among them, CK_t and CK_c represent differential clock (signal) inputs, Dummy-A indicates that there is no read / write under the corresponding differential clock, and the pin of DQ5 (data bus 5) does not change. DATA1...DATAn are bits that make up the Chipid (chip identification) information. According to this Figure 2 it can be seen that this instruction has no change in DQS (data strobe signal) and belongs to an instruction that does not meet the JEDEC specification.

[0116] In this scenario, after the CPU sends a test instruction, the FPGA parses that the control command therein is a first type of command, and then converts the control command to obtain a corresponding control signal.

[0117] As Figure 3 shown, the receiving module of the FPGA synchronously receives first data, which includes control data and address data. Among them, the control data are 3'b111, 3'b101, 3'b111, 3'b111,..., 3'b111 from front to back, a total of 63 3-bit binary data. The address data includes a BANK signal and an address signal. Among them, the BANK signal is a total of 63 4-bit binary data 4'b0000 from front to back; the address signal is 0x1FFFF, 0x0008A, 0x1FFFF, 0x1FFFF,..., 0x1FFFF from front to back, a total of 63 17-bit binary data;

[0118] The FPGA then stores the control data, BANK signal, and address signal into corresponding first-in first-out memories, a first-in first-out memory, a second-in first-out memory, and a third-in first-out memory respectively. 63 3-bit binary data, 63 4-bit binary data, and 63 17-bit binary data are stored in these three first-in first-out memories respectively;

[0119] Under the drive of the control signal, the execution module of the FPGA controls the data read from three first-in-first-out memories and outputs them to the corresponding DRAM chip pins simultaneously until these three first-in-first-out memories are empty. At the same time, when it is detected that the issued instruction is the Read Chipid instruction, the signals of all DQ (gated data) pins of the DRAM chip are immediately read out and stored in the corresponding fourth first-in-first-out memory. There are a total of 60 data, and only the data of DQ5 is the Chipid data we need.

[0120] If the data in the fourth first-in-first-out memory is not empty, the data in the fourth first-in-first-out memory is read out and sent to the CPU. After receiving the data, the CPU separately extracts the data of the DQ5 pin and prints it in the serial port.

[0121] The second aspect of the present application provides a memory test device, as Figure 4 shown, the device includes:

[0122] A receiving module 1, configured to receive a test instruction, where the test instruction includes a control command;

[0123] An analysis module 2, configured to analyze the command type to which the control command belongs;

[0124] A conversion module 〈0000262〉, configured to convert the control command into a corresponding control signal when the analysis module 2 analyzes that the command type to which the control command belongs belongs to the first command type;

[0125] An execution module 4, configured to output the corresponding first data in the preset storage area to the corresponding pin of the memory to be tested at the falling edge of the command clock according to the control signal; and / or, read the second data of the corresponding pin of the memory to be tested into the preset storage area.

[0126] In some embodiments, the first command type is a command that does not meet the JEDEC specification. < /

[0127] In some embodiments, the conversion module 3 is specifically configured to:

[0128] Search for the signal generation data corresponding to the control command in the stored command list, and generate a converted control signal according to the signal generation data.

[0129] In some embodiments, the conversion module 3 is further specifically configured to:

[0130] If multiple signal generation data corresponding to the control command are found in the stored command list, select the signal generation data corresponding to the type identifier of the memory to be tested from them for control signal generation.

[0131] In some embodiments, the device further includes:

[0132] A first prompting module, configured to output information for prompting that the test instruction is an incorrect instruction when the signal generation data corresponding to the control command cannot be found according to the stored command list.

[0133] In some embodiments, the device further includes:

[0134] A decoding module, configured to decode the control command to obtain a corresponding control signal when the command type to which the control command belongs parsed by the parsing module 2 belongs to a second command type.

[0135] In some embodiments, the second command type is a command that complies with the JEDEC specification.

[0136] In some embodiments, the execution module 4 includes:

[0137] An output unit, configured to output corresponding first data in a preset storage area to corresponding pins of the memory under test;

[0138] And / or

[0139] A reading unit, configured to read second data of corresponding pins of the memory under test into the preset storage area.

[0140] In some embodiments, the test instruction further includes the first data, and the device further includes:

[0141] A storage module, configured to store the first data in the preset storage area.

[0142] In some embodiments, the first data includes address data.

[0143] In some embodiments, the address data includes a storage unit array address, a group address, a row address, and a column address, the preset storage area includes a first sub-storage area and a second sub-storage area, and the storage module specifically includes:

[0144] A first storage unit, configured to store the storage unit array address in the first sub-storage area therein;

[0145] A second storage unit, configured to store the group address, the row address, and the column address in the second sub-storage area therein.

[0146] In some embodiments, the preset storage area further includes a third sub-storage area, the first data further includes control data, and the storage module further includes:

[0147] A third storage unit, configured to store the control data in the third sub-storage area.

[0148] In some embodiments, the preset storage area includes a fourth sub-storage area, and the reading unit is specifically configured to:

[0149] Read the second data of the corresponding pin of the memory into the fourth sub-storage area.

[0150] In some embodiments, the first sub-storage area, the second sub-storage area, the third sub-storage area, and the fourth sub-storage area are all FIFO storage areas.

[0151] In some embodiments, the memory to be tested is a DRAM chip.

[0152] A third aspect of the present application provides a memory testing device, which includes the memory testing device described in any one of the above, and the device further includes:

[0153] An instruction sending device, configured to send the test instruction to the memory testing device.

[0154] In some embodiments, the instruction sending device is a CPU.

[0155] Wherein, the device further includes a universal asynchronous receiver / transmitter;

[0156] The CPU is connected to the user terminal through the universal asynchronous receiver / transmitter to receive the operation information corresponding to the test instruction input by the user terminal.

[0157] The functions and implementation manners of the units or modules in the above embodiments of the device in the present application are the same as those in the embodiments of the above memory testing method. For specific analysis, reference can be made to the embodiments of the above memory testing method. To avoid repetition, it will not be elaborated here.

[0158] The above is the preferred implementation manner of the present application. It should be noted that for those of ordinary skill in the art in the technical field of the present application, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present application.

Claims

1. A memory testing method, characterized in that, The method includes: Receiving a test instruction, where the test instruction includes a control command; Parsing the command type to which the control command belongs; When it is parsed that the command type to which the control command belongs belongs to the first command type, converting the control command into a corresponding control signal; the first command type is a command that cannot directly decode to obtain a corresponding control signal; Outputting corresponding first data in a preset storage area to corresponding pins of a memory under test according to the control signal at the falling edge of a command clock; and / or, reading second data of corresponding pins of the memory under test into the preset storage area.

2. The memory test method according to claim 1, wherein: The first command type is a command that does not meet the JEDEC specification.

3. A memory test method according to claim 1, wherein, The converting the control command into a corresponding control signal specifically includes: Searching for signal generation data corresponding to the control command in a stored command list, and generating a control signal according to the signal generation data.

4. The memory test method according to claim 1, wherein The method further includes: When it is parsed that the command type to which the control command belongs belongs to the second command type, decoding the control command to obtain a corresponding control signal.

5. The memory test method according to claim 1, wherein The test instruction further includes the first data, and the method further includes: Storing the first data into the preset storage area.

6. The memory test method according to claim 5, characterized in that, The first data includes address data and control data, the address data includes a storage cell array address, a group address, a row address, and a column address, the preset storage area includes a first sub-storage area, a second sub-storage area, and a third sub-storage area, and the method includes: Storing the storage cell array address into the first sub-storage area therein, storing the group address, row address, and column address into the second sub-storage area therein, and storing the control data into the third sub-storage area.

7. A memory test device, characterized in that, The device includes: A receiving module, configured to receive a test instruction, where the test instruction includes a control command; An analysis module, configured to analyze the command type to which the control command belongs; A conversion module, configured to convert the control command into a corresponding control signal when the analysis module analyzes that the command type to which the control command belongs belongs to the first command type; An execution module, configured to output corresponding first data in a preset storage area to corresponding pins of a memory under test according to the control signal at the falling edge of a command clock; and / or, read second data of corresponding pins of the memory under test into the preset storage area.

8. The memory test device according to claim 7, wherein:

9. The memory test device according to claim 8, characterized in that, The first command type is a command that does not meet the JEDEC specification. The conversion module is specifically configured to:

10. The memory test device according to claim 7, wherein, Search for signal generation data corresponding to the control command in a stored command list, and generate a control signal according to the signal generation data. The device further includes:

11. The memory test device according to claim 7, wherein, A decoding module, configured to decode the control command to obtain a corresponding control signal when the analysis module analyzes that the command type to which the control command belongs belongs to the second command type. The test instruction further includes the first data, and the device further includes: A storage module, configured to store the first data into the preset storage area.

12. The memory test device according to claim 11, wherein: The first data includes address data and control data. The address data includes a storage cell array address, a group address, a row address, and a column address. The preset storage area includes a first sub-storage area, a second sub-storage area, and a third sub-storage area. The storage module specifically includes: A first storage unit for storing the storage cell array address in the first sub-storage area therein; A second storage unit for storing the group address, row address, and column address in the second sub-storage area therein; A third storage unit for storing the control data in the third sub-storage area.

13. A memory test device, characterized in that, The device includes the memory test device according to any one of claims 7-12. The device further includes: An instruction sending device for sending the test instruction to the memory test device.

14. The memory test device according to claim 13, characterized in that, The instruction sending device is a CPU.

15. The memory test device according to claim 14, wherein: The device further includes a universal asynchronous receiver / transmitter; The CPU is connected to the user terminal through the universal asynchronous receiver / transmitter to receive operation information corresponding to the test instruction input by the user terminal.

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