Chip interconnection packaging method and chip package

Abstract

The application provides a chip interconnection packaging method and a chip packaging element. The interconnection packaging method is used for packaging at least two upper and lower electrode chips, and comprises the following steps: connecting each first electrode to each other by additive manufacturing to form a first interconnection channel, and extending the first interconnection channel to a first preset plane; preparing a second interconnection channel on the first preset plane by additive manufacturing, and extending the first interconnection channel and the second interconnection channel to a second preset plane, respectively; connecting each second electrode to the second interconnection channel by additive manufacturing, and pouring glue to package the chip to obtain a chip packaging element. The application grows an interconnection circuit directly on the electrode of the chip, avoids the problem that the quality of a welding spot is difficult to control in a traditional welding process, improves the reliability of a product, can package multiple chips in batches, greatly improves the packaging efficiency, and eliminates a packaging substrate, thereby reducing the production cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a chip interconnection packaging method and a chip packaging. BACKGROUND

[0002] Most of the chips on the market are upper and lower electrode chips, that is, the electrodes of the chip are arranged on the upper and lower two different surfaces of the chip. The interconnection packaging method of this type of chip is to first fixedly bond the lower electrodes of each chip to the corresponding electrodes of the packaging substrate, and then use a wire bonding machine to wire bond the upper electrodes of each chip to the corresponding electrodes of the packaging substrate, so as to realize the electrical interconnection of each chip.

[0003] However, the current interconnection packaging method has the following problems: each chip needs to be wire bonded one by one, the packaging efficiency is low; the quality of the solder joints is difficult to guarantee, and the reliability of the packaged product is low. SUMMARY

[0004] In view of the above problems, the present application is proposed to provide a chip interconnection packaging method and a chip packaging that can overcome the above problems or at least partially solve the above problems, comprising:

[0005] A chip interconnection packaging method for packaging at least two chips, the chip comprising a first electrode and a second electrode arranged oppositely; comprising:

[0006] Each of the first electrodes is connected to each other by additive manufacturing to form a first interconnection channel, and the first interconnection channel is extended upward to a first predetermined plane;

[0007] A second interconnection channel is prepared on the first predetermined plane by additive manufacturing, and the first interconnection channel and the second interconnection channel are respectively extended upward to a second predetermined plane;

[0008] Each of the second electrodes is connected to the second interconnection channel by additive manufacturing, and the chip is encapsulated by glue to obtain a chip packaging.

[0009] Preferably, the step of connecting each of the first electrodes to each other by additive manufacturing to form a first interconnection channel, and extending the first interconnection channel upward to a first predetermined plane, comprises:

[0010] Each of the chips is placed on the surface of a first carrier board; wherein each of the first electrodes faces upward;

[0011] A first encapsulation glue layer is laid on the side of each of the chips;

[0012] The first interconnection channel is prepared on the surface of each chip and the first encapsulation layer by additive manufacturing;

[0013] The first conductive column is prepared on the surface of the first interconnection channel by additive manufacturing, and the second encapsulation layer is laid on the circumferential side of the first conductive column.

[0014] Preferably, the step of preparing the first interconnection channel on the surface of each chip and the first encapsulation layer by additive manufacturing comprises:

[0015] A photosensitive material is coated on the surface of each chip and the first encapsulation layer, and exposure and development are performed to expose a first target area on the surface of each chip and the first encapsulation layer; wherein the first target area is connected with the first electrode respectively;

[0016] The first interconnection channel is prepared on the surface of the first target area by additive manufacturing;

[0017] The photosensitive material is removed.

[0018] Preferably, the step of preparing the second interconnection channel on the first preset plane by additive manufacturing, and extending the first interconnection channel and the second interconnection channel to the second preset plane respectively comprises:

[0019] The second interconnection channel is prepared on the surface of the second encapsulation layer by additive manufacturing;

[0020] The first extension column is prepared on the surface of the first conductive column and the second extension column is prepared on the surface of the second interconnection channel by additive manufacturing respectively, and the third encapsulation layer is laid on the circumferential side of the first extension column and the second extension column.

[0021] Preferably, the step of preparing the second interconnection channel on the surface of the second encapsulation layer by additive manufacturing comprises:

[0022] A photosensitive material is coated on the surface of the second encapsulation layer, and exposure and development are performed to expose a second target area on the surface of the second encapsulation layer;

[0023] The second interconnection channel is prepared on the surface of the second target area by additive manufacturing;

[0024] The photosensitive material is removed.

[0025] Preferably, the step of preparing a second interconnection channel on the first preset plane by additive manufacturing, and making the first interconnection channel and the second interconnection channel respectively extend to the second preset plane, further comprises:

[0026] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0027] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0028] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0029] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0030] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0031] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0032] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0033] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0034] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0035] Preferably, the step of preparing a first extension channel and a second extension channel on the surface of the first extension column, the second extension column and the third encapsulation layer by additive manufacturing, further comprises:

[0036] A chip package prepared by the interconnection packaging method according to any one of the above, comprising: at least two chips and a packaging glue layer wrapped outside the chips; the first electrodes of each of the chips are connected to each other and extend to the surface of the packaging glue layer; the second electrodes of each of the chips are connected to each other and extend to the surface of the packaging glue layer.

[0037] The present application has the following advantages:

[0038] In the embodiments of the present application, in order to solve the problems of low packaging efficiency, difficult to guarantee the quality of solder joints and low product reliability of the existing interconnection packaging method, the present application provides a solution of interconnecting the same type of electrodes of different chips by additive manufacturing, specifically: "connecting each of the first electrodes to each other by additive manufacturing to form a first interconnection path, and extending the first interconnection path upward to a first preset plane; preparing a second interconnection path on the first preset plane by additive manufacturing, and extending the first interconnection path and the second interconnection path upward to a second preset plane, respectively; connecting each of the second electrodes to the second interconnection path by additive manufacturing, and pouring glue to package the chips to obtain a chip package". By directly growing interconnection lines on the electrodes of the chips, the problem of difficult to control the quality of solder joints caused by traditional soldering process is avoided, the reliability of the product is improved, and a plurality of the chips can be packaged in batches, which greatly improves the packaging efficiency and eliminates the packaging substrate, thereby reducing the production cost. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the present application, the drawings needed to be used in the description of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] Figure 1 is a step flow chart of a chip interconnection packaging method provided by an embodiment of the present application;

[0041] Figure 2 is a flowchart of a chip interconnection packaging method provided by an embodiment of the present application;

[0042] Figure 3 is a schematic diagram of the internal structure of a chip package provided by an embodiment of the present application.

[0043] The reference signs in the drawings of the specification are as follows:

[0044] 100, chip; 110, first electrode; 111, first interconnection channel; 112, first conductive column; 113, first extension column; 114, first extension channel; 120, second electrode; 121, conductive channel; 122, second conductive column; 123, second interconnection channel; 124, second extension column; 125, second extension channel; 210, first encapsulation layer; 220, second encapsulation layer; 230, third encapsulation layer; 240, fourth encapsulation layer; 300, first carrier plate; 400, second carrier plate. DETAILED DESCRIPTION

[0045] In order to make the objectives, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application.

[0046] It should be noted that in any embodiment of the present application, the interconnection packaging method is used to package at least two chips 100, and the chip 100 is an upper and lower electrode chip, i.e., it includes oppositely arranged first electrodes 110 and second electrodes 120. As an example, the first electrode 110 is a positive electrode (P electrode), and the second electrode 120 is a negative electrode (N electrode); as another example, the first electrode 110 is a negative electrode (N electrode), and the second electrode 120 is a positive electrode (P electrode).

[0047] Reference Figures 1-2 An interconnection packaging method of a chip is shown, which comprises:

[0048] S110, connecting each first electrode 110 to each other by additive manufacturing to form a first interconnection channel 111, and extending the first interconnection channel 111 upward to a first preset plane;

[0049] S120, preparing a second interconnection channel 123 on the first preset plane by additive manufacturing, and extending the first interconnection channel 111 and the second interconnection channel 123 to a second preset plane, respectively;

[0050] S130, connecting each second electrode 120 to the second interconnection channel 123 by additive manufacturing, and encapsulating the chip 100 by pouring glue to obtain a chip packaging piece.

[0051] In the embodiments of the present application, in order to solve the problems of low packaging efficiency, poor solder quality and low product reliability of the existing interconnection packaging method, the present application provides a solution for interconnecting the same type of electrodes of different chips 100 by using additive manufacturing, specifically: "interconnect each first electrode 110 by additive manufacturing to form a first interconnection path 111, and extend the first interconnection path 111 upward to a first predetermined plane; prepare a second interconnection path 123 on the first predetermined plane by additive manufacturing, and extend the first interconnection path 111 and the second interconnection path 123 upward to a second predetermined plane respectively; connect each second electrode 120 to the second interconnection path 123 by additive manufacturing, and encapsulate the chip 100 by glue to obtain a chip package". By growing interconnection lines directly on the electrodes of the chip 100, the problem of difficult control of solder quality caused by traditional soldering process is avoided, the reliability of the product is improved, and a plurality of chips 100 can be packaged in batches, greatly improving the packaging efficiency, and eliminating the packaging substrate, reducing the production cost.

[0052] In the following, the interconnection packaging method of a chip in the present exemplary embodiment will be further described.

[0053] As described in step S110, interconnect each first electrode 110 by additive manufacturing to form a first interconnection path 111, and extend the first interconnection path 111 upward to a first predetermined plane.

[0054] Each chip 100 is arranged at intervals on the same horizontal plane, each first electrode 110 faces upward, and the first interconnection path 111 is prepared on the plane where the first electrode 110 is located by additive manufacturing (Additive Manufacturing, AM), so that each first electrode 110 is interconnected, and a first conductive column 112 is prepared on the surface of the first interconnection path 111 by additive manufacturing, so that the first interconnection path 111 extends upward to the first predetermined plane.

[0055] It should be noted that additive manufacturing, also known as 3D printing, is a manufacturing technology that uses digital model files as the basis, and through software and numerical control system, special metal materials, non-metal materials or medical biological materials are stacked layer by layer in the form of extrusion, sintering, melting, light curing, spraying, etc. to manufacture solid objects. Specifically, the additive manufacturing method involved in the present application can be one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating and chemical plating.

[0056] The first interconnection path 111 and the first conductive post 112 can be made of the same conductive material as the first electrode 110.

[0057] As described in step S120, a second interconnection path 123 is prepared on the first preset plane by additive manufacturing, and the first interconnection path 111 and the second interconnection path 123 are respectively extended upward to the second preset plane.

[0058] The second interconnection path 123 is prepared on the first preset plane by additive manufacturing, and the first extension post 113 and the second extension post 124 are prepared on the surface of the first conductive post 112 and the second interconnection path 123 respectively by additive manufacturing, so that the first interconnection path 111 and the second interconnection path 123 extend upward to the second preset plane respectively.

[0059] The first extension post 113 may be made of the same conductive material as the first electrode 110; the second interconnection path 123 and the second extension post 124 may be made of the same conductive material as the second electrode 120.

[0060] As described in step S130, each of the second electrodes 120 is connected to the second interconnection path 123 by additive manufacturing, and the chip 100 is encapsulated with potting compound to obtain a chip package.

[0061] Each of the chips 100 is arranged at intervals on the same horizontal plane with each of the second electrodes 120 facing upwards. An extended circuit is prepared by additive manufacturing, and each of the second electrodes 120 is connected to the second interconnection path 123. The chips 100 are then encapsulated with encapsulating glue to obtain the chip package.

[0062] The extension circuit can be made of the same conductive material as the second electrode 120.

[0063] The encapsulating adhesive includes one or more of epoxy resin, silicone, PI (Polyimide) resin, PE (Polyethylene) resin, and PT (Phenolic Triazine) resin. After curing, the encapsulating adhesive exhibits good insulation and sealing properties, providing protection and preventing the product from getting damp.

[0064] In one embodiment of this application, the specific process of “interconnecting each of the first electrodes 110 to form a first interconnection path 111 by additive manufacturing and extending the first interconnection path 111 upward to a first preset plane” can be further described in conjunction with the following description.

[0065] Placing each of the chips 100 on the surface of the first carrier board 300; wherein each of the first electrodes 110 faces upward. Specifically, arranging each of the chips 100 on the surface of the first carrier board 300 at intervals, so that each of the first electrodes 110 faces upward.

[0066] Laying the first encapsulation adhesive layer 210 on the periphery of each of the chips 100. Specifically, pouring the first encapsulation adhesive layer 210 on the surface of the first carrier board 300, so that the first encapsulation adhesive layer 210 wraps around the periphery of each of the chips 100, and the top of the first encapsulation adhesive layer 210 extends to a position not higher than the top of each of the first electrodes 110.

[0067] Prepared the first interconnection passage 111 on the surface of each of the chips 100 and the first encapsulation adhesive layer 210 by additive manufacturing; wherein the first interconnection passage 111 is connected with each of the first electrodes 110 respectively. Specifically, prepared the first interconnection passage 111 horizontally extending on the surface of each of the chips 100 and the first encapsulation adhesive layer 210 by additive manufacturing, so that the first interconnection passage 111 is connected with each of the first electrodes 110 respectively.

[0068] Prepared the first conductive column 112 on the surface of the first interconnection passage 111 by additive manufacturing, and laid the second encapsulation adhesive layer 220 on the periphery of the first conductive column 112. Specifically, prepared the first conductive column 112 vertically extending on the surface of the first interconnection passage 111 by additive manufacturing, so that the top of the first conductive column 112 extends to the first preset plane, and poured the second encapsulation adhesive layer 220 on the surface of the first encapsulation adhesive layer 210, so that the second encapsulation adhesive layer 220 wraps around the periphery of the first conductive column 112, and the top of the second encapsulation adhesive layer 220 extends to a position not higher than the top of the first conductive column 112.

[0069] In an embodiment of the present application, the specific process of “laying the first encapsulation adhesive layer 210 on the periphery of each of the chips 100” can be further illustrated in combination with the following description.

[0070] Pouring the encapsulation adhesive to a height not higher than the top of the first electrode 110. Specifically, pouring the encapsulation adhesive on the surface of the first carrier board 300, so that the encapsulation adhesive wraps around the periphery of the chip 100, and the top of the encapsulation adhesive extends to a position not higher than the top of the first electrode 110.

[0071] Carrying out drying treatment on the encapsulation adhesive to form the first encapsulation adhesive layer 210. Specifically, carrying out drying treatment on the encapsulation adhesive at 60-160°C to form the first encapsulation adhesive layer 210.

[0072] In an embodiment of the present application, the specific process of "preparing the first interconnection passage 111 on the surface of each chip 100 and the first encapsulation layer 210 by additive manufacturing" can be further illustrated in combination with the following description.

[0073] A photosensitive material is coated on the surface of each chip 100 and the first encapsulation layer 210, and exposure and development are performed to expose a first target area on the surface of each chip 100 and the first encapsulation layer 210; wherein the first target area is connected with the first electrode 110 respectively. Specifically, the photosensitive material is coated on the surface of each chip 100 and the first encapsulation layer 210, and exposure and development are performed to solidify the photosensitive material that has undergone photopolymerization reaction to form a first photosensitive material layer, and the photosensitive material that has not undergone photopolymerization reaction (i.e. the photosensitive material on the surface of the first target area) is washed away. The photosensitive material includes one or more of photoresist (including positive photoresist and negative photoresist), photosensitive polyimide resin, photosensitive sol-gel or its mixture or composition, and a mixed solution of PhTES, N-methyl-2-pyrrolidone and polymethyl methacrylate, which has good photosensitivity.

[0074] The first interconnection passage 111 is prepared on the surface of the first target area by additive manufacturing. Specifically, the first interconnection passage 111 extending horizontally is prepared on the surface of the first target area by additive manufacturing.

[0075] The photosensitive material is removed. Specifically, the first photosensitive material layer is removed by a stripping agent.

[0076] In an embodiment of the present application, the specific process of "preparing the first conductive pillar 112 on the surface of the first interconnection passage 111 by additive manufacturing" can be further illustrated in combination with the following description.

[0077] A photosensitive material is coated on the surface of the first interconnection passage 111, and exposure and development are performed to expose a first target growth area on the surface of the first interconnection passage 111. Specifically, the photosensitive material is coated on the surface of the first encapsulation layer 210, each first electrode 110 and the first interconnection passage 111, and exposure and development are performed to solidify the photosensitive material that has undergone photopolymerization reaction to form a second photosensitive material layer, and the photosensitive material that has not undergone photopolymerization reaction (i.e. the photosensitive material on the surface of the first target growth area) is washed away.

[0078] The first conductive column 112 is prepared on the surface of the first target growth region by additive manufacturing. Specifically, the first conductive column 112 extending longitudinally is prepared on the surface of the first target growth region by additive manufacturing.

[0079] The photosensitive material is removed. Specifically, the second photosensitive material layer is removed by a degreasing agent.

[0080] In an embodiment of the present application, the specific process of "laying the second encapsulation adhesive layer 220 on the periphery of the first conductive column 112" can be further illustrated in combination with the following description.

[0081] The encapsulation adhesive is filled to a height not higher than the top of the first conductive column 112. Specifically, the encapsulation adhesive is poured on the surface of the first encapsulation adhesive layer 210, so that the encapsulation adhesive wraps around the periphery of the first conductive column 112, and the top of the encapsulation adhesive extends to a position not higher than the top of the first conductive column 112.

[0082] The encapsulation adhesive is subjected to drying treatment to form the second encapsulation adhesive layer 220. Specifically, the encapsulation adhesive is subjected to drying treatment at 60-160°C to form the second encapsulation adhesive layer 220.

[0083] In an embodiment of the present application, the specific process of "preparing the second interconnection passage 123 on the first preset plane by additive manufacturing, and making the first interconnection passage 111 and the second interconnection passage 123 respectively extend upward to a second preset plane" can be further illustrated in combination with the following description.

[0084] The second interconnection passage 123 is prepared on the surface of the second encapsulation adhesive layer 220 by additive manufacturing. Specifically, the second interconnection passage 123 extending horizontally is prepared on the surface of the second encapsulation adhesive layer 220 by additive manufacturing.

[0085] The first extension column 113 is prepared on the surface of the first conductive column 112 and the second extension column 124 is prepared on the surface of the second interconnection passage 123 by additive manufacturing, and a third encapsulation adhesive layer 230 is laid on the circumferential side of the first extension column 113 and the second extension column 124. Specifically, the first extension column 113 extending longitudinally is prepared on the surface of the first conductive column 112 and the second extension column 124 extending longitudinally is prepared on the surface of the second interconnection passage 123 by additive manufacturing, so that the top of the first extension column 113 and the second extension column 124 extends to the second preset plane respectively, and the third encapsulation adhesive layer 230 is poured on the surface of the second encapsulation adhesive layer 220, so that the third encapsulation adhesive layer 230 is wrapped on the circumferential side of the first extension column 113 and the second extension column 124, and the top of the third encapsulation adhesive layer 230 extends to a position not higher than the top of the first extension column 113 and the second extension column 124.

[0086] In an embodiment of the present application, the specific process of "preparing the second interconnection passage 123 on the surface of the second encapsulation adhesive layer 220 by additive manufacturing" can be further illustrated in combination with the following description.

[0087] A photosensitive material is coated on the surface of the second encapsulation adhesive layer 220, and exposure and development are performed to expose the second target area on the surface of the second encapsulation adhesive layer 220. Specifically, the photosensitive material is coated on the surface of the second encapsulation adhesive layer 220, and exposure and development are performed, so that the photosensitive material that has undergone photopolymerization reaction is cured to form a third photosensitive material layer, and the photosensitive material that has not undergone photopolymerization reaction (i.e. the photosensitive material on the surface of the second target area) is washed away.

[0088] The second interconnection passage 123 is prepared on the surface of the second target area by additive manufacturing. Specifically, the second interconnection passage 123 extending horizontally is prepared on the surface of the second target area by additive manufacturing.

[0089] The photosensitive material is removed. Specifically, the third photosensitive material layer is removed by a stripping agent.

[0090] In an embodiment of the present application, the specific process of "preparing the first extension column 113 on the surface of the first conductive column 112 and the second extension column 124 on the surface of the second interconnection passage 123 by additive manufacturing" can be further illustrated in combination with the following description.

[0091] A photosensitive material is coated on surfaces of the first conductive pillars 112 and the second interconnection passages 123, and exposure and development are performed to expose the second target growth region on the surface of the first conductive pillars 112 and the third target growth region on the surface of the second interconnection passages 123. Specifically, the photosensitive material is coated on surfaces of the second encapsulation adhesive layer 220, the first conductive pillars 112 and the second interconnection passages 123, and exposure and development are performed to solidify the photosensitive material that has undergone photopolymerization reaction to form a fourth photosensitive material layer, and the photosensitive material that has not undergone photopolymerization reaction (i.e. the photosensitive material on the surfaces of the second target growth region and the third target growth region) is washed away.

[0092] The first extension pillars 113 on the surface of the second target growth region and the second conductive pillars 122 on the surface of the third target growth region are respectively prepared by additive manufacturing. Specifically, the first extension pillars 113 extending longitudinally on the surface of the second target growth region and the second conductive pillars 122 extending longitudinally on the surface of the third target growth region are respectively prepared by additive manufacturing.

[0093] The photosensitive material is removed. Specifically, the fourth photosensitive material layer is removed by a stripping agent.

[0094] In an embodiment of the present application, the specific process of "laying a third encapsulation adhesive layer 230 on the periphery of the first extension pillars 113 and the second extension pillars 124" can be further explained in combination with the following description.

[0095] The encapsulation adhesive is poured to a height not higher than the top of the first extension pillars 113 and the second extension pillars 124. Specifically, the encapsulation adhesive is poured on the surface of the second encapsulation adhesive layer 220 so that the encapsulation adhesive wraps around the periphery of the first extension pillars 113 and the second extension pillars 124, and the top of the encapsulation adhesive extends to a position not higher than the top of the first extension pillars 113 and the second extension pillars 124.

[0096] The encapsulation adhesive is subjected to drying treatment to form the third encapsulation adhesive layer 230. Specifically, the encapsulation adhesive is subjected to drying treatment at 60-160°C to form the third encapsulation adhesive layer 230.

[0097] In an embodiment of the present application, the specific process of "preparing the second interconnection passages 123 on the first preset plane by additive manufacturing, and making the first interconnection passages 111 and the second interconnection passages 123 respectively extend upward to the second preset plane" can be further explained in combination with the following description.

[0098] The first extended passage 114 and the second extended passage 125 are respectively prepared on surfaces of the first extension column 113, the second extension column 124 and the third encapsulation layer 230 by additive manufacturing. The first extended passage 114 is connected with the first extension column 113. The second extended passage 125 is connected with the second extension column 124. Specifically, after the first extension column 113 and the second extension column 124 are respectively prepared on surfaces of the first conductive column 112 and the second interconnection passage 123 by additive manufacturing, and the third encapsulation layer 230 is laid on the circumferential side of the first extension column 113 and the second extension column 124, the first extended passage 114 and the second extended passage 125 which extend horizontally are respectively prepared on surfaces of the first extension column 113, the second extension column 124 and the third encapsulation layer 230 by additive manufacturing, so that the first extended passage 114 is connected with the first extension column 113, and the second extended passage 125 is connected with the second extension column 124.

[0099] In an embodiment of the present application, the specific process of "the first extended passage 114 and the second extended passage 125 are respectively prepared on surfaces of the first extension column 113, the second extension column 124 and the third encapsulation layer 230 by additive manufacturing" can be further illustrated in combination with the following description.

[0100] A photosensitive material is coated on surfaces of the first extension column 113, the second extension column 124 and the third encapsulation layer 230, and exposure and development are performed to expose third target areas and fourth target areas on surfaces of the first extension column 113, the second extension column 124 and the third encapsulation layer 230. The third target areas are connected with the first extension column 113. The fourth target areas are connected with the second extension column 124. Specifically, the photosensitive material is coated on surfaces of the first extension column 113, the second extension column 124 and the third encapsulation layer 230, and exposure and development are performed, so that the photosensitive material which has occurred photopolymerization reaction is solidified to form a fifth photosensitive material layer, and the photosensitive material (i.e. the photosensitive material on surfaces of the third target areas and the fourth target areas) which has not occurred photopolymerization reaction is washed away.

[0101] The first extended passage 114 is prepared on a surface of the third target area, and the second extended passage 125 is prepared on a surface of the fourth target area by additive manufacturing. Specifically, the first extended passage 114 which extends horizontally is prepared on the surface of the third target area, and the second extended passage 125 which extends horizontally is prepared on the surface of the fourth target area by additive manufacturing.

[0102] The photosensitive material is removed. Specifically, the fifth photosensitive material layer is removed by a remover.

[0103] In an embodiment of the present application, the specific process of connecting each second electrode 120 to the second interconnection path 123 by additive manufacturing can be further described as follows.

[0104] Each chip 100 is placed on the surface of the second carrier board 400, with each second electrode 120 facing upwards. Specifically, each chip 100 is flipped onto the surface of the second carrier board 400, with each second electrode 120 facing upwards, and the first carrier board 300 is removed.

[0105] A vertical through hole is etched inside the first encapsulation layer 210 and the second encapsulation layer 220, with the through hole corresponding to each second electrode 120, and the through hole being connected to the second interconnection path 123. Specifically, a photosensitive material is coated and exposed and developed to form an etching window, which facilitates etching and removing the part inside the first encapsulation layer 210 and the second encapsulation layer 220 corresponding to the through hole.

[0106] Each second electrode 120 is extended along the surface of the first encapsulation layer 210 and the through hole to the surface of the second interconnection path 123 by additive manufacturing. Specifically, an extended circuit is prepared on the surface of the first encapsulation layer 210 and inside the through hole by additive manufacturing, so that each second electrode 120 is extended to the surface of the second interconnection path 123.

[0107] As an example, a second conductive column 122 is prepared inside the through hole by additive manufacturing, so that the second conductive column 122 extends from the bottom of the through hole to the top of the through hole; then a conductive path 121 is prepared on the surface of the first encapsulation layer 210 by additive manufacturing, so that one end of the conductive path 121 is connected to the second electrode 120, and the other end is connected to the top of the second conductive column 122.

[0108] As another example, a conductive path 121 is prepared on the surface of the first encapsulation layer 210 by additive manufacturing, so that one end of the conductive path 121 is connected to the second electrode 120, and the other end extends to the top side of the through hole; then a second conductive column 122 is prepared inside the through hole by additive manufacturing, so that the second conductive column 122 extends from the bottom of the through hole to the top of the through hole, and is connected to the end of the conductive path 121 away from the second electrode 120.

[0109] In an embodiment of the present application, the specific process of "forming a longitudinally extending through hole by etching inside the first encapsulation layer 210 and the second encapsulation layer 220" can be further explained in combination with the following description.

[0110] A photosensitive material is coated on the surface of the first encapsulation layer 210, and exposure and development are performed to expose the target part of the upper encapsulation layer composed of the first encapsulation layer 210 and the second encapsulation layer 220; wherein the target part is a longitudinally extending columnar structure corresponding to each second electrode 120, and the target part is connected with the second interconnection passage 123 respectively. Specifically, the photosensitive material is coated on the surface of the first encapsulation layer 210, and exposure and development are performed to solidify the photosensitive material that has undergone photopolymerization reaction to form a sixth photosensitive material layer, and the photosensitive material that has not undergone photopolymerization reaction (i.e. the photosensitive material on the surface of the target part) is washed away.

[0111] The target part is etched and removed. Specifically, the target part is etched and removed by rapid chemical etching. Different etching solutions can be selected according to the material of the upper encapsulation layer, the product is immersed in the etching solution, the etching condition is observed, and the product is taken out immediately after the target part is etched away, and then washed with clean water to remove the etching solution.

[0112] The photosensitive material is removed. Specifically, the sixth photosensitive material layer is removed by a stripper.

[0113] In an embodiment of the present application, the specific process of "extending each second electrode 120 along the surface of the first encapsulation layer 210 and the through hole to the surface of the second interconnection passage 123 by additive manufacturing" can be further explained in combination with the following description.

[0114] A second conductive column 122 is prepared inside the through hole by additive manufacturing. Specifically, the second conductive column 122 is prepared inside the through hole by additive manufacturing to extend longitudinally, so that the second conductive column 122 extends from the bottom of the through hole to the top of the through hole.

[0115] A conductive passage 121 is prepared on the surface of the first encapsulation layer 210 by additive manufacturing; wherein the conductive passage 121 is connected with the second electrode 120 and the second conductive column 122 respectively. Specifically, the conductive passage 121 is prepared on the surface of the first encapsulation layer 210 by additive manufacturing to extend horizontally, so that the conductive passage 121 extends from the second electrode 120 to the end of the second conductive column 122 close to the second electrode 120.

[0116] In an embodiment of the present application, the specific process of "preparing the second conductive column 122 inside the through hole by additive manufacturing" can be further illustrated in combination with the following description.

[0117] A photosensitive material is coated on the surface of the first encapsulation layer 210, and exposure and development are performed to expose a fifth target region on the surface of the first encapsulation layer 210; wherein the fifth target region corresponds to the position of the through hole. Specifically, the photosensitive material is coated on the surface of the first encapsulation layer 210, and exposure and development are performed, so that the photosensitive material that has undergone photopolymerization reaction is solidified to form a seventh photosensitive material layer, and the photosensitive material (i.e. the photosensitive material on the surface of the fifth target region) that has not undergone photopolymerization reaction is washed away.

[0118] The second conductive column 122 is prepared inside the through hole by additive manufacturing. Specifically, the second conductive column 122 extending longitudinally is prepared inside the through hole by additive manufacturing.

[0119] The photosensitive material is removed. Specifically, the seventh photosensitive material layer is removed by a stripping agent.

[0120] In an embodiment of the present application, the specific process of "preparing the conductive path 121 on the surface of the first encapsulation layer 210 by additive manufacturing" can be further illustrated in combination with the following description.

[0121] A photosensitive material is coated on the surface of the first encapsulation layer 210, and exposure and development are performed to expose a sixth target region on the surface of the first encapsulation layer 210; wherein the sixth target region respectively corresponds to the second electrode 120 and the conductive column. Specifically, the photosensitive material is coated on the surface of the first encapsulation layer 210, and exposure and development are performed, so that the photosensitive material that has undergone photopolymerization reaction is solidified to form an eighth photosensitive material layer, and the photosensitive material (i.e. the photosensitive material on the surface of the sixth target region) that has not undergone photopolymerization reaction is washed away.

[0122] The conductive path 121 is prepared on the surface of the sixth target region by additive manufacturing. Specifically, the conductive path 121 extending horizontally is prepared on the surface of the sixth target region by additive manufacturing.

[0123] The photosensitive material is removed. Specifically, the eighth photosensitive material layer is removed by a stripping agent.

[0124] In an embodiment of the present application, the specific process of "encapsulating the chip 100" can be further illustrated in combination with the following description.

[0125] A fourth encapsulation adhesive layer 240 is laid on the top of the chip 100. Specifically, the fourth encapsulation adhesive layer 240 is poured on the top of the chip 100, and the top of the fourth encapsulation adhesive layer 240 extends to a position higher than the top of the second electrode 120.

[0126] In an embodiment of the present application, the specific process of "laying a fourth encapsulation adhesive layer 240 on the top of the chip 100" can be further described as follows.

[0127] The encapsulation adhesive is poured to a height higher than the top of the chip 100. Specifically, the encapsulation adhesive is poured on the top of the chip 100, and the top of the encapsulation adhesive extends to a position higher than the top of the second electrode 120.

[0128] The encapsulation adhesive is subjected to drying treatment to form the fourth encapsulation adhesive layer 240. Specifically, the encapsulation adhesive is subjected to drying treatment at 60-160°C to form the fourth encapsulation adhesive layer 240.

[0129] In a specific implementation of the present application, the interconnection encapsulation method comprises:

[0130] Each chip 100 is placed on the surface of a first carrier board 300; wherein each first electrode 110 faces upward;

[0131] A first encapsulation adhesive layer 210 is laid on the periphery of each chip 100;

[0132] The first interconnection passage 111 is prepared on the surface of each chip 100 and the first encapsulation adhesive layer 210 by additive manufacturing; wherein the first interconnection passage 111 is connected with each first electrode 110, respectively;

[0133] A first conductive column 112 is prepared on the surface of the first interconnection passage 111 by additive manufacturing, and a second encapsulation adhesive layer 220 is laid on the periphery of the first conductive column 112;

[0134] The second interconnection passage 123 is prepared on the surface of the second encapsulation adhesive layer 220 by additive manufacturing;

[0135] A first extension column 113 is prepared on the surface of the first conductive column 112 and a second extension column 124 is prepared on the surface of the second interconnection passage 123 by additive manufacturing, respectively, and a third encapsulation adhesive layer 230 is laid on the periphery of the first extension column 113 and the second extension column 124;

[0136] A first extended via 114 and a second extended via 125 are respectively prepared on the surface of the first extended column 113, the second extended column 124 and the third encapsulation layer 230 by additive manufacturing; wherein the first extended via 114 is connected with the first extended column 113; the second extended via 125 is connected with the second extended column 124;

[0137] Each chip 100 is placed on the surface of the second carrier board 400; wherein each second electrode 120 faces upward;

[0138] A through hole extending longitudinally is etched in the interior of the first encapsulation layer 210 and the second encapsulation layer 220; wherein the through hole corresponds to each second electrode 120 one by one; the through hole is respectively connected with the second interconnection via 123;

[0139] A second conductive column 122 extending longitudinally is prepared along the interior of the through hole by additive manufacturing, so that the second conductive column 122 extends from the bottom of the through hole to the top of the through hole;

[0140] A conductive via 121 extending horizontally is prepared along the surface of the first encapsulation layer 210 by additive manufacturing, so that one end of the conductive via 121 is connected with the second electrode 120, and the other end is connected with the top of the second conductive column 122;

[0141] A fourth encapsulation layer 240 is laid on the top of the chip 100, to obtain a chip package.

[0142] In another specific implementation of the present application, the interconnection packaging method comprises:

[0143] Each chip 100 is placed on the surface of the first carrier board 300; wherein each first electrode 110 faces upward;

[0144] A first encapsulation layer 210 is laid on the periphery of each chip 100;

[0145] The first interconnection via 111 is prepared on the surface of each chip 100 and the first encapsulation layer 210 by additive manufacturing; wherein the first interconnection via 111 is respectively connected with each first electrode 110;

[0146] A first conductive column 112 is prepared on the surface of the first interconnection via 111 by additive manufacturing, and a second encapsulation layer 220 is laid on the periphery of the first conductive column 112;

[0147] The second interconnection via 123 is prepared on the surface of the second encapsulation layer 220 by additive manufacturing;

[0148] A first extension column 113 is prepared on the surface of the first conductive column 112 and a second extension column 124 is prepared on the surface of the second interconnection passage 123 by additive manufacturing, and a third encapsulation adhesive layer 230 is laid on the circumferential side of the first extension column 113 and the second extension column 124;

[0149] A first extension passage 114 and a second extension passage 125 are respectively prepared on the surface of the first extension column 113, the second extension column 124 and the third encapsulation adhesive layer 230 by additive manufacturing; the first extension passage 114 is connected with the first extension column 113; the second extension passage 125 is connected with the second extension column 124;

[0150] Each chip 100 is placed on the surface of the second carrier board 400; each second electrode 120 faces upward;

[0151] A through hole extending longitudinally is etched in the first encapsulation adhesive layer 210 and the second encapsulation adhesive layer 220; the through hole corresponds to each second electrode 120 one by one; the through hole is respectively connected with the second interconnection passage 123;

[0152] A horizontally extending conductive passage 121 is prepared on the surface of the first encapsulation adhesive layer 210 by additive manufacturing, so that one end of the conductive passage 121 is connected with the second electrode 120 and the other end extends to the top side of the through hole;

[0153] A second conductive column 122 extending longitudinally is prepared in the through hole by additive manufacturing, so that the second conductive column 122 extends from the bottom of the through hole to the top of the through hole and is connected with the end of the conductive passage 121 away from the second electrode 120;

[0154] A fourth encapsulation adhesive layer 240 is laid on the top of the chip 100 to obtain a chip package.

[0155] Referring to Figure 3 , a chip package prepared by the interconnection packaging method according to any one of the above embodiments is shown, which comprises at least two chips 100 and an encapsulation adhesive layer wrapping the outside of the chip 100; the first electrodes 110 of each chip 100 are connected with each other and extend to the surface of the encapsulation adhesive layer; the second electrodes 120 of each chip 100 are connected with each other and extend to the surface of the encapsulation adhesive layer. The product reliability of the chip package is high, the packaging efficiency is high, and no packaging substrate is needed, so the packaging cost is low.

[0156] Although the preferred embodiments of the application have been described, those skilled in the art will be able to make additional modifications and variations without departing from the scope of the application. Accordingly, the appended claims are intended to encompass all such modifications and variations as falling within the scope of the application.

[0157] Finally, it is to be understood that the phraseology or terminology employed herein, such as "first" and "second", etc., are for descriptive purposes only and should not be construed to connote or otherwise imply any kind of ordering, precedence or relationships between or among the elements or operations so described. Moreover, the terms "comprising", "including", or any other variations thereof, are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0158] The above provides a chip interconnection packaging method and a chip package provided by the application, and the principles and implementation manners of the application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the application and its core idea. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the application. In conclusion, the content of the specification should not be understood as a limitation of the application.

Claims

1. A chip interconnection packaging method for packaging at least two chips, said chips including a first electrode and a second electrode disposed opposite to each other; characterized in that, The application relates to a chip packaging method and a chip packaging device. The first electrodes are connected to each other by additive manufacturing to form first interconnection channels, and the first interconnection channels are extended upward to a first preset plane; Specifically, each chip is placed on the surface of a first carrier plate, wherein each first electrode faces upward; a first encapsulation glue layer is laid on the periphery of each chip; the first interconnection channels are prepared on the surface of each chip and the first encapsulation glue layer by additive manufacturing; the first interconnection channels are connected to each first electrode respectively; first conductive columns are prepared on the surface of the first interconnection channels by additive manufacturing, and a second encapsulation glue layer is laid on the periphery of the first conductive columns; Second interconnection channels are prepared on the first preset plane by additive manufacturing, and the first interconnection channels and the second interconnection channels are extended upward to a second preset plane respectively; Each second electrode is connected to the second interconnection channels by additive manufacturing, and the chips are encapsulated by glue to obtain a chip packaging device.

2. The method of claim 1, wherein, The step of preparing the first interconnection channels on the surface of each chip and the first encapsulation glue layer by additive manufacturing comprises the following steps: A photosensitive material is coated on the surface of each chip and the first encapsulation glue layer, and exposure and development are performed to expose a first target area on the surface of each chip and the first encapsulation glue layer; the first target area is connected to the first electrode respectively; The first interconnection channels are prepared on the surface of the first target area by additive manufacturing; and the photosensitive material is removed.

3. The method of claim 1, wherein, The step of preparing the second interconnection channels on the first preset plane by additive manufacturing, and extending the first interconnection channels and the second interconnection channels upward to the second preset plane respectively comprises the following steps: The second interconnection channels are prepared on the surface of the second encapsulation glue layer by additive manufacturing; First extension columns are prepared on the surface of the first conductive columns and second extension columns are prepared on the surface of the second interconnection channels by additive manufacturing respectively, and a third encapsulation glue layer is laid on the periphery of the first extension columns and the second extension columns.

4. The method of claim 3, wherein, The step of preparing the second interconnection channels on the surface of the second encapsulation glue layer by additive manufacturing comprises the following steps: A photosensitive material is coated on the surface of the second encapsulation glue layer, and exposure and development are performed to expose a second target area on the surface of the second encapsulation glue layer; The second interconnection channels are prepared on the surface of the second target area by additive manufacturing; The photosensitive material is removed.

5. The method of claim 3, wherein the step of forming the interconnects comprises: The step of preparing the second interconnection channels on the first preset plane by additive manufacturing, and extending the first interconnection channels and the second interconnection channels upward to the second preset plane respectively further comprises the following steps: First extension channels and second extension channels are prepared on the surface of the first extension columns, the second extension columns and the third encapsulation glue layer by additive manufacturing respectively; the first extension channels are connected to the first extension columns; and the second extension channels are connected to the second extension columns.

6. The method of claim 5, wherein, The step of preparing the first and second extended vias on the surfaces of the first, second and third extended columns by additive manufacturing, comprises: coating a photosensitive material on the surfaces of the first, second and third extended columns, and performing exposure and development to expose third and fourth target areas on the surfaces of the first, second and third extended columns; wherein the third target area is connected with the first extended column, and the fourth target area is connected with the second extended column; preparing the first and second extended vias on the surfaces of the third and fourth target areas by additive manufacturing, respectively; removing the photosensitive material.

7. The method of claim 1, wherein, The step of connecting each of the second electrodes with the second interconnection vias by additive manufacturing, comprises: placing each of the chips on the surface of a second carrier board; wherein each of the second electrodes faces upward; etching a through hole extending longitudinally in the interior of the first and second encapsulation layers; wherein the through hole corresponds to each of the second electrodes one by one; and the through hole is connected with the second interconnection via, respectively; extending each of the second electrodes along the surface of the first encapsulation layer and the through hole to the surface of the second interconnection via by additive manufacturing.

8. The interconnection packaging method of claim 1, wherein, The additive manufacturing comprises one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating and electroless plating.

9. A chip package prepared by the interconnection packaging method according to any one of claims 1 to 8, characterized by, comprises: at least two chips and an encapsulation layer wrapped outside the chips; the first electrodes of each of the chips are connected with each other and extend to the surface of the encapsulation layer; and the second electrodes of each of the chips are connected with each other and extend to the surface of the encapsulation layer.

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