Chip cutting method, device, apparatus, and storage medium

Abstract

The application discloses a chip cutting method, device, equipment and storage medium. The target cutting path of a to-be-cut unit in a three-dimensional stacked chip is determined. If the target cutting path does not meet a preset cutting condition, a first cutting position of the target cutting path is determined based on the reference width and a reference mark of the to-be-cut unit. The target cutting path is cut according to the determined first cutting position. Thus, the chip cutting efficiency is improved without replacing the cutting knife.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a chip dicing method, apparatus, device, and storage medium. Background Technology

[0002] Three-Dimensional Integrated Circuits (3DIC) hybrid bonding technology is a hybrid bonding technique that connects multiple chips together through direct Cu-Cu bonding. It is a wafer-level electrical interconnection technology. After bonding to form a three-dimensional stacked chip, the three-dimensional stacked chip needs to be further diced to obtain the final chip.

[0003] Wafer dicing is a crucial step in the 3D stacked chip packaging process. Traditional wafers consist of repeating cells with identical dicing widths for each cell. Traditional dicing methods can only cut along the center of each dicing channel; if dicing widths differ, frequent blade changes are necessary, leading to high costs. Summary of the Invention

[0004] This application provides a chip dicing method, apparatus, device, and storage medium that can cut dicing channels of different widths in a three-dimensional stacked chip without changing the dicing blade, which helps to reduce costs and improve chip dicing efficiency.

[0005] In a first aspect, embodiments of this application provide a chip dicing method for dicing three-dimensional stacked chips, the method comprising:

[0006] Determine the target cutting path for the unit to be cut in a 3D stacked chip;

[0007] In response to the target cutting path not meeting the preset cutting conditions, the first cutting position of the target cutting path is determined based on the preset reference width and the reference mark of the unit to be cut, wherein the preset cutting conditions are determined according to the cutting path width corresponding to the cutting blade;

[0008] The target cutting path is cut according to the first cutting position.

[0009] Furthermore, after cutting the target cutting path according to the first cutting position, the method further includes:

[0010] In response to the existence of another unit in the three-dimensional stacked chip that shares the target cutting path with the unit to be cut, a second cutting position is determined in the cut target cutting path based on the reference width and the reference mark of the other unit to be cut, and the target cutting path is cut again according to the second cutting position.

[0011] Furthermore, the distance between the first cutting position and the reference mark is equal to the reference width, wherein the reference mark is a mark used to define the target cutting path.

[0012] Furthermore, the cutting method also includes:

[0013] In response to the target cutting path satisfying the preset cutting conditions, the target cutting path is cut according to its center position.

[0014] Furthermore, the cutting method further includes: determining that the target cutting channel does not meet the preset cutting conditions in response to the width of the target cutting channel being greater than the reference width; or determining that the target cutting channel does not meet the preset cutting conditions in response to the position of the target cutting channel in the three-dimensional stacked chip being pre-marked.

[0015] Furthermore, the three-dimensional stacked chip includes a first wafer and a second wafer stacked together. The first wafer includes multiple memory cells, and the second wafer includes multiple logic cells. The area of ​​each logic cell corresponds to the area of ​​at least one memory cell. Each unit to be diced includes a logic cell and a corresponding memory cell.

[0016] Furthermore, the three-dimensional stacked chip includes multiple frame regions, each frame region having multiple units to be cut, and the cutting width of the inner layer unit to be cut in the frame region is inconsistent with the cutting width between adjacent frame regions.

[0017] Secondly, embodiments of this application provide a chip dicing apparatus for dicing three-dimensional stacked chips, the apparatus comprising:

[0018] The kerf determination module is used to determine the target kerf for the unit to be cut in the 3D stacked chip;

[0019] The position determination module is used to determine the first cutting position of the target cutting path based on the preset reference width and the reference mark of the unit to be cut when the target cutting path does not meet the preset cutting conditions. The preset cutting conditions are determined according to the cutting path width corresponding to the cutting blade.

[0020] The cutting module is used to cut the target cutting path according to the first cutting position.

[0021] Thirdly, embodiments of this application provide a chip dicing apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the chip dicing method provided in the first aspect.

[0022] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the chip dicing method provided in the first aspect.

[0023] The chip dicing method, apparatus, device, and storage medium provided in this application determine the target dicing ridge of the cell to be diced in a three-dimensional stacked chip. In response to the target dicing ridge not meeting preset dicing conditions, a first dicing position of the target dicing ridge is determined based on a preset reference width and a reference mark of the cell to be diced. The target dicing ridge is then diced according to the determined first dicing position. In this way, for dicing ridges in a three-dimensional stacked chip that are relatively wide and cannot be directly diced because they do not meet the preset dicing conditions, the dicing position can be re-determined, ensuring the consistency of the diced chips. Dicing dicing ridges of different widths in a three-dimensional stacked chip can be achieved without changing the dicing blade, which is beneficial for improving chip dicing efficiency.

[0024] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0025] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0026] Figure 1 A schematic diagram of an exemplary three-dimensional stacked chip structure is shown;

[0027] Figure 2 This specification illustrates an exemplary framework design diagram provided in an embodiment.

[0028] Figure 3 A flowchart of a chip cutting method provided in an embodiment of this specification is shown;

[0029] Figure 4 An exemplary cutting diagram provided in an embodiment of this specification is shown;

[0030] Figure 5 A structural block diagram of a chip dicing apparatus provided in an embodiment of this specification is shown;

[0031] Figure 6 A schematic diagram of the structure of a chip cutting device provided in an embodiment of this specification is shown. Detailed Implementation

[0032] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0033] Figure 1 A schematic diagram of an exemplary three-dimensional stacked chip structure is shown. Figure 1 As shown, the three-dimensional stacked chip may include a first wafer 110 and a second wafer 120 stacked together. The first wafer 110 includes multiple memory cells, and the second wafer 120 includes multiple logic cells. The first wafer 110 and the second wafer 120 are bonded together using 3DIC technology to form the three-dimensional stacked chip. Further, the three-dimensional stacked chip is divided to obtain the desired chip. The specific circuit structure of the logic cells can be designed according to the functional requirements of the actual application; for example, it can be used for AI (Artificial Intelligence) and applications requiring high-speed caching, and there are no limitations here.

[0034] In 3D IC chip manufacturing, because memory cells are small-capacity cells, when designing the frame for the first wafer 110, the dicing width of the repeating cells within each frame region differs from the dicing width of the entire frame region due to factors such as test keys. The dicing width of the entire frame region is greater than that of the repeating cells within the frame region. Furthermore, logic cells can be designed according to different memory capacity requirements. Therefore, the final chip dicing will vary due to the inconsistent sizes of the logic cells. It should be noted that the frame region is the single-exposure area during semiconductor processing of the wafer. Since the wafer area is larger than the exposure area, multiple frame regions are typically designed on the wafer surface during frame design.

[0035] To better understand the above issues, a specific example is provided below.

[0036] In the design process of the first wafer 110, it is assumed that the capacity of the repeating cell, i.e., the memory cell, is 1G, and the dicing size of the memory cell is designed as X / Y, such as... Figure 2 As shown. It should be noted that, Figure 2 The unfilled small squares arranged in the middle array represent memory cells, and for illustration purposes, only some memory cells are shown with overlaid logic cells, indicated by the area filled with diagonal lines. The logic cells overlaid on other memory cells are not shown.

[0037] When designing the frame for the first wafer 110, a frame area size of 24G is used, meaning each frame area contains 24 memory cells, such as 4 memory cells horizontally and 6 memory cells vertically. Assume there are four frame areas on the first wafer 110, marked with dashed rectangles. Because the test key for the first wafer 110 needs to be placed there, the dicing width of the outermost memory cells near the adjacent frame area will be greater than that of the inner memory cells. For example... Figure 2 As shown, the width of the cutting channel of the outermost storage cell of the frame region on the side closest to the adjacent frame region is denoted as X1 / Y1, where X1 is greater than X and Y1 is greater than Y.

[0038] The number of storage units matched with a logical unit is determined based on the storage capacity requirement of the logical unit. Taking a logical unit with a storage capacity requirement of 4G as an example, there are 2 storage units horizontally and 2 vertically. This results in four types of outermost slicing channels: X / X1 / Y / Y1, which means that the slicing channel widths may be inconsistent.

[0039] Accordingly, in the design process of the second wafer 120, the dicing design of the internal repeating units, i.e. logic units, is also carried out according to the X / Y width. When designing the frame, the dicing width of the logic units distributed on the outermost layer of the frame area on the side closest to the adjacent frame area is kept consistent with that of the first wafer 110, which is also X1 / Y1.

[0040] In other words, for this type of three-dimensional stacked chip, the width of the dicing kerf for each cell is not uniform. However, since the dicing blade has a specific applicable dicing width, if traditional wafer dicing methods are used, the dicing blade needs to be changed frequently, which is costly and complex, and does not improve chip dicing efficiency.

[0041] Therefore, this specification provides a chip dicing method. First, the target dicing ridge of the cell to be diced in the three-dimensional stacked chip is determined. If the target dicing ridge does not meet preset dicing conditions, a first dicing position of the target dicing ridge is determined based on a preset reference width and a reference mark of the cell to be diced. Then, the target dicing ridge is diced according to the determined first dicing position. In this way, for dicing ridges with relatively large widths or that do not meet the preset dicing conditions, the dicing position can be re-determined, effectively ensuring the consistency of the diced chips. It can diced ridges of different widths in the three-dimensional stacked chip without changing the dicing blade, which is beneficial to improving chip dicing efficiency. Furthermore, it is applicable to dicing methods for all chip sizes.

[0042] It is understood that the chip cutting method provided in the embodiments of this specification can be applied in the 3DIC chip packaging process to cut the required chip from a three-dimensional stacked chip. The specific implementation schemes provided in the embodiments of this specification will be described in detail below.

[0043] Figure 3 A flowchart of the chip cutting method provided in the embodiments of this specification is shown, such as... Figure 3 As shown, the method may include the following steps S101 to S103.

[0044] Step S101: Determine the target cutting path of the unit to be cut in the three-dimensional stacked chip.

[0045] In this embodiment, the three-dimensional stacked chip is a stacked structure formed by connecting multiple wafers together using 3DIC technology. Typically, chips are mass-produced, and the stacked wafers contain multiple repeating units. Correspondingly, the three-dimensional stacked chip contains multiple units to be diced, each with pre-drilled dicing channels around it. Dividing along these channels allows for the individual cutting of these units to obtain the desired wafer.

[0046] by Figure 1 Taking the illustrated three-dimensional stacked chip as an example, the first wafer 110 includes multiple memory cells, and the second wafer 120 includes multiple logic cells, with the area of ​​each logic cell corresponding to the area of ​​at least one memory cell. In this case, each unit to be cut includes one logic cell and a corresponding memory cell. The number of memory cells corresponding to a logic cell in the three-dimensional stacked chip is determined based on the actual storage capacity requirement of that logic cell. For example, if a logic cell corresponds to four memory cells, then the corresponding unit to be cut includes that logic cell and the four memory cells it covers.

[0047] Understandably, during the processing of the first wafer 110 and the second wafer 120, since the area of ​​the exposure region is usually smaller than the wafer area, multiple frame regions are designed, thereby forming multiple arrayed repeating units in each frame region. In other words, the final three-dimensional stacked chip also includes multiple frame regions, each with multiple units to be diced, and the dicing width of the inner-layer units within a frame region is inconsistent with the dicing width between adjacent frame regions. Here, the inner-layer units to be diced are those distributed in the innermost layer of the frame region, not those involved in the dicing of the entire frame region.

[0048] Therefore, for the inner layer units to be cut, the widths of the two cutting tracks in the horizontal direction are the same, and the widths of the two cutting tracks in the vertical direction are also the same. However, for the units to be cut that are distributed in the outermost layer of the frame area and share cutting tracks with adjacent frame areas, two different widths of cutting tracks will be involved in both the horizontal and vertical directions.

[0049] For example, suppose Figure 2 In the diagram, the x-axis represents the horizontal direction, and the y-axis represents the vertical direction. For example... Figure 2 The unit die0 to be cut in the first frame region 201 shown has a cutting path width of X1 between it and the unit die1 to be cut in the second frame region 202 in the x-axis direction, and a cutting path width of X between it and the inner unit to be cut in this frame region; in the y-axis direction, it has a cutting path width of Y1 between it and the unit die2 to be cut in the third frame region 203, and a cutting path width of Y between it and the inner unit to be cut in this frame region. Where X1 is greater than X, and Y1 is greater than Y.

[0050] In step S101, the target cutting path is the cutting path that the unit to be cut currently needs to cut. It is understood that each type of cutting blade corresponds to a suitable cutting path width. The width of the target cutting path determines whether it can be directly cut at the center position of the cutting path using the current cutting blade. Therefore, preset cutting conditions can be set in advance according to the cutting path width corresponding to the cutting blade. Cutting paths whose width matches the cutting path width corresponding to the cutting blade meet the preset cutting conditions; conversely, cutting paths whose width does not match the cutting path width corresponding to the cutting blade do not meet the preset cutting conditions.

[0051] For the units to be cut located on the outermost layer of the frame area, if the target cutting path is a shared cutting path along the x-axis with adjacent units to be cut in the middle layer of this frame area, then the width of the target cutting path is the first width, denoted as X above. If the target cutting path is a shared cutting path along the x-axis with outer units to be cut in an adjacent frame area, then the width of the target cutting path is the second width, denoted as X1 above. Similarly, if the target cutting path is a shared cutting path along the y-axis with adjacent units to be cut in the middle layer of this frame area, then the width of the target cutting path is the third width, denoted as Y above. If the target cutting path is a shared cutting path along the y-axis with outer units to be cut in an adjacent frame area, then the width of the target cutting path is the fourth width, denoted as Y1 above.

[0052] For the units to be cut distributed in the inner layers of the frame area, if the target cutting path is a cutting path in the x-axis direction, the target cutting path width is the first width; if the target cutting path is a cutting path in the y-axis direction, the target cutting path width is the third width.

[0053] In practice, when designing a 3D stacked chip, the width of the kerf path for the inner layer of the frame region can be set to match the cutting width of the dicing blade, meaning the kerf path for the inner layer of the unit to be cut meets the preset cutting conditions. In this case, the kerf paths with the second and fourth widths mentioned above, because their widths are inconsistent with the inner layer kerf path widths, do not match the cutting width of the dicing blade and therefore do not meet the preset cutting conditions.

[0054] Based on the above analysis, there are at least two ways to determine whether the target cutting path meets the preset cutting conditions:

[0055] The first method is to determine whether the target cutting path meets the preset cutting conditions based on the width of the target cutting path and the preset reference width.

[0056] For example, the width of the target etchable can be determined based on the current position of the cell to be diced in the 3D stacked chip and the positional relationship between the target etchable and the cell to be diced. Alternatively, the width of the target etchable can be determined by detecting the distance between the reference mark of the cell to be diced and the reference marks of adjacent cells to be diced sharing the same target etchable, perpendicular to the dicing direction. It is understood that, to facilitate dicing alignment, reference marks are set for each cell to be diced in the dicing surface during the formation of the 3D stacked chip. These reference marks are used to define the etchable, serving as the boundary between the chip area and the etchable area; for example, they can be represented as reference lines or reference points.

[0057] Furthermore, the cutting width of the inner layer unit to be cut within the same frame region can be set as the reference width. In this case, the first width X is the reference width in the x-axis direction, and the third width Y is the reference width in the y-axis direction. The first width and the third width can be equal or unequal, depending on the actual design requirements.

[0058] If the width of the target cutting path is greater than the reference width, it is determined that the target cutting path does not meet the preset cutting conditions. In this case, step S102 is executed to complete the cutting of the target cutting path. If the width of the target cutting path is equal to the reference width, it is determined that the target cutting path meets the preset cutting conditions. In this case, step S103 can be executed to complete the cutting of the target cutting path. It should be noted that the terms "greater than" and "equal to" can be interpreted broadly. For example, a deviation threshold can be set according to the actual acceptable error range. If the absolute value of the difference between the width of the target cutting path and the reference width is less than the deviation threshold, it can be determined that the width of the target cutting path is equal to the reference width; if the difference between the width of the target cutting path and the reference width is greater than the deviation threshold, it can be determined that the width of the target cutting path is greater than the reference width.

[0059] The second method can also determine whether the target dicing path meets the preset cutting conditions based on its position in the 3D stacked chip. For example, the positions of dicing paths in the 3D stacked chip whose width does not match the cutting width of the dicing blade (i.e., dicing paths whose width is greater than the reference width) can be marked in advance. After determining the position of the target dicing path, if the marked position is detected, it is determined that the target dicing path does not meet the preset cutting conditions, and the following step S102 is executed to complete the cutting of the target dicing path; if it is not marked, it is determined that the target dicing path meets the preset cutting conditions, and the following step S103 is executed to complete the cutting of the target dicing path.

[0060] In step S102, in response to the target cutting path not meeting the preset cutting conditions, the first cutting position of the target cutting path is determined based on the reference width and the reference mark of the unit to be cut, and the target cutting path is cut according to the first cutting position.

[0061] If a target dicing line does not meet the preset cutting conditions, cutting it according to its center position will result in an excessively large blank width, making it impossible to guarantee the consistency of the cut chips, and may even lead to defective chips that cannot be installed or used. Therefore, redetermining the cutting position of the target dicing line based on the reference width and the reference mark of the unit to be cut helps to reduce the difference in blank width between it and other cutting positions, thus ensuring the consistency of the cut chips.

[0062] In one optional implementation, the distance between the first cutting position and the corresponding reference mark of the unit to be cut can be equal to the reference width. Of course, in other embodiments of this specification, besides the above-described implementation, the relationship between the first cutting position, the reference width, and the reference mark of the unit to be cut can be configured according to actual needs, and is not limited here. For example, the distance between the first cutting position and the corresponding reference mark of the unit to be cut can be equal to half the reference width, or equal to 1.2 times the reference width.

[0063] After determining the first cutting position, the cutting blade can be controlled to cut the target cutting path according to the first cutting position to obtain the required chip.

[0064] Furthermore, in response to the existence of another unit sharing the target cutting path with the unit to be cut, when cutting the other unit, a second cutting position needs to be determined in the target cutting path after cutting, based on the reference width and the reference mark of the other unit, and the target cutting path is cut again according to the second cutting position. The method for determining the second cutting position can refer to the method for determining the first cutting position, and will not be repeated here.

[0065] For dicing paths that do not meet the preset cutting conditions and are shared by two adjacent units to be cut, the two units are cut on that dicing path through the aforementioned two cuts. This eliminates the need to replace the dicing blade, thus improving the consistency of the blank width caused by inconsistent dicing path widths and effectively ensuring the consistency of the cut chips. Compared to replacing the dicing blade, this method helps reduce costs and improve chip cutting efficiency.

[0066] The following is based on Figure 2 In the example shown, the cutting of die0 in the first frame region 201, die1 in the second frame region 202, die2 in the third frame region 203, and die3 in the fourth frame region 204 are used as examples for illustration.

[0067] like Figure 2 As shown, the cutting widths of die0, die1, die2, die3, and die4 are X / X1 / Y / Y1 respectively; the cutting widths of die1, die2, die3, and die4 are X1 / X / Y / Y1 respectively; and the cutting widths of die3, die4, die5, die6, die7, die8, die9, die1, die1, die9 ...9, die1, die9, die9, die9, die1, die9

[0068] like Figure 4As shown, for the cutting path S1 between the units to be cut (die0 and die1), assuming the reference mark on one side of cutting path S1 for die0 is L1, and the reference mark on the other side of cutting path S1 for die1 is L2, and the reference width in the x-axis direction is X, during the cutting process of die0, a first cut is performed at the position C1, which is X distance from L1 in the x-axis direction. Then, during the cutting process of die1, a second cut is performed in cutting path S1 after the first cut, at the position C2, which is X distance from L2 in the x-axis direction.

[0069] For the cutting path S2 between the units to be cut (die0 and die2), assuming the reference mark on one side of cutting path S2 for die0 is L3, and the reference mark on the other side of cutting path S2 for die2 is L4, with a reference width of Y in the y-axis direction, during the cutting process of die0, the first cutting position C3 is taken as the first cutting position in the y-axis direction, and a second cutting is performed at the position C4 in the y-axis direction, after the first cutting in cutting path S2.

[0070] Similarly, the cutting paths between die1 and die3, as well as between die2 and die3, will be cut in a similar manner, which will not be described in detail here.

[0071] This allows for the effective removal of excess portions from the X1-width and Y1-width cutting channels during the cutting process, ensuring that the cut die0, die1, die2, and die3 are all the same size.

[0072] Step S103: In response to the target cutting path meeting the preset cutting conditions, the target cutting path is cut according to the center position of the target cutting path.

[0073] The target cutting path that meets the preset cutting conditions has a width that matches the cutting width of the cutting blade. There's no need to redetermine the cutting position; cutting can be performed according to the center position of the cutting path. For these cutting paths, only one cut is needed to complete the cutting of two units sharing the same cutting path. For example, in the example above, both the cutting path with a width of X in the x-axis direction and the cutting path with a width of Y in the y-axis direction require only one cut.

[0074] Secondly, based on the same inventive concept, embodiments of this specification also provide a chip dicing apparatus for dicing three-dimensional stacked chips. For example... Figure 5 As shown, the chip cutting apparatus 50 includes:

[0075] The cutting path determination module 501 is used to determine the target cutting path of the unit to be cut in the three-dimensional stacked chip.

[0076] The position determination module 502 is used to determine the first cutting position of the target cutting path based on the preset reference width and the reference mark of the unit to be cut when the target cutting path does not meet the preset cutting conditions. The preset cutting conditions are determined according to the cutting path width corresponding to the cutting blade.

[0077] The cutting module 503 is used to cut the target cutting path according to the first cutting position.

[0078] In an optional implementation, the position determination module 502 is further configured to: in response to the existence of another unit to be cut in the three-dimensional stacked chip that shares the target cutting path with the unit to be cut, determine a second cutting position in the cut target cutting path based on the reference width and the reference mark of the other unit to be cut. At this time, the cutting module 503 is further configured to: cut the target cutting path again according to the second cutting position.

[0079] In one alternative implementation, the distance between the first cutting position and the reference mark is equal to the reference width, wherein the reference mark is a mark used to define the target cutting path.

[0080] In an optional implementation, the cutting module 503 is further configured to: cut the target cutting path according to the center position of the target cutting path in response to the target cutting path satisfying the preset cutting conditions.

[0081] In an optional embodiment, the cutting device 50 further includes: a judgment module, configured to determine that the target cutting channel does not meet the preset cutting conditions in response to the width of the target cutting channel being greater than the reference width; or to determine that the target cutting channel does not meet the preset cutting conditions in response to the position of the target cutting channel in the three-dimensional stacked chip being pre-marked.

[0082] In one optional embodiment, the three-dimensional stacked chip includes a first wafer 110 and a second wafer 120 stacked together. The first wafer 110 includes a plurality of memory cells, and the second wafer 120 includes a plurality of logic cells, the area of ​​each logic cell corresponding to the area of ​​at least one memory cell; each cell to be diced includes a logic cell and a corresponding memory cell.

[0083] In one optional implementation, the three-dimensional stacked chip includes multiple frame regions, each frame region having multiple units to be cut, and the cutting width of the inner layer unit to be cut in the frame region is inconsistent with the cutting width between adjacent frame regions.

[0084] It should be noted that the above modules can be implemented by software code or by hardware such as integrated circuit chips.

[0085] It should also be noted that for the specific process of each module implementing its respective function, please refer to the specific content described in the method embodiment provided in the first aspect above, which will not be repeated here.

[0086] Thirdly, based on the same inventive concept, embodiments of this specification also provide a chip cutting device, such as... Figure 6 As shown, the chip dicing apparatus 60 may include: a memory 601, a processor 602, and a computer program stored in the memory 601 and executable on the processor 602. When the processor 602 executes the program, it implements the steps of the chip dicing method provided in any of the embodiments of the first aspect described above. For specific implementation details, please refer to the method embodiments provided in the first aspect described above.

[0087] Of course, in addition to the above structure, the chip cutting device 60 also includes other structures such as cutting blades. Other implementation details can be found in relevant technologies and are not limited here.

[0088] Fourthly, based on the same inventive concept, embodiments of this specification also provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the chip dicing method provided in any of the embodiments of the first aspect above. For specific implementation details, please refer to the method embodiments provided in the first aspect above.

[0089] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, devices, and computer program products according to embodiments of this specification. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 Devices that specify the functions in one or more boxes.

[0090] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including an instruction device, which is implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0091] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0092] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "a plurality of" means two or more, including two or more cases.

[0093] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0094] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A chip cutting method, characterized in that, The method is used for cutting three-dimensional stacked chips, and the method includes: Determine the target cutting path for the unit to be cut in the three-dimensional stacked chip; If the width of the target cutting path is greater than the reference width, it is determined that the target cutting path meets the preset cutting conditions. Then, based on the preset reference width and the reference mark of the unit to be cut, the first cutting position of the target cutting path is determined, wherein the preset cutting conditions are determined according to the cutting path width corresponding to the cutting blade. The target cutting path is cut according to the first cutting position.

2. The cutting method according to claim 1, characterized in that, After cutting the target cutting path according to the first cutting position, the method further includes: In response to the existence of another unit in the three-dimensional stacked chip that shares the target cutting path with the unit to be cut, a second cutting position is determined in the cut target cutting path based on the reference width and the reference mark of the other unit to be cut, and the target cutting path is cut again according to the second cutting position.

3. The cutting method according to claim 1, characterized in that, The distance between the first cutting position and the reference mark is equal to the reference width, wherein the reference mark is a mark used to define the target cutting path.

4. The cutting method according to claim 1, characterized in that, Also includes: If the width of the target cutting channel is equal to the reference width, it is determined that the target cutting channel meets the preset cutting conditions, and the target cutting channel is cut according to the center position of the target cutting channel.

5. The cutting method according to claim 1, characterized in that, Also includes: If the width of the target cutting path is greater than the reference width, it is determined that the target cutting path does not meet the preset cutting conditions. or In response to the fact that the position of the target cut path in the three-dimensional stacked chip is pre-marked, it is determined that the target cut path does not meet the preset cutting conditions.

6. The cutting method according to claim 1, characterized in that, The three-dimensional stacked chip includes a first wafer and a second wafer stacked together. The first wafer includes multiple memory cells, and the second wafer includes multiple logic cells. The area of ​​each logic cell corresponds to the area of ​​at least one memory cell. Each of the units to be cut includes a logic unit and a storage unit corresponding to that logic unit.

7. The cutting method according to claim 1, characterized in that, The three-dimensional stacked chip includes multiple frame regions, each frame region has multiple units to be cut, and the cutting width of the inner layer unit to be cut in the frame region is inconsistent with the cutting width between adjacent frame regions.

8. A chip cutting apparatus, characterized in that, The apparatus is used for cutting three-dimensional stacked chips, and the apparatus includes: The kerf determination module is used to determine the target kerf for the unit to be cut in the 3D stacked chip; The position determination module is used to determine the first cutting position of the target cutting track in response to the fact that the width of the target cutting track is greater than the reference width. If the target cutting track meets the preset cutting conditions, the module determines the first cutting position of the target cutting track based on the preset reference width and the reference mark of the unit to be cut. The preset cutting conditions are determined according to the cutting track width corresponding to the cutting blade. The cutting module is used to cut the target cutting path according to the first cutting position.

9. A chip cutting device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-7.

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