A method for ultrathin wafer dicing based on laser-induced thermal decomposition pre-cutting

Abstract

This invention discloses an ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting. Before grinding the ultrathin wafer, a first groove is cut into the substrate surface using laser-induced thermal decomposition pre-cutting technology to remove metal and dielectric layers from the wafer surface, effectively preventing delamination during subsequent dicing. Then, a second groove is formed by partial cutting, cutting to a position close to the center of the substrate. A protective film is then applied to the chip surface, and the back side of the wafer is then aligned and partially cut using IR light transmission, partially cutting the silicon wafer without severing it, maintaining the overall structural integrity of the wafer. After dicing, grinding and thinning are performed, followed by film expansion to separate the chip. This invention solves the problem of back bounce or back-side microcracks caused by excessive surface stress during the thinning and dicing of silicon wafers below 100μm, significantly improving the packaging yield.

Description

[Technical Field]

[0001] This invention belongs to the field of chip packaging technology, and in particular relates to an ultrathin wafer cutting method based on laser-induced thermal decomposition pre-cutting. [Background Technology]

[0002] As integrated circuit chip manufacturing technology nodes develop, chip manufacturing technology that follows Moore's Law is gradually approaching its physical limits. Consequently, the cost-effectiveness of chips is getting worse. On the other hand, the Internet of Things, big data, cloud computing and other technologies require higher and higher integration of electronic packaging components and shorter and shorter electrical connections between chips. Chips are constantly developing towards higher density and thinner and lighter designs.

[0003] For integrated circuits with processes below 28nm, ultra-thin wafer fabrication is becoming increasingly common and thinner. Chips can achieve multi-layer interconnection and multi-layer stacking. For processes below 28nm, in order to reduce inter-chip coupling and digital crosstalk, low-k (low-dielectric) materials need to be added in IC chip fabrication. However, low-k materials have low adhesion to silicon substrates, and when using traditional cutting methods, thin film detachment and breakage are prone to occur, further increasing the complexity and difficulty of wafer cutting. The problems caused by cutting are obviously more complicated.

[0004] Traditional processes involve first thinning the silicon-based material surface using grinding equipment, then using a diamond cutter to cut the wafer pattern along the dicing path, separating the chip from the wafer to form a single chip. However, as wafer thickness becomes increasingly thinner, for wafers thinner than 100µm, the warping stress after grinding is very high and stress deformation is prone to occur. Furthermore, due to the extreme thinness of the wafer, there is a significant risk of chipping during the subsequent film lamination process before cutting. Additionally, when using diamond cutters, under a fixed spindle speed and cutting speed, the metal debris generated in the dicing path generates considerable heat when the hard metal blade passes over the silicon-based composite material. This metal debris, encasing the diamond blade, can lead to cutting deviation and blade breakage if the feed rate is too high, resulting in reduced chip yield. Moreover, when cutting ultra-thin, low-dielectric-constant wafers, delamination between metal layers is likely to occur. Therefore, mechanical cutting methods are no longer suitable for silicon-based materials, glass, and third-generation semiconductor materials thinner than 100µm.

[0005] In the prior art, patent publication number CN115020339A discloses a wafer dicing method, which processes the wafer by first dicing and then thinning, specifically including:

[0006] 1) Set dicing channels on the front side of the wafer;

[0007] 2) The wafer is cut along the dicing path using a laser according to the "preset cutting thickness";

[0008] 3) Apply a fixing film to the front side of the wafer;

[0009] 4) Thin the back side of the wafer until the wafer thickness matches the "target thickness";

[0010] 5) Attach the dicing film to the thinned surface, peel off the fixing film on the front side of the wafer to obtain multiple chips, and complete the dicing.

[0011] This cutting method is a single-cutting approach, using a laser to cut to the target thickness in one go, and then thinning it through grinding. However, when the chip is very thin, after grinding to the target thickness, the wafer needs to be handled during the dicing and film bonding process. Both the handling process and the subsequent film bonding process have a significant risk of wafer cracking. After grinding, on the one hand, there is no connection between individual chips, and the wafer's integrity is maintained only by the protective film on top. Since the film is a flexible material, the overall flatness of the wafer after grinding is poor, and chips are prone to squeezing and rubbing, especially at corners where edge collapse can occur, leading to chip defects. On the other hand, for very thin chips, the chip with the target thickness after grinding is very thin, and its internal stress is large, making it impossible to perform subsequent film bonding or even film expansion operations.

[0012] Therefore, it is necessary to provide a new ultrathin wafer cutting method based on laser-induced thermal decomposition pre-cutting to solve the above problems. [Summary of the Invention]

[0013] The main objective of this invention is to provide an ultrathin wafer cutting method based on laser-induced thermal decomposition pre-cutting, which solves the problem of back bounce or back-side microcracks caused by excessive surface stress during the existing silicon wafer thinning and cutting process below 100μm, and significantly improves the packaging yield.

[0014] This invention achieves the above objective through the following technical solution: an ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting, wherein the wafer includes a substrate layer and a plurality of chips arrayed on the substrate layer, and the dicing method includes the following steps:

[0015] S1. The first adhesive film is pasted on the back of the wafer;

[0016] S2. Using laser-induced thermal decomposition technology, the front side of the wafer is pre-cut according to a set cutting path, and a first groove is formed on the substrate layer.

[0017] S3. Perform a first half-cutting process on the bottom of the first groove along the set cutting path, cutting to a first depth, and forming a second groove at the bottom of the first groove; the first depth is less than or equal to half the thickness of the substrate layer;

[0018] S4. A second adhesive film is pasted onto the front side of the wafer to cover the chip;

[0019] S5. Remove the first adhesive film;

[0020] S6. The back side of the wafer is aligned with the second groove and a second half-cut is performed along the set cutting path to a second depth. The sum of the first depth and the second depth is less than the total thickness of the substrate layer.

[0021] S7. Thinning treatment is performed on the back side of the wafer;

[0022] S8. A third adhesive film is pasted onto the thinned surface;

[0023] S9. Remove the second adhesive film;

[0024] S10. Perform a film expansion process on the wafer to achieve chip separation.

[0025] Compared with existing technologies, the beneficial effects of the ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting of the present invention are as follows: Before grinding the ultrathin wafer, a first groove is cut on the substrate surface using laser-induced thermal decomposition pre-cutting technology to remove metal and dielectric layers from the wafer surface, effectively preventing delamination during subsequent dicing; then, a second groove is formed by half-cutting, cutting to a position close to the middle of the substrate; then, a protective film is applied to the chip surface, and then half-cutting is performed on the back side of the wafer using IR light transmission alignment, half-cutting the silicon wafer without cutting through it, allowing communication between adjacent chips. The wafer is connected together via a connector on the substrate layer, maintaining the overall structural integrity of the wafer. After dicing, it is then ground and thinned, and the wafer still maintains a single structure, thus reducing the risk of wafer cracking during the overall wafer pick-up and film application process. After thinning, a blue film is then attached to the bottom of the substrate, and the subsequent film expansion process is incorporated into the dicing process. The film expansion process is used to break the aforementioned connector at the top, achieving chip separation. This dicing method solves the problem of back bounce or backside microcracks caused by excessive surface stress during the thinning and dicing of silicon wafers below 100μm, significantly improving the packaging yield. [Attached Image Description]

[0026] Figure 1 This is a schematic diagram of the structure of an embodiment of the present invention;

[0027] Figure 2 This is a flowchart illustrating the manufacturing process of an embodiment of the present invention;

[0028] Figure 3a-3k This is a schematic diagram illustrating the structural changes of the wafer package during the fabrication process in an embodiment of the present invention;

[0029] The numbers in the image represent:

[0030] 100-Wafer;

[0031] 1-Substrate; 2-Chip;

[0032] 10-First adhesive film; 20-First groove; 30-Second groove; 40-Second adhesive film; 50-Third groove; 60-Connecting section; 70-Third adhesive film; 80-Expanding machine.

Detailed Implementation Methods

[0033] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0034] The technical solutions provided in this application will be explained in detail below with reference to specific embodiments.

[0035] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the wafer 100 to be cut provided in this embodiment. The wafer 100 includes a substrate layer 1 and a plurality of chips 2 arrayed on the substrate layer 1. The wafer 100 has a front side and a back side arranged opposite to each other.

[0036] Please refer to Figure 2 This embodiment is a method for cutting ultrathin wafers based on laser-induced thermal decomposition pre-cutting, which includes the following steps:

[0037] S1. Attach the first adhesive film 10 to the back of wafer 100, such as... Figure 3a As shown.

[0038] S2. Laser-induced thermal decomposition is used to pre-cut the front side of wafer 100 according to a set cutting path, forming a first groove 20 on substrate layer 1; the cross-section of the first groove 20 is a trapezoidal structure wider at the top and narrower at the bottom; the depth of the first groove 20 is 5–25 μm. Figure 3b As shown.

[0039] Step S2 involves using a laser of a preset wavelength to thermally decompose the metal and dielectric layer (such as silicon nitride, silicon oxide, or silicon oxynitride stack) on the surface of the wafer, thereby removing the metal and dielectric layer. Therefore, the depth of the first groove 20 should extend to the bottom of the dielectric layer of the wafer 100.

[0040] S3. Perform a first half-cutting process on the bottom of the first groove 20 along the set cutting path, cutting to a first depth, and forming a second groove 30 at the bottom of the first groove 20; the first depth is the distance from the upper surface of the substrate layer 1 to the bottom of the second groove 30; the first depth is less than or equal to half the thickness of the substrate layer 1; the width of the second groove 30 is less than or equal to the width of the bottom of the first groove 20, such as... Figure 3c As shown.

[0041] In step S3, the first semi-cutting process can be performed using laser cutting or mechanical cutting. Since the first groove 20 already exists, it provides the conditions for using mechanical cutting in the first semi-cutting process. The diamond tool can extend into the first groove 20, reducing the risk of edge chipping, delamination, and other phenomena.

[0042] By forming the second groove 30, the wafer cutting stress can be released, thereby reducing the risk of wafer cracking during subsequent film application due to stress.

[0043] S4. Apply the second adhesive film 40 to the front side of wafer 100 to cover chip 2 and protect it from scratches. Figure 3d As shown.

[0044] S5. Remove the first adhesive film 10 from the back of the wafer, as shown. Figure 3e As shown.

[0045] S6. Align the second groove 30 with the back side of the wafer 100 and perform a second half-cutting process along the set cutting path to the second depth, and form a third groove 50 on the lower surface of the substrate layer 1. The sum of the first depth and the second depth is less than the total thickness of the substrate layer 1.

[0046] In step S5, the wafer is cut but not severed, so that the substrate layers 1 at the bottom of two adjacent chips 2 are connected together by a connecting segment 60, ensuring the integrity of the wafer 100.

[0047] The second semi-cutting process can be performed using laser cutting or mechanical cutting tools, such as... Figure 3f As shown. During the second half-cutting process, the back side of the wafer can be aligned with transmitted light so that the cutting laser or cutting tool can be accurately aligned with the second groove 30 and the cutting operation can be carried out along the set cutting path.

[0048] S7. Thinning treatment of the back side of wafer 100: The back side of substrate 1 is thinned by grinding from the initial thickness to 80-100 μm, such as... Figure 3g As shown.

[0049] S8. A third adhesive film 70 is applied to the thinned surface of the wafer back side for protection, such as... Figure 3h As shown.

[0050] S9. Peel off the second adhesive film 40 on chip 2 to expose chip 2. Figure 3i As shown.

[0051] S10. Use the film expander 80 to perform film expansion processing on wafer 100, such as... Figure 3j As shown, the connection segment 60 between the substrate layer 1 at the bottom of two adjacent chips 2 is disconnected to achieve the separation of individual chips, as shown. Figure 3k As shown, a high-frequency vibration force is applied to the bottom of the wafer substrate by a film expander, causing the connecting section 60 to crack and break, thus achieving chip splitting; at the same time, it can also increase the gap between two adjacent chips 2, which facilitates subsequent chip removal operations.

[0052] This embodiment presents an ultrathin wafer cutting method based on laser-induced thermal decomposition pre-cutting, which effectively reduces the abnormalities caused by excessive stress on the wafer surface during cutting, resulting in back bounce or backside microcracks, thereby improving the yield of packaged products.

[0053] The above descriptions are merely some embodiments of the present invention. For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method for dicing ultrathin wafers based on laser-induced thermal decomposition pre-cutting, wherein the wafer comprises a substrate layer and a plurality of chips arrayed on the substrate layer, characterized in that: The cutting method includes the following steps: S1. The first adhesive film is pasted onto the back of the wafer; S2. Using laser-induced thermal decomposition technology, the front side of the wafer is pre-cut according to a set cutting path, and a first groove is formed on the substrate layer. S3. Perform a first half-cutting process on the bottom of the first groove along the set cutting path, cut to a first depth, and form a second groove at the bottom of the first groove, wherein the first depth is less than or equal to half the thickness of the substrate layer. S4. A second adhesive film is pasted onto the front side of the wafer to cover the chip; S5. Remove the first adhesive film; S6. The back side of the wafer is aligned with the second groove and a second half-cut is performed along the set cutting path to a second depth. The sum of the first depth and the second depth is less than the total thickness of the substrate layer. S7. Thinning treatment is performed on the back side of the wafer; S8. A third adhesive film is pasted onto the thinned surface; S9. Remove the second adhesive film; S10. Perform a film expansion process on the wafer to achieve chip separation.

2. The ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting as described in claim 1, characterized in that: The first groove has a trapezoidal cross-section that is wider at the top and narrower at the bottom.

3. The ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting as described in claim 1 or 2, characterized in that: The depth of the first groove is 5–25 μm.

4. The ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting as described in claim 1 or 2, characterized in that: The depth of the first groove should extend to the bottom of the dielectric layer of the wafer.

5. The ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting as described in claim 1, characterized in that: The first depth is the distance from the upper surface of the substrate layer to the bottom of the second groove.

6. The ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting as described in claim 1 or 5, characterized in that: The width of the second groove is less than or equal to the bottom width of the first groove.

7. The ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting as described in claim 1, characterized in that: After step S6 is completed, the substrate layers at the bottom of two adjacent chips are connected together by a connecting segment.

8. The ultrathin wafer dicing method based on laser-induced thermal decomposition pre-cutting as described in claim 1, characterized in that: The cutting in steps S3 and S6 is laser cutting or mechanical cutting.

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