Power element and method of manufacturing the same

Abstract

The present application provides a power device and a manufacturing method thereof. The power device comprises a semiconductor layer, a well region, a body region, a gate, a source and a drain, a first alignment metal silicide barrier layer and a second alignment metal silicide barrier layer. The first alignment metal silicide barrier layer is formed on the upper surface of the semiconductor layer and is between the gate and the drain, and part of the well region is located and connected directly below the first alignment metal silicide barrier layer. The second alignment metal silicide barrier layer is formed directly above the first alignment metal silicide barrier layer and is connected to the first alignment metal silicide barrier layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a power device and a manufacturing method thereof, and more particularly to a power device capable of improving breakdown voltage and a manufacturing method thereof. BACKGROUND

[0002] Figure 1 A cross-sectional view of a known power device 100 and metal oxide semiconductor (MOS) devices 100a and 100b is shown. The power device refers to a device in which the voltage applied to the drain is higher than 5V during normal operation. Generally, the power device has a drift region 12a (shown in the dashed box) between the drain 19 and the body region 16, and the lateral length of the drift region 12a is adjusted according to the operating voltage during normal operation. As shown, the power device 100 includes a well region 12, an insulating structure 13, a barrier layer 14, a body region 16, a gate 17, a source 18, and a drain 19. Figure 1 Figure 1

[0003] As shown, the substrate 11 is divided into a high voltage region 13a and a low voltage region 13b. The well region 12 of the high voltage region 13a and the low voltage region 13b is formed by the same process step; the gate of the high voltage region 13a and the low voltage region 13b is formed by the same process step; and the barrier layer 14 of the high voltage region 13a and the low voltage region 13b is formed by the same process step. Basically, the power device 100 in which the voltage applied to the drain is higher than 5V is formed in the high voltage region 13a, and the MOS devices 100a and 100b in which the voltage applied to the drain is not higher than 5V are formed in the low voltage region 13b. The MOS devices 100a and 100b are shown with the gate and the barrier layer 14; other parts such as the source and the drain are omitted here. The insulating structure 13 is a local oxidation of silicon (LOCOS) structure to define an operating region as the main active region during operation of the power device 100. Figure 1 Figure 1

[0004] ​​​​The barrier layer 14 is formed in the high-voltage region 13a and the low-voltage region 13b by the same process to avoid the need for the protected region to be in direct contact with the metal layer after the gate electrode, and to block the metal layer. In the power element 100, the thickness of the barrier layer 14 limits the breakdown voltage of the power element 100, but in the MOS elements 100a and 100b in the low-voltage region 13b, the gap between the MOS elements 100a and 100b is small relative to the gap between the power elements in the high-voltage region 13a due to the miniaturization of the MOS elements 100a and 100b; thus, the thickness of the barrier layer 14 in the power element 100 is limited by the thickness of the barrier layer 14 in the MOS elements 100a and 100b in the low-voltage region 13b, which limits the breakdown voltage of the power element 100 and limits the range of applications of the power element 100; and if the thickness of the barrier layer 14 is increased to increase the withstand voltage of the power element 100, the barrier layer 14 in the MOS elements 100a and 100b will have a residual problem when formed.

[0005] Therefore, the present application provides a power element capable of improving the breakdown voltage in the non-conducting operation and a manufacturing method thereof. SUMMARY

[0006] In one aspect, the present application provides a power element, comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface; a well region having a first conductivity type formed in the semiconductor layer, and the well region being located below and connected to the upper surface; a body region having a second conductivity type formed in the semiconductor layer, and the body region being located below and connected to the upper surface, and the body region being adjacent to the well region in a channel direction; a gate electrode formed on the upper surface, and part of the body region being located directly below and connected to the gate electrode to provide a reverse current channel of the power element in a conducting operation, and part of the well region adjacent to the body region being located directly below the gate electrode to provide a drift current channel of the power element in the conducting operation; a source electrode and a drain electrode having the first conductivity type, and the source electrode and the drain electrode being formed below and connected to the upper surface, and the source electrode and the drain electrode being located in the body region below the gate electrode on the outside and in the well region away from the body region side, respectively; a first salicide block (SAB) layer formed on the upper surface, and the first SAB layer being located between the gate electrode and the drain electrode, and part of the well region being located directly below and connected to the first SAB layer; and a second SAB layer formed above and connected to the first SAB layer.

[0007] In another aspect, the present disclosure provides a power device manufacturing method, comprising: forming a semiconductor layer on a substrate, the semiconductor layer having an upper surface; forming a well region in the semiconductor layer, the well region having a first conductivity type, and the well region being located below and connected to the upper surface; forming a body region in the semiconductor layer, the body region having a second conductivity type, and the body region being located below and connected to the upper surface, the body region being adjacent to the well region in a channel direction; forming a gate on the upper surface, part of the body region being located directly below and connected to the gate to provide a reverse current channel of the power device in an on operation, and part of the well region adjacent to the body region being located directly below the gate to provide a drift current channel of the power device in the on operation; forming a source and a drain below and connected to the upper surface, the source and the drain having the first conductivity type, and the source and the drain being located in the body region below the gate outside and in the well region away from the body region side respectively; forming a first salicide block (SAB) layer on the upper surface, the first SAB layer being located between the gate and the drain, and part of the well region being located directly below and connected to the first SAB layer; and forming a second SAB layer directly above and connected to the first SAB layer.

[0008] In an embodiment, the power device further comprises an aligned metal silicide layer having electrical conductivity, the aligned metal silicide layer being formed on and connected to the second SAB layer, the aligned metal silicide layer being electrically connected to a predetermined potential to alleviate the electric field distribution when the power device is operated.

[0009] In an embodiment, the power device is a laterally diffused metal oxide semiconductor (LDMOS) device.

[0010] In an embodiment, the first SAB layer and the second SAB layer have a dielectric constant after being stacked, the dielectric constant being lower than 3.9.

[0011] In an embodiment, the first SAB layer and the second SAB layer have a dielectric constant after being stacked, the dielectric constant being higher than 3.9.

[0012] In an embodiment, the first SAB layer and the second SAB layer have a dielectric constant after being stacked, the dielectric constant being equal to 3.9.

[0013] In one embodiment, the substrate has a low voltage region and a high voltage region, wherein the power device is formed in the high voltage region; wherein a plurality of metal oxide semiconductor (MOS) devices are formed in the low voltage region; wherein the first SAB layer is formed in the low voltage region and the high voltage region; wherein the second SAB layer is formed in the high voltage region and not in the low voltage region.

[0014] In one embodiment, the thickness of the second SAB layer is adjusted according to the requirement of off-state breakdown voltage of the power device.

[0015] The advantage of the present application is that the present application can improve the off-state breakdown voltage.

[0016] The purposes, technical contents, characteristics and effects of the present application will be more apparent through the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A cross-sectional view of a known power device and metal oxide semiconductor device is shown.

[0018] Figure 2 A cross-sectional view of a power device and metal oxide semiconductor device according to one embodiment of the present application is shown.

[0019] Figure 3 A cross-sectional view of a power device according to one embodiment of the present application is shown.

[0020] Figure 4 A cross-sectional view of a power device manufacturing method according to one embodiment of the present application is shown.

[0021] Figures 5A-5H A cross-sectional view of a power device manufacturing method according to one embodiment of the present application is shown.

[0022] BRIEF DESCRIPTION OF DRAWINGS

[0023] 11, 21: substrate

[0024] 12, 22: well region

[0025] 12a, 22a: drift region

[0026] 13a, 23a: high voltage region

[0027] 13b, 23b: low voltage region

[0028] 13: insulating structure

[0029] 14: barrier layer

[0030] 16, 26: body region

[0031] 17, 27: gate

[0032] 18, 28: source

[0033] 19, 29: drain

[0034] 21': semiconductor layer

[0035] 21a: upper surface

[0036] 21b: lower surface

[0037] 25: alignment metal silicide layer

[0038] 26', 28': photoresist layer

[0039] 100, 200: power element

[0040] 100a, 100b, 200a, 200b: MOS element

[0041] 241: first SAB layer

[0042] 242: second SAB layer

[0043] 271: dielectric layer

[0044] 272: conductive layer

[0045] 273: spacer layer DETAILED DESCRIPTION

[0046] The foregoing and other technical contents, features and effects of the present application will be apparent from the following detailed description of the preferred embodiments, given by way of example only, with reference to the accompanying drawings. The drawings of the present application are all schematic and mainly intended to represent the process steps and the up-down sequence relationship between the layers, rather than being drawn in accordance with the proportions of the shapes, thicknesses and widths.

[0047] Reference is made to Figure 2 , which is a cross-sectional schematic view showing a power element 200 and metal oxide semiconductor (MOS) elements 200a and 200b according to an embodiment of the present application. As shown in Figure 2 , the power element 200 includes a well region 22, a first alignment metal silicide block (SAB) layer 241, a second SAB layer 242, a body region 26, a gate 27, a source 28 and a drain 29.

[0048] The well region 22 is of a first conductivity type and is formed on a substrate 21. As shown in Figure 2As shown, substrate 21 is divided into a high-voltage region 23a and a low-voltage region 23b. The well regions 22 of both high-voltage and low-voltage regions 23a and 23b are formed using the same process step; the gates of both regions are formed using the same process step; and the first SAB layer 241 of both regions is formed using the same process step. Essentially, power devices 200 with a drain voltage higher than 5V are formed in high-voltage region 23a, while MOS devices 200a and 200b with a drain voltage not higher than 5V are formed in low-voltage region 23b. MOS devices 200a and 200b are... Figure 2 The gate and the first aligned metal silicide barrier layer 241 are shown in the diagram; other parts of the MOS elements 200a and 200b, such as the source and drain, are omitted here.

[0049] To isolate the metal layer behind the gate in the high-voltage region 23a and the low-voltage region 23b from the partial well region 22, and to prevent the protected area from directly contacting the metal layer, the first SAB layer 241 is formed simultaneously in both the high-voltage region 23a and the low-voltage region 23b using the same process. The second SAB layer 242 is formed only in the high-voltage region 23a and not in the low-voltage region 23b, and the second SAB layer 242 is formed directly above and connected to the first SAB layer 241.

[0050] like Figure 3 As shown, the power device 200 includes: a semiconductor layer 21', a well region 22, a first SAB layer 241, a second SAB layer 242, an alignment metal silicide layer 25, a body region 26, a gate 27, a source 28, and a drain 29. The semiconductor layer 21' is formed on the substrate 21; the well region 22, the source 28, and the drain 29 have a first conductivity type; the body region 26 has a second conductivity type. The power device 200 is, for example, as shown below. Figure 3 The illustrated device is a lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS). The power device according to the invention can be applied, for example, to a power stage circuit in a switching power supply circuit, which is well known to those skilled in the art and will not be described in detail here.

[0051] Semiconductor layer 21' is formed on substrate 21, and semiconductor layer 21' is in the vertical direction (e.g. Figure 3The substrate 21, for example but not limited to, is a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21' is formed on the substrate 21, for example but not limited to, by an epitaxial step, or is part of the substrate 21. The manner of forming the semiconductor layer 21' is well known to those skilled in the art and will not be described here.

[0052] Please continue to refer to Figure 3 The well region 22 has a first conductivity type and is formed in the semiconductor layer 21' and is located below and connected to the upper surface 21a. The body region 26 has a second conductivity type and is formed in the semiconductor layer 22 and is located below and connected to the upper surface 21a, and the body region 26 is adjacent to the well region 22 in the channel direction (as indicated by the solid arrow direction in Figure 3 The gate 27 is formed on the upper surface 21a, and part of the body region 26 is located directly below and connected to the gate 27 to provide a reverse current channel of the power element 200 in the on-state, and part of the well region 22 is located directly below the gate 27 to provide a drift current channel of the power element 200 in the on-state (as indicated by the thick dashed box in Figure 3 The source 28 and the drain 29 have the first conductivity type, and the source 28 and the drain 29 are formed below and connected to the upper surface 21a, and the source 28 and the drain 29 are respectively located in the body region 26 below the outside of the gate 27 and in the well region 22 away from the body region 26.

[0053] Please continue to refer to Figure 3 The first SAB layer 241 is formed on the upper surface 21a, and the first SAB layer 241 is located between the gate 27 and the drain 29, and part of the well region 22 is located directly below and connected to the first SAB layer 241. The second SAB layer 242 is formed directly above and connected to the first SAB layer 241. In an embodiment, the thickness of the second SAB layer 242 can be greater than the thickness of the first SAB layer 241. In an embodiment, the second SAB layer 242 can have multiple layers. The first SAB layer 241 and the second SAB layer 242 superimposed have a dielectric constant. In an embodiment, the aforementioned dielectric constant is lower than 3.9. In another embodiment, the aforementioned dielectric constant is higher than 3.9. In yet another embodiment, the aforementioned dielectric constant is equal to 3.9. In an embodiment, the thickness of the second SAB layer 242 can be adjusted according to the requirement of the off-state breakdown voltage of the power element 200.

[0054] As Figure 3As shown, the alignment metal silicide layer 25 has electrical conductivity, and is formed on and connected to the second SAB layer 242. The alignment metal silicide layer 25 is used to be electrically connected to a predetermined potential, so as to alleviate the electric field distribution and optimize the withstand voltage when the power element 200 is operated. In an embodiment, the alignment metal silicide layer 25 is, for example, a polysilicon doped with impurities, and can also be a compound of polysilicon and metal, such as, but not limited to, tungsten silicide, cobalt silicide, titanium silicide, and nickel silicide.

[0055] The gate 27 includes a dielectric layer 271 connected to the upper surface 21a, a conductive layer 272 having electrical conductivity, and a spacer layer 273 having electrical insulation properties. The gate 27 is used to be controlled by a control signal to turn on and off the power element 200.

[0056] Please continue to refer to Figure 3 In the channel direction, the drift region 22a is located between and separates the drain 29 and the body region 26, and is located in the well region 22 close to the upper surface 21a, and is used as a drift current channel in the on operation of the power element 200.

[0057] It should be noted that the so-called reverse current channel refers to a region in which, in the on operation of the power element 200, an inversion layer is formed below the gate 27 due to the voltage applied to the gate 27, so that the on current passes through, which is well known to those skilled in the art and will not be described here.

[0058] It should be noted that the so-called drift current channel refers to a region in which, in the on operation of the power element 200, the on current passes through in a drift manner, which is well known to those skilled in the art and will not be described here.

[0059] It should be noted that the upper surface 21a does not refer to a completely flat plane, but to a surface of the semiconductor layer 21'.

[0060] It should be noted that the aforementioned "first conductivity type" and "second conductivity type" refer to impurities of different conductivity types being doped in a semiconductor component region (such as, but not limited to, the aforementioned well region, body region, source, and drain, etc.) in the power element, so that the semiconductor component region becomes the first or second conductivity type (such as, but not limited to, the first conductivity type is N-type, and the second conductivity type is P-type, or vice versa), wherein the first conductivity type and the second conductivity type are conductivity types opposite to each other in electrical properties.

[0061] Further, it is noted that the so-called power device is a device that, in normal operation, has a voltage applied to the drain that is higher than a certain voltage, for example 5 V, and the lateral distance of the body region 26 from the drain 29 (the length of the drift region) is adapted to the operating voltage to be withstood in normal operation, so that the device can be operated at the aforementioned higher certain voltage. This is known to the person skilled in the art and will not be described in more detail here.

[0062] Figure 4 is a diagram showing the sum thickness of the first SAB layer and the second SAB layer versus the off-state breakdown voltage of the power device according to an embodiment of the present application. As shown in Figure 4 , in the case of a dielectric constant of less than 3.9 after the first SAB layer 241 and the second SAB layer 242 are stacked, the off-state breakdown voltage is better when the sum thickness of the first SAB layer 241 and the second SAB layer 242 is about 450 A. In the case of a dielectric constant of equal to 3.9 after the first SAB layer 241 and the second SAB layer 242 are stacked, the off-state breakdown voltage is better when the sum thickness of the first SAB layer 241 and the second SAB layer 242 is about 650 A. In the case of a dielectric constant of more than 3.9 after the first SAB layer 241 and the second SAB layer 242 are stacked, the off-state breakdown voltage is better when the sum thickness of the first SAB layer 241 and the second SAB layer 242 is about 800 A. According to the present application, the material and thickness of the second SAB layer can be selected or adjusted according to different dielectric constants and the best off-state breakdown voltage.

[0063] Reference is made to Figures 5A-5H , which shows a cross-sectional view of a method of manufacturing a power device 200. As shown in Figure 5A , a substrate 21 is first provided, which is for example but not limited to a P-type or N-type semiconductor silicon substrate. Then, as shown in Figure 5B , a semiconductor layer 21' is formed on the substrate 21, which has opposite upper and lower surfaces 21a and 21b in the vertical direction (as shown by the dotted arrow in Figure 5B , the same applies hereinafter). The semiconductor layer 21' is formed on the substrate 21, for example by epitaxy, or is formed using part of the substrate 21. The manner in which the semiconductor layer 21' is formed is known to the person skilled in the art and will not be described in more detail here.

[0064] Reference is made to Figure 5B , then a well region 22 is formed in the semiconductor layer 21', and in the vertical direction the well region 22 is located below and connected to the upper surface 21a. The well region 22 has a first conductivity type, which can be formed, for example but not limited to, by means of an ion implantation process step, in which first conductivity type impurities are implanted in the form of accelerated ions, for example but not limited to boron or gallium. Figure 5BThe downward-pointing dashed arrow indicates that the material is injected into the semiconductor layer 21' to form a well region 22.

[0065] Next, please refer to Figure 5C A body region 26 is formed in the semiconductor layer 21', and the body region 26 is located below and connected to the upper surface 21a. The body region 26 is in the channel direction (e.g. Figure 5C (As indicated by the solid arrow in the image, the same applies below) It is adjacent to the well region 22. A portion of the body region 26 is located directly below and connected to the subsequently formed gate 27 to provide a reverse current path for the power element 200 during conduction operation. The body region 26 has a second conductivity type. The steps for forming the body region 26 include, for example but not limited to, using a photoresist layer 26' formed by a photolithography process as a shield, doping the well region 22 of the semiconductor layer 21' with a second conductivity type impurity, and counterdoping a defined portion from the well region 22 to form the body region 26. In this embodiment, for example but not limited to, an ion implantation process can be used to implant a portion of the well region 22 with a second conductivity type impurity in the form of accelerated ions to form the body region 26.

[0066] Next, please refer to Figure 5D A gate 27 is formed on the upper surface 21a of the semiconductor layer 21'. A portion of the body region 26 is located directly below the gate 27 and connected to the gate 27 to provide a reverse current path for the power element 200 during conduction operation. A portion of the well region 22 is located directly below the gate 27 to provide a drift current path for the power element 200 during conduction operation.

[0067] The gate 27 includes a dielectric layer 271 connected to the upper surface 21a, a conductive layer 272 having conductive properties, and a spacer layer 273 having electrical insulating properties. The gate 27 is used to receive control signals to control the power element 200 to turn on and off.

[0068] Please refer to the following section. Figure 5EThe source 28 and the drain 29 are formed under the upper surface 21a and connected to the upper surface 21a, and the source 28 and the drain 29 are respectively located in the body region 26 under the gate 27 in the channel direction and in the well region 22 away from the body region 26 side, and in the channel direction, the drift region 22a is located between the drain 29 and the body region 26 in the well region 22 close to the upper surface 21a, and is used as a drift current channel of the power element 200 in the on operation. The steps of forming the source 28 and the drain 29, for example but not limited to, using the gate 27 and the photoresist layer 28' formed by the photolithography process step as a shield, the first conductive type impurity is doped into the body region 26 and the well region 22 respectively, to form the source 28 and the drain 29. Among them, the first conductive type impurity can be used, for example but not limited to, ion implantation process step, the first conductive type impurity is implanted into the body region 26 and the well region 22 in the form of accelerated ions, to form the source 28 and the drain 29.

[0069] Next, referring to Figure 5F The first SAB layer 241 is formed on the upper surface 21a. The first SAB layer 241 is located between the gate 27 and the drain 29, and part of the well region 22 is located and connected directly below the first SAB layer 241. The steps of forming the first SAB layer 241, for example but not limited to, are formed by deposition process step, photolithography process step and etching process step. The first SAB layer 241 can be formed in the high voltage region and the low voltage region at the same time by the same process step.

[0070] Next, referring to Figure 5G The second SAB layer 242 is formed directly above the first SAB layer 241 and connected to the first SAB layer 241. The steps of forming the second SAB layer 242, for example but not limited to, are formed by deposition process step, photolithography process step and etching process step. It should be noted that the second SAB layer 242 is only formed in the high voltage region, not in the low voltage region.

[0071] Next, referring to Figure 5H The aligned metal silicide layer 25 is formed on the second SAB layer 242, so that the aligned metal silicide layer 25 is connected to the second SAB layer 242. The aligned metal silicide layer 25 has conductivity and is used to be electrically connected to a predetermined potential to alleviate the electric field distribution when the power element 200 operates. The steps of forming the aligned metal silicide layer 25, for example but not limited to, are formed by deposition process step, photolithography process step and etching process step.

[0072] The above has been described for the preferred embodiments of the present application, but the above description is merely to enable those skilled in the art to understand the content of the present application, and is not intended to limit the scope of the rights of the present application. Various equivalent changes can be conceived by those skilled in the art in the same spirit of the present application. For example, other process steps or structures such as a metal silicide layer can be added without affecting the main characteristics of the elements; again, the lithography technology is not limited to the mask technology, and can also include electron beam lithography technology. All of these can be analogized according to the teachings of the present application. In addition, each of the embodiments described is not limited to separate application, and can be combined, such as but not limited to combining two embodiments. Therefore, the scope of the present application should encompass all of the above and other equivalent changes. In addition, any implementation form of the present application does not necessarily achieve all the purposes or advantages, and therefore, any item of the claims should not be limited thereto.

Claims

1. A power element, characterized by Comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface; a well region having a first conductivity type formed in the semiconductor layer, and the well region is located below and connected to the upper surface; a body region having a second conductivity type formed in the semiconductor layer, and the body region is located below and connected to the upper surface, and the body region is adjacent to the well region in a channel direction; a gate formed on the upper surface, and part of the body region is located directly below and connected to the gate to provide a reverse current channel of the power element in a conducting operation, and part of the well region adjacent to the body region is located directly below the gate to provide a drift current channel of the power element in the conducting operation; a source and a drain having the first conductivity type, and the source and the drain are formed below and connected to the upper surface, and the source and the drain are respectively located in the body region below the gate and in the well region away from the body region side; a first alignment metal silicide barrier layer formed on the upper surface, and the first alignment metal silicide barrier layer is located between the gate and the drain, and part of the well region is located directly below and connected to the first alignment metal silicide barrier layer; and a second alignment metal silicide barrier layer formed above and connected to the first alignment metal silicide barrier layer; wherein the substrate has a low voltage region and a high voltage region, and the power element is formed in the high voltage region; wherein a plurality of metal oxide semiconductor elements are formed in the low voltage region; wherein the first alignment metal silicide barrier layer is formed in the low voltage region and the high voltage region; wherein the second alignment metal silicide barrier layer is formed in the high voltage region and is not located in the low voltage region.

2. The power element of claim 1, wherein, Further comprising an alignment metal silicide layer having conductivity, and the alignment metal silicide layer is formed on and connected to the second alignment metal silicide barrier layer, and the alignment metal silicide layer is used to be electrically connected to a predetermined potential to alleviate the electric field distribution when the power element operates.

3. The power component of claim 1, wherein, The power element is a lateral diffusion metal oxide semiconductor element.

4. The power component of claim 1, wherein, The first alignment metal silicide barrier layer and the second alignment metal silicide barrier layer have a dielectric constant after being superimposed, and the dielectric constant is lower than 3.

9.

5. The power component of claim 1, wherein, The first alignment metal silicide barrier layer and the second alignment metal silicide barrier layer have a dielectric constant after being superimposed, and the dielectric constant is higher than 3.

9.

6. The power component of claim 1, wherein, The first alignment metal silicide barrier layer and the second alignment metal silicide barrier layer have a dielectric constant after being superimposed, and the dielectric constant is equal to 3.

9.

7. The power component of claim 1, wherein, The thickness of the second alignment metal silicide barrier layer is adjusted according to the requirement of non-conducting breakdown voltage of the power element.

8. A power device manufacturing method, characterized by, Comprising: forming a semiconductor layer on a substrate, the semiconductor layer having an upper surface; forming a well region in the semiconductor layer, and the well region has a first conductivity type, and the well region is located below and connected to the upper surface; forming a body region in the semiconductor layer, the body region having a second conductivity type, and the body region being located below and connected to the upper surface, the body region being contiguous to the well region in a channel direction; forming a gate on the upper surface, part of the body region being located directly below and connected to the gate to provide a reverse current channel of the power element in an on-operation, and part of the well region contiguous to the body region being located directly below the gate to provide a drift current channel of the power element in the on-operation; forming a source and a drain below and connected to the upper surface, and the source and the drain having the first conductivity type, and the source and the drain being located in the body region below and away from the well region outside of the gate, respectively; forming a first alignment metal silicide barrier on the upper surface, and the first alignment metal silicide barrier being located between the gate and the drain, and part of the well region being located directly below and connected to the first alignment metal silicide barrier; and forming a second alignment metal silicide barrier on and connected to the first alignment metal silicide barrier; wherein the substrate has a low voltage region and a high voltage region, and the power element is formed in the high voltage region; wherein a plurality of metal oxide semiconductor elements are formed in the low voltage region; wherein the first alignment metal silicide barrier is formed in the low voltage region and the high voltage region; wherein the second alignment metal silicide barrier is formed in the high voltage region, and not in the low voltage region.

9. The power device manufacturing method according to claim 8, wherein further comprising forming an alignment metal silicide layer on and connected to the second alignment metal silicide barrier, the alignment metal silicide layer having electrical conductivity and being electrically connected to a predetermined potential to mitigate electric field distribution when the power element is operated.

10. The power device manufacturing method according to claim 8, wherein The power element is a lateral diffusion metal oxide semiconductor element.

11. The power device manufacturing method according to claim 8, wherein The first alignment metal silicide barrier and the second alignment metal silicide barrier, when stacked, have a dielectric constant lower than 3.

9.

12. The power device manufacturing method according to claim 8, wherein The first alignment metal silicide barrier and the second alignment metal silicide barrier, when stacked, have a dielectric constant higher than 3.

9.

13. The power device manufacturing method according to claim 8, wherein The first alignment metal silicide barrier and the second alignment metal silicide barrier, when stacked, have a dielectric constant equal to 3.

9.

14. The power device manufacturing method according to claim 8, wherein The thickness of the second alignment metal silicide barrier is adjusted according to the off-breakdown voltage requirement of the power element.

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