A voltage detection circuit for motor-driven adaptive dead-time control
By detecting the gate voltage of the high-side power transistor through an adaptive dead-time control circuit, the problem of increased power loss in traditional motor drive circuits is solved, adaptive dead-time control is achieved, and power consumption is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI I CORE ELECTRONICS
- Filing Date
- 2022-12-09
- Publication Date
- 2026-05-26
AI Technical Summary
The fixed dead time design in traditional motor drive circuits leads to increased power loss and cannot adapt to the needs under different power supply voltages.
Design an adaptive dead-time control voltage detection circuit for motor drive. By detecting the gate voltage of the high-side power transistor, output logic control signal to control the conduction state of the low-side power transistor. Adaptive control of dead time is achieved using only one high-voltage device.
It reduces power loss caused by excessively long dead time, has a wide applicable voltage range, low power consumption, and is suitable for systems with special requirements.
Smart Images
Figure CN115940583B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a voltage detection circuit for adaptive dead-time control of motor drive. Background Technology
[0002] In the H-bridge of a motor drive circuit, the power transistor connected to the power supply is the high-side power transistor, and the power transistor connected to ground is the low-side power transistor. The gate control signals for the high-side and low-side power transistors are generated by the high-side and low-side drive circuits, respectively, to control the operation of the bridge circuit. To ensure that the high-side and low-side power transistors do not conduct simultaneously and to avoid shoot-through damage to the circuit, a dead time needs to be set during the switching process of the power transistors to protect the circuit's safe operation. Traditional drive circuits use a fixed dead time, which is relatively simple in principle. However, to ensure that shoot-through does not occur under all conditions, the dead time is usually designed to be relatively long, which increases the conduction time of the body diode and increases power loss. Furthermore, when the drive circuit is applied in different scenarios and under different power supply voltages, considering the impact of power consumption, different dead times may be required. Obviously, the traditional fixed dead time circuit is no longer suitable.
[0003] In the design of an adaptive dead-time circuit, a voltage detection circuit is required to detect the gate voltage of the high-side power transistor. When the gate voltage drops to a level that turns off the high-side power transistor, a logic control signal is output to turn on the low-side power transistor. The voltage detection circuit not only needs to accurately detect the gate voltage of the high-side power transistor but also needs to perform level shifting. The circuit structure should be simple, with few high-voltage components and low power consumption.
[0004] Existing technologies such as Figure 1 As shown, it mainly includes an interface module, a dead time module, a high-side driver, a low-side driver, a high-side power transistor N1, and a low-side power transistor N2.
[0005] Interface module: Receives control signals IN1 and IN2, and performs shaping and logical operations on the control signals.
[0006] Dead time module: Sets the dead time for signals IN1_HS and IN2_LS to ensure that outputs DRV_HS and DRV_LS will not be high at the same time, thus ensuring that power transistors N1 and N2 will not be turned on at the same time.
[0007] High-side drive: The high-side transistor logic control signal DRV_HS is level-shifted, logic-judged, etc., and the high-side transistor gate drive signal VG_HS is output.
[0008] Low-side drive: The low-side transistor logic control signal DRV_LS is level-shifted, logic-judged, etc., and the low-side transistor gate drive signal VG_LS is output.
[0009] In order to ensure that no shoot-through occurs under any conditions, the above-mentioned drive circuit has a relatively long dead time, which increases the conduction time of the body diode and increases power loss.
[0010] In traditional motor drive circuits, a fixed dead time is used to prevent the power transistor (bridge arm) from shooting. To ensure that the power transistor will not shoot under various conditions, the dead time is usually set to be relatively long, which greatly increases the power loss of the bridge arm. Summary of the Invention
[0011] The purpose of this invention is to provide a voltage detection circuit for adaptive dead-time control of motor drive, so as to solve the problems mentioned in the background art.
[0012] To achieve the above objectives, the present invention provides the following technical solution: a voltage detection circuit for adaptive dead-time control of motor drive, the voltage detection circuit including a high-voltage transistor NM_H, bias current I1, bias current I2, bias current I3, power supply voltage VDD, constant-voltage transistor PM1, constant-voltage transistor PM2, constant-voltage transistor NM1 and inverter INV4;
[0013] The input signal VG_HS on the high-voltage transistor NM_H is the signal to be detected. The input INV_HS_N on the gate of the constant-voltage transistor PM1 is a logic control signal, which is inverted with VG_HS. The output VOUT is the detection result. The power supply voltage VDD is a low-voltage logic power supply.
[0014] The drain of the high-voltage transistor NM_H is connected to the input signal VG_HS, and its gate is electrically connected to the logic power supply VDD. Its source intersects the bias current I1, the gate of the constant-voltage transistor PM2, and its source at point A. The other end of the bias current I1 is electrically connected to GND. The drain of the constant-voltage transistor PM2, the drain of PM1, and the gate of the constant-voltage transistor NM1 intersect at point B. The source of the constant-voltage transistor PM1 is connected to the power supply voltage VDD, and the source of the constant-voltage transistor NM1 is electrically connected to GND. Its drain intersects the bias current I2 and the input terminal of the inverter INV4 at point C. The other end of the bias current I2 is electrically connected to VDD. One end of the bias current I3 is electrically connected to the power supply voltage VDD, and the other end is connected to the power supply terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to VOUT.
[0015] Preferably, the system in which it is applied includes AND gate AND1, AND gate AND2, inverter INV1, inverter INV2, inverter INV3, high-side drive, low-side drive, voltage detection circuit, high-side power transistor N1 and low-side power transistor N2;
[0016] The high-side drive is used to perform level conversion and logic judgment on the logic control signal IN1_HS of the high-side power transistor N1, and to output the gate control signal VG_HS of the high-side power transistor N1.
[0017] The low-side drive is used to perform level conversion and logic judgment on the logic control signal IN2_LS of the low-side power transistor N2, and output the gate control signal VG_LS of the low-side power transistor N2.
[0018] The voltage detection circuit is used to detect the gate voltage VG_HS of the high-side power transistor N1. When the gate voltage VG_HS of the high-side power transistor N1 drops to the turn-off voltage of the high-side power transistor N1, the logic control signal VOUT is output.
[0019] Preferably, a voltage VM is electrically connected to the drain of the high-side power transistor N1, the voltage VM being the power supply voltage of the power transistor. A signal IN1 is connected to the input terminal of the AND gate AND1, the signal IN1 being the input control signal of the high-side power transistor. A signal IN2 is connected to the input terminal of the AND gate AND2, the signal IN2 being the input control signal of the low-side power transistor. The signals IN1 and IN2 will not be high at the same time.
[0020] When signal IN1 is high and signal IN2 is low, the voltage detection circuit outputs VOUT at a high level, the AND gate AND2 outputs IN2_LS at a low level, the low-side driver outputs VG_LS at a low level, the AND gate AND1 outputs IN1_HS at a high level, and the high-side driver outputs VG_HS at a high level. At this time, the high-side power transistor N1 is turned on, and the low-side power transistor N2 is turned off.
[0021] Preferably, when the signal IN1 transitions from high to low, the signal IN2 transitions from low to high, and the signal IN1_HS transitions from high to low, the gate voltage VG_HS of the high-side power transistor N1 begins to decrease. Since VG_HS is still relatively high, the output VOUT of the voltage detection circuit remains high. After inverting VOUT, an AND operation is performed with the signal IN2, resulting in the output IN2_LS remaining low. The low-side power transistor N2 remains off. When the gate voltage VG_HS of the high-side power transistor N1 drops to a very low level, the high-side power transistor N1 turns off, the output VOUT of the voltage detection circuit transitions to low, the signal IN2_LS transitions to high, the gate voltage VG_LS of the low-side power transistor N2 begins to rise, and the low-side power transistor N2 begins to conduct.
[0022] Preferably, when the signal IN1 is low and the signal IN2 is high, the voltage detection circuit outputs VOUT at a low level, IN2_LS at a high level, VG_LS at a high level, IN1_HS at a low level, and VG_HS at a low level. At this time, the high-side power transistor N1 is turned off and the low-side power transistor N2 is turned on.
[0023] Preferably, when the signal IN1 jumps from low to high, the signal IN2 jumps from high to low, and the signal IN2_LS jumps from high to low, the gate voltage VG_LS of the low-side power transistor N2 begins to decrease. Since VG_LS is still relatively high, it is inverted and ANDed with the signal IN1. The output IN1_HS is still low, and the high-side power transistor N1 is still in the off state.
[0024] When the gate voltage VG_LS of the low-side power transistor N2 drops to a very low level, the low-side power transistor N2 is turned off, and IN1_HS jumps to a high level. When the gate voltage VG_HS of the high-side power transistor N1 starts to rise, the high-side power transistor N1 starts to turn on.
[0025] Preferably, the input terminal of AND gate AND1 is electrically connected to the output terminal of inverter INV2, the input terminal of inverter INV2 is electrically connected to the output terminal of the low-side driver, and the output terminal of AND gate AND1 is electrically connected to the input terminal of the high-side driver.
[0026] Preferably, the input terminal of the inverter INV1 is electrically connected to the output terminal of the AND gate AND1, the output terminal of the inverter INV1 is electrically connected to the voltage detection circuit, the other end of the voltage detection circuit is electrically connected to the output terminal of the high-side drive, and the output terminal of the high-side drive is electrically connected to the gate of the high-side power transistor N1.
[0027] Preferably, the input terminal of the AND gate AND2 is electrically connected to the output terminal of the inverter INV3, the output terminal of the voltage detection circuit is electrically connected to the input terminal of the inverter INV3, the output terminal of the AND gate AND2 is electrically connected to the input terminal of the low-side drive, the output terminal of the low-side drive is electrically connected to the gate of the low-side power transistor N2, the source of the low-side power transistor N2 is electrically grounded, and the drain of the low-side power transistor N2 is electrically connected to the source of the high-side power transistor N1.
[0028] Preferably, the power supply voltage VDD is a low-voltage logic power supply, typically 3.3V or 5V, and the bias currents I1, I2 and I3 are all nA-level bias currents.
[0029] Compared with the prior art, the beneficial effects of the present invention are:
[0030] The voltage detection circuit of this invention is used to detect the gate voltage of the high-side power transistor. Its output is processed with the logic control signal of the low-side power transistor to control the operating state of the low-side power transistor. The low-side power transistor can only be turned on when the gate voltage of the high-side power transistor drops to a very low level (power transistor off), preventing shoot-through between the high-side and low-side power transistors. This invention can detect voltage signals in the high-voltage domain and can be used in systems with special requirements. Its detection principle and circuit implementation are simple, using only one high-voltage device, with a small area, low power consumption, and a wide applicable voltage range. Applying this circuit can achieve adaptive control of the dead time, reducing the power loss caused by an excessively long fixed dead time; and it can use a small bias current, resulting in very low power consumption. Attached Figure Description
[0031] Figure 1 A schematic diagram of the dead-time drive circuit is provided in the prior art of this invention;
[0032] Figure 2 This is a schematic diagram of the motor drive circuit using adaptive dead time according to the present invention;
[0033] Figure 3 This is a schematic diagram of the voltage detection circuit of the present invention. Detailed Implementation
[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0035] Please see Figures 2-3This invention provides a technical solution: a voltage detection circuit for adaptive dead-time control of a motor drive. The system includes AND gates AND1 and AND2, inverters INV1, INV2, and INV3, a high-side driver, a low-side driver, a voltage detection circuit, a high-side power transistor N1, and a low-side power transistor N2. The input of AND gate AND1 is electrically connected to the output of inverter INV2, the input of inverter INV2 is electrically connected to the output of the low-side driver, and the output of AND gate AND1 is electrically connected to the input of the high-side driver. The input of inverter INV1 is electrically connected to the output of AND gate AND1. The output terminal of INV1 is electrically connected to the voltage detection circuit, and the other end of the voltage detection circuit is electrically connected to the output terminal of the high-side drive. The high-side drive is electrically connected to the gate of the high-side power transistor N1. The input terminal of AND gate AND2 is electrically connected to the output terminal of inverter INV3. The output terminal of the voltage detection circuit is electrically connected to the input terminal of inverter INV3. The output terminal of AND gate AND2 is electrically connected to the input terminal of the low-side drive. The output terminal of the low-side drive is electrically connected to the gate of the low-side power transistor N2. The source of the low-side power transistor N2 is electrically grounded, and the drain of the low-side power transistor N2 is electrically connected to the source of the high-side power transistor N1.
[0036] The high-side drive is used to perform level conversion and logic judgment on the logic control signal IN1_HS of the high-side power transistor N1, and to output the gate control signal VG_HS of the high-side power transistor N1.
[0037] The low-side drive is used to perform level conversion and logic judgment on the logic control signal IN2_LS of the low-side power transistor N2, and output the gate control signal VG_LS of the low-side power transistor N2.
[0038] The voltage detection circuit is used to detect the gate voltage VG_HS of the high-side power transistor N1. When the gate voltage VG_HS of the high-side power transistor N1 drops to the turn-off voltage of the high-side power transistor N1, the logic control signal VOUT is output.
[0039] A voltage VM is electrically connected to the drain of the high-side power transistor N1, which is the power supply voltage of the power transistor. Signal IN1 is connected to the input of AND gate AND1, and signal IN1 is the input control signal for the high-side power transistor. Signal IN2 is connected to the input of AND gate AND2, and signal IN2 is the input control signal for the low-side power transistor. Signals IN1 and IN2 cannot be high simultaneously. When signal IN1 is high and signal IN2 is low, the voltage detection circuit outputs VOUT high, and the AND gate AND2 outputs IN2_LS low. The low-side drive outputs VG_LS... When LS is low, the output IN1_HS of the AND gate AND1 is high, and the output VG_HS of the high-side drive is high. At this time, the high-side power transistor N1 is turned on, and the low-side power transistor N2 is turned off. When the signal IN1 jumps from high to low, the signal IN2 jumps from low to high, and IN1_HS jumps from high to low, the gate voltage VG_HS of the high-side power transistor N1 begins to decrease. Since VG_HS is still relatively high, the output VOUT of the voltage detection circuit is still high. After inverting it, it is ANDed with the signal IN2, and the output IN2_LS is still low. The low-side power transistor N2 is still in the off state. When the high-side power... When the gate voltage VG_HS of transistor N1 drops to a very low level, the high-side power transistor N1 is turned off, the voltage detection circuit output VOUT jumps to a low level, IN2_LS jumps to a high level, the gate voltage VG_LS of the low-side power transistor N2 starts to rise, and the low-side power transistor N2 starts to conduct. When signal IN1 is low and signal IN2 is high, the voltage detection circuit outputs VOUT as low, IN2_LS as high, VG_LS as high, IN1_HS as low, and VG_HS as low. At this time, the high-side power transistor N1 is turned off, and the low-side power transistor N2... 2. On-state: When the signal IN1 jumps from low to high, the signal IN2 jumps from high to low, and the signal IN2_LS jumps from high to low, the gate voltage VG_LS of the low-side power transistor N2 begins to decrease. Since VG_LS is still relatively high, it is inverted and ANDed with the signal IN1. The output IN1_HS is still low, and the high-side power transistor N1 is still off. When the gate voltage VG_LS of the low-side power transistor N2 drops to a very low level, the low-side power transistor N2 turns off, the signal IN1_HS jumps to a high level, the gate voltage VG_HS of the high-side power transistor N1 begins to rise, and the high-side power transistor N1 begins to conduct.As can be seen from the above, during the switching between the high-side power transistor N1 and the low-side power transistor N2, the high-side power transistor N1 and the low-side power transistor N2 will not experience a shoot-through phenomenon, and the dead time is determined by the fall time of the gate voltage of the power transistor. Under different conditions, the dead time can be adaptively adjusted.
[0040] The voltage detection circuit includes a high-voltage transistor NM_H, bias current I1, bias current I2, bias current I3, power supply voltage VDD, a constant-voltage transistor PM1, a constant-voltage transistor PM2, a constant-voltage transistor NM1, and an inverter INV4.
[0041] The input signal VG_HS on the high-voltage transistor NM_H is the signal to be detected, which is the gate signal of the high-side power transistor N1. The input INV_HS_N on the gate of the constant-voltage transistor PM1 is a logic control signal, which is inverted with VG_HS. The output VOUT is the detection result. The power supply voltage VDD is a low-voltage logic power supply. The value of the low-voltage logic power supply of the power supply voltage VDD is usually 3.3V or 5V. The bias currents I1, I2 and I3 are all nA-level bias currents.
[0042] The drain of the high-voltage transistor NM_H is connected to the input signal VG_HS, and its gate is electrically connected to the logic power supply VDD. Its source intersects the bias current I1, the gate of the constant-voltage transistor PM2, and its source at point A. The other end of the bias current I1 is electrically connected to GND. The drain of the constant-voltage transistor PM2, the drain of PM1, and the gate of the constant-voltage transistor NM1 intersect at point B. The source of the constant-voltage transistor PM1 is connected to the power supply voltage VDD, and the source of the constant-voltage transistor NM1 is electrically connected to GND. Its drain intersects the bias current I2 and the input terminal of the inverter INV4 at point C. The other end of the bias current I2 is electrically connected to VDD. One end of the bias current I3 is electrically connected to the power supply voltage VDD, and the other end is connected to the power supply terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to VOUT.
[0043] Working principle and usage process of this invention:
[0044] When the high-side power transistor N1 is turned on, the input signal VG_HS to be detected is at a high level, and the voltage is the power transistor supply voltage VM plus a turn-on voltage. Therefore, a high-voltage transistor NM_H with a drain capable of withstanding high voltage is connected to it. The source bias current I1 is implemented by a low-voltage transistor. Therefore, the gate of the high-voltage transistor NM_H is connected to the power supply voltage VDD. When VG_HS is at a high level, its source voltage VDD is VDD. A The value is VDD minus the gate-source voltage of the high-voltage transistor NM_H, i.e., V A =VDD-VGS,NM_H This ensures that the voltage at this point does not exceed the device withstand voltage of the low-voltage tube, thus protecting the device.
[0045] The circuit to the right of the dashed line uses the power supply voltage VDD as the power source, which can realize voltage detection and transfer the output detection signal VOUT to the VDD voltage domain, making it convenient to perform logic operations with subsequent logic circuits.
[0046] The bias current I3 connected in series with the inverter INV1 is used to limit the current during its switching process and reduce circuit power consumption.
[0047] When the high-side power transistor N1 is turned on, the input signal VG_HS to be detected is high. At this time, INV_HS_N is low, the constant voltage transistor PM1 is turned on, and V B When the voltage is high, the constant voltage transistor NM1 is turned on, and V... C When the voltage is low, the output VOUT is high.
[0048] When the logic control signal INV1 of the high-side power transistor N1 goes low, the gate voltage VG_HS of the high-side power transistor N1 begins to decrease. When VG_HS > VDD-V GS,NM_H At that time, the voltage at point A remains constant, i.e., V A =VDD-V GS,NM_H At this point, INV_HS_N has switched to a high level, the constant voltage transistor PM1 is off, and V... B =V A +V DS,PM2 =VDD-V GS,NM_H +V DS,PM2 V DS,PM2 V represents the drain-source voltage difference of PM2. Since the drain voltage of the atmospheric pressure tube PM2 is higher than the substrate voltage, the source is short-circuited to the substrate, and the PN junction between the drain and the substrate is forward-biased. DS,PM2 Approximately 0.5V. At this point, the voltage at point B is still relatively high, and the constant-pressure tube NM1 remains conducting. C When the signal is low, the output VOUT remains high. The output signal VOUT performs a logic operation with the low-side logic control signal IN2, and IN2_LS remains low, meaning the low-side power transistor N2 remains off.
[0049] When VG_HS drops to VDD-V GS,NM_H When V is below A As VG_HS decreases, V A =VG_HS, V B =VG_HS+V DS,PM2 V B It also decreases along with VG_HS. When V B The voltage drops to the threshold voltage V of MOSFET NM1 THNThe following is VG_HS+V DS,PM2 <V THN VG_HS <V THN -V DS,PM2 With the constant voltage transistor NM1 off, the voltage at point C begins to rise. When it reaches the switching voltage of inverter INV4, the output VOUT jumps low, and the low-side power transistor N2 begins to conduct. This is because the threshold voltage V of the constant voltage transistor NM1 (typically a 5V device) is... THN Approximately 0.7V, V DS,PM2 The voltage is approximately 0.5V. Therefore, the low-side power transistor N2 will only turn on when VG_HS drops to 0.2V. At this time, the high-side power transistor N1 has already turned off, and there will be no shoot-through.
[0050] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A voltage detection circuit for adaptive dead-time control of motor drive, characterized in that: The circuit includes a voltage detection circuit comprising a high-voltage transistor NM_H, bias currents I1, I2, and I3, a power supply voltage VDD, constant-voltage transistors PM1 and PM2, constant-voltage transistor NM1, and an inverter INV4. The gate control signal VG_HS on the high-voltage transistor NM_H is the signal to be detected. The gate input INV_HS_N of the constant-voltage transistor PM1 is a logic control signal, inverted from VG_HS, and its output VOUT is the detection result. The power supply voltage VDD is a low-voltage logic power supply. The drain of the high-voltage transistor NM_H is connected to the gate control signal VG_HS, and its gate is electrically connected to the power supply voltage VDD. The source of the high-voltage transistor NM_H intersects at point A with one end of the bias current I1, the gate of the constant-voltage transistor PM2, and its source. The other end of the bias current I1 is electrically connected to GND. The drain of the constant-voltage transistor PM2 and the inverter INV4 are connected to the gate of the high-voltage transistor PM1. The drain of the diode and the gate of the constant voltage diode NM1 intersect at point B; the source of the constant voltage diode PM1 is connected to the power supply voltage VDD, the source of the constant voltage diode NM1 is electrically connected to GND, and the drain of the diode intersects at point C with one end of the bias current I2 and the input terminal of the inverter INV4; the other end of the bias current I2 is electrically connected to VDD; one end of the bias current I3 is electrically connected to the power supply voltage VDD, and the other end is connected to the power supply terminal of the inverter INV4; the output terminal of the inverter INV4 is connected to VOUT.
2. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 1, characterized in that: The system includes AND gates AND1 and AND2, inverters INV1, INV2, and INV3, a high-side driver, a low-side driver, a voltage detection circuit, a high-side power transistor N1, and a low-side power transistor N2. The high-side driver performs level shifting and logic judgment on the logic control signal IN1_HS of the high-side power transistor N1, and outputs the gate control signal VG_HS of the high-side power transistor N1. The low-side driver performs level shifting and logic judgment on the logic control signal IN2_LS of the low-side power transistor N2, and outputs the gate control signal VG_LS of the low-side power transistor N2. The voltage detection circuit detects the gate control signal VG_HS of the high-side power transistor N1; when the gate control signal VG_HS of the high-side power transistor N1 drops to the turn-off voltage value of the high-side power transistor N1, it outputs the logic control signal VOUT.
3. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 2, characterized in that: The drain of the high-side power transistor N1 is electrically connected to a voltage VM, which is the power supply voltage of the power transistor. The input of AND gate AND1 is connected to a signal IN1, which is the input control signal for the high-side power transistor. The input of AND gate AND2 is connected to a signal IN2, which is the input control signal for the low-side power transistor. Signals IN1 and IN2 cannot be high simultaneously. When IN1 is high and IN2 is low, the voltage detection circuit outputs VOUT high, AND gate AND2 outputs IN2_LS low, the low-side driver outputs VG_LS low, AND gate AND1 outputs IN1_HS high, and the high-side driver outputs VG_HS high. At this time, the high-side power transistor N1 is turned on, and the low-side power transistor N2 is turned off.
4. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 3, characterized in that: When signal IN1 transitions from high to low, signal IN2 transitions from low to high, and IN1_HS transitions from high to low, the gate control signal VG_HS of the high-side power transistor N1 begins to decrease. Since VG_HS is still relatively high, the output VOUT of the voltage detection circuit remains high. After inverting VOUT, it is ANDed with signal IN2, resulting in the output IN2_LS, which remains low. The low-side power transistor N2 remains off. When the gate control signal VG_HS of the high-side power transistor N1 drops to a very low level, the high-side power transistor N1 turns off, the output VOUT of the voltage detection circuit transitions to low, IN2_LS transitions to high, the gate control signal VG_LS of the low-side power transistor N2 begins to rise, and the low-side power transistor N2 begins to conduct.
5. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 4, characterized in that: When signal IN1 is low and signal IN2 is high, the voltage detection circuit outputs VOUT as low, IN2_LS as high, VG_LS as high, IN1_HS as low, and VG_HS as low. At this time, the high-side power transistor N1 is turned off, and the low-side power transistor N2 is turned on.
6. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 5, characterized in that: When signal IN1 jumps from low to high, signal IN2 jumps from high to low, and signal IN2_LS jumps from high to low, the gate control signal VG_LS of the low-side power transistor N2 begins to decrease. Since VG_LS is still relatively high, it is inverted and ANDed with signal IN1. The output IN1_HS is still low, and the high-side power transistor N1 remains off. When the gate control signal VG_LS of the low-side power transistor N2 drops to a very low level, the low-side power transistor N2 turns off, and IN1_HS jumps to a high level. The gate control signal VG_HS of the high-side power transistor N1 begins to rise, and the high-side power transistor N1 begins to conduct.
7. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 2, characterized in that: The first input terminal of AND gate AND1 is electrically connected to the output terminal of inverter INV2, the second input terminal of AND gate AND1 is connected to the control signal IN1, the input terminal of inverter INV2 is electrically connected to the output terminal of the low-side drive, and the output terminal of AND gate AND1 is electrically connected to the input terminal of the high-side drive.
8. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 2, characterized in that: The input terminal of the inverter INV1 is electrically connected to the output terminal of the AND gate AND1. The output terminal of the inverter INV1 is electrically connected to the voltage detection circuit. The other end of the voltage detection circuit is electrically connected to the output terminal of the high-side drive. The output terminal of the high-side drive is electrically connected to the gate of the high-side power transistor N1.
9. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 2, characterized in that: The first input terminal of AND gate AND2 is electrically connected to the output terminal of inverter INV3. The second input terminal of AND gate AND2 is connected to the control signal IN2. The output terminal of the voltage detection circuit is electrically connected to the input terminal of inverter INV3. The output terminal of AND gate AND2 is electrically connected to the input terminal of the low-side drive. The output terminal of the low-side drive is electrically connected to the gate of the low-side power transistor N2. The source of the low-side power transistor N2 is electrically grounded. The drain of the low-side power transistor N2 is electrically connected to the source of the high-side power transistor N1.
10. A voltage detection circuit for adaptive dead-time control of a motor drive according to claim 1, characterized in that: The power supply voltage VDD is a low-voltage logic power supply, which is 3.3V or 5V. The bias currents I1, I2 and I3 are all in the nA range.