Frame synchronization method, logic module and video processing device

Abstract

The present application is applicable to the field of display control technology, and provides a frame synchronization method, a logic module, and a video processing device. The frame synchronization method includes: the logic module obtains the current reference frequency; the logic module generates the current output frequency based on the current pixel clock; the logic module determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency. In the above-mentioned process of implementing frame synchronization, obtaining the current reference frequency, generating the current output frequency based on the current pixel clock, and determining the target pixel clock frequency are all performed by the same logic module. The target pixel clock frequency is used to adjust the current pixel clock, which can improve the accuracy of the pixel clock, avoid error accumulation, and improve the performance of frame synchronization.

Description

Technical Field

[0001] The present application belongs to the field of display control technology, and in particular, relates to a frame synchronization method, a logic module and a video processing device. Background Art

[0002] Video output genlock is a synchronization technology used to control the timing parameters of the device's output video signal so that it is synchronized with an external reference signal, thereby achieving the purpose of synchronizing the output video signal with the reference signal. It is usually used in video post-processing, non-linear editing, and studios.

[0003] FrameLock, also known as frame-level synchronization, is a method in Genlock that controls the frame rate of the output video signal of the video processing device to be synchronized with the frame rate of the external reference signal, thereby ensuring effective collaboration between various devices in the studio (cameras, recorders, animations, subtitle machines, etc.).

[0004] In order to achieve frame synchronization, the related technology uses the frame rate of the external reference signal to directly generate the pixel clock. Due to the precision error in the generation of the pixel clock, the frame rate of the output video signal and the frame rate of the external reference signal are not strictly the same. The long-term accumulation of errors can easily cause the output video signal to lose lock with the reference signal. Summary of the invention

[0005] The main purpose of the present application is to provide a frame synchronization method, a logic module and a video processing device to improve the performance of frame synchronization.

[0006] In a first aspect, an embodiment of the present application provides a frame synchronization method, including:

[0007] The logic module obtains the current reference frequency, where the reference frequency includes the frequency of the reference field synchronization signal;

[0008] The logic module generates a current output frequency based on a current pixel clock, and the output frequency includes a frequency of an output field synchronization signal;

[0009] The logic module determines a target pixel clock frequency according to a phase difference between a current reference frequency and an output frequency, and the target pixel clock frequency is used to adjust a current pixel clock.

[0010] The frame synchronization method provided in the first aspect obtains the current reference frequency through a logic module, generates the current output frequency based on the current pixel clock, and then determines the target pixel clock frequency based on the phase difference between the current reference frequency and the output frequency, and the target pixel clock frequency is used to adjust the current pixel clock. In this embodiment, obtaining the current reference frequency, generating the current output frequency based on the current pixel clock, and determining the target pixel clock frequency are all performed by the same logic module, and the determined target pixel clock frequency is used to adjust the current pixel clock, which can improve the accuracy of the pixel clock, avoid the accumulation of errors, and improve the effect and accuracy of frame synchronization, that is, improve the performance of frame synchronization.

[0011] Optionally, in some possible implementations, the logic module determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency, and then further includes:

[0012] The logic module triggers the clock chip to adjust the current pixel clock based on the target pixel clock frequency.

[0013] Optionally, in some possible implementations, when the clock chip is triggered to generate a pixel clock for the first time or a signal output parameter is updated, a pixel clock frequency is generated by a logic module, and the clock chip is triggered to generate a pixel clock based on the generated pixel clock frequency, wherein the signal output parameters include resolution and / or refresh rate.

[0014] Optionally, in some possible implementations, when the clock chip is triggered to generate a pixel clock for the first time or a signal output parameter is updated, the logic module obtains the pixel clock frequency from the control module and triggers the clock chip to generate a pixel clock based on the obtained pixel clock frequency, wherein the signal output parameters include resolution and / or refresh rate.

[0015] Optionally, in some possible implementations, the logic module and the control module are two independent chips;

[0016] Alternatively, the logic module and the control module are two modules integrated in the same chip.

[0017] Optionally, in some possible implementations, the logic module determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency, including:

[0018] determining a phase adjustment value based on a proportional-integral-derivative controller and a phase difference;

[0019] The current pixel clock frequency is adjusted based on the phase adjustment value to obtain a target pixel clock frequency.

[0020] Optionally, in some possible implementations, adjusting the current pixel clock frequency based on the phase adjustment value includes:

[0021] Determine the percentage of the phase adjustment value in M ​​frame periods, where M is a positive integer;

[0022] Adjust the current pixel clock frequency by a percentage.

[0023] Optionally, in some possible implementations, the logic module determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency, including:

[0024] When the absolute value of the phase difference is greater than a preset threshold and the reference frequency is greater than the output frequency, the logic module increases the current pixel clock frequency based on the absolute value to obtain a target pixel clock frequency; or,

[0025] When the absolute value of the phase difference is greater than a preset threshold and the reference frequency is less than the output frequency, the logic module reduces the current pixel clock frequency based on the absolute value to obtain a target pixel clock frequency; or,

[0026] When the absolute value of the phase difference is less than or equal to the preset threshold, the logic module determines the current pixel clock frequency as the target pixel clock frequency.

[0027] In a second aspect, an embodiment of the present application provides a logic module, including:

[0028] A phase detection unit, used to obtain a current reference frequency, where the reference frequency includes a frequency of a reference field synchronization signal;

[0029] A generating unit, configured to generate a current output frequency based on a current pixel clock, wherein the output frequency includes a frequency of an output field synchronization signal;

[0030] The synchronization control unit is used to determine a target pixel clock frequency according to a phase difference between a current reference frequency and an output frequency, and the target pixel clock frequency is used to adjust a current pixel clock.

[0031] In a third aspect, an embodiment of the present application provides a video processing device, including: a processor and a memory, the processor and the memory are coupled, the memory stores program instructions, and when the program instructions stored in the memory are executed by the processor, the frame synchronization method provided in the first aspect is executed.

[0032] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored. The computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes the frame synchronization method provided in the first aspect.

[0033] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a video processing device, the video processing device executes the frame synchronization method provided in the first aspect above.

[0034] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 This is a schematic diagram of a signal synchronization scenario provided by this application;

[0037] Figure 2 This is another schematic diagram of a signal synchronization scenario provided by the present application;

[0038] Figure 3 It is a timing diagram of synchronization of an output signal and a reference signal provided by the present application;

[0039] Figure 4 This is a schematic diagram of a frame synchronization implementation method provided by the present application;

[0040] Figure 5 This is a flow chart for implementing frame synchronization provided by the present application;

[0041] Figure 6 is a schematic flow chart of a frame synchronization method provided by an exemplary embodiment of the present application;

[0042] Figure 7 It is a schematic diagram of a logic module provided by an embodiment of the present application;

[0043] Figure 8 It is a schematic diagram of a video processing device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0044] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0045] In addition, the embodiments described in the present application are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0046] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features. It should also be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In the description of the present application, it should also be noted that the terms "first", "second", "third", etc. are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0047] In order to better understand the embodiments of the present application, the terms or concepts that may be involved in the embodiments are introduced below.

[0048] 1. Field Programmable Gate Array (FPGA);

[0049] FPGA is a product further developed on the basis of programmable devices such as programmable array logic and general array logic. As a semi-custom circuit in the field of application-specific integrated circuits, it not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0050] 2. Micro Controller Unit (MCU);

[0051] MCU, also known as Single Chip Microcomputer, is a chip-level computer that appropriately reduces the frequency and specifications of the Central Process Unit (CPU) and integrates memory, timer, Universal Serial Bus (USB), analog-to-digital converter and other peripheral interfaces, and even drive circuits on a single chip to provide different combination controls for different applications.

[0052] 3. Video output phase lock (Genlock);

[0053] Genlock is a synchronization technology used to control the timing parameters of the output video signal of the video processing equipment to synchronize it with the external reference signal, thereby achieving the purpose of synchronizing the output video signal with the reference signal. It is usually used in video post-processing, non-linear editing, and studio scenes.

[0054] For example, when multiple video processing devices (such as video splicers) work together to splice a large video screen, it is necessary to ensure that the video signals output by each video processing device are synchronized with the reference signal.

[0055] 4. Frame synchronization (FrameLock);

[0056] FrameLock, also known as frame-level synchronization, is a method in Genlock that controls the frame rate of the output video signal of the video processing device to be synchronized with the frame rate of the external reference signal, thereby ensuring effective collaboration between various devices in the studio (cameras, recorders, animations, subtitle machines, etc.).

[0057] 5.ARM;

[0058] ARM refers to Advanced Reduced Instruction Set Computer Machines (ARM).

[0059] 6. Field synchronization signal (VSYNC, VS);

[0060] The function of VS is to select the effective field signal interval on the display panel.

[0061] 7. Proportional Integral Differentiation (PID) controller;

[0062] PID forms the control deviation based on the given value and the actual output value. It is a control algorithm with simple algorithm, good robustness and high reliability.

[0063] As an example, see Figure 1 , Figure 1 This is a schematic diagram of a signal synchronization scenario provided by this application. Figure 1 As shown, the video source is used to provide a reference signal, and the display screen is used to display the spliced ​​video images. Video processing device 1, video processing device 2 and video processing device 3 work together to splice a large video image for display on the display screen.

[0064] Among them, the video processing device 1 and the video processing device 2 have the Genlock function turned on to synchronize the output video signal with the reference signal. Therefore, the edges of the spliced ​​video images displayed on the display screen by the video processing device 1 and the video processing device 2 are seamlessly connected. The video processing device 3 does not have the Genlock function turned on, so that the video signal it outputs fails to synchronize with the reference signal, resulting in tearing at the edges of the spliced ​​video images displayed on the display screen. That is, the video processing device 3 does not use the Genlock function, resulting in its output image being out of sync with the output images of other video processing devices.

[0065] As another example, see Figure 2 , Figure 2 This is another signal synchronization scenario diagram provided by this application. Figure 2 As shown in the figure, in a studio scene, when the camera is shooting a scene containing a display screen, it is necessary to ensure that the camera video sampling is synchronized with the output image refresh on the display screen, otherwise the image captured by the camera on the display screen will have rolling stripes. In order to solve this problem, the Genlock function needs to be enabled in the video processing device. For example, the video processing device enables the Genlock function to synchronize the output video signal with the camera reference signal, thereby avoiding rolling stripes in the image captured by the camera on the display screen.

[0066] The above two examples fully illustrate that the Genlock function is very important for video processing devices. In order to achieve Genlock between video processing devices, frame synchronization can be used. For example, the frequency of the field synchronization signal (Vertical Sync, VS) of the reference video is measured (that is, the frequency of the reference field synchronization signal, hereinafter described as "the frequency of the reference VS"), the pixel clock frequency is determined according to the frequency of the reference VS, and then the pixel clock is generated according to the pixel clock frequency; since the field synchronization signal of the output video signal (hereinafter described as "output VS") is related to the pixel clock, the pixel clock frequency used to generate the pixel clock is determined based on the reference VS, so that the output VS can be basically the same frequency as the reference VS.

[0067] See also Figure 3 , Figure 3 This is a timing diagram of synchronization between output VS and reference VS provided by the present application, which shows the ideal state between output VS, output HS (i.e., the line synchronization signal of the output video signal) and reference VS under frame synchronization. For example, the rising edge of output VS is consistent with that of reference VS, or the falling edge of output VS is consistent with that of reference VS, or both the rising edge and the falling edge of output VS are consistent with that of reference VS.

[0068] As mentioned above, determining the pixel clock frequency according to the frequency of the reference VS can be implemented based on the following formula (1):

[0069] F PCLK =F VS(ref) *Htotal*VTotal, (1)

[0070] In the above formula (1), F PCLK Indicates the pixel clock frequency, F VS(ref) Represents the frequency of reference VS, Htotal represents the pixels in the horizontal direction, and VTotal represents the pixels in the vertical direction.

[0071] In the process of achieving frame synchronization, there will be errors when measuring the frequency of the reference VS, and the pixel clock generated by the clock generator (such as the clock chip) will also have accuracy errors. Due to the existence of these errors, the actual output VS and the reference VS are not strictly synchronized. The accumulated errors over a long period of time can easily cause the output VS to lose lock with the reference VS.

[0072] Therefore, during the frame synchronization process, F PCLK Real-time fine-tuning is performed to eliminate accumulated errors and ensure that there is no loss of lock between the output VS and the reference VS.

[0073] In the related technology, MCU and FPGA are used to realize F PCLK As an example, see Figure 4 , Figure 4 This is a schematic diagram of a frame synchronization implementation method provided by this application. Figure 4 The devices shown in the figure include FPGA, MCU and clock chip. FPGA includes generation module and phase detection module, and MCU includes frequency control module and synchronization control module.

[0074] Among them, the phase detection module detects the reference VS ( Figure 4The MCU calculates the pixel clock frequency according to the current resolution, and uses the chip configuration bus (Inter-Integrated Circuit, IIC) to configure the clock chip according to the pixel clock frequency, so that the clock chip generates the corresponding pixel clock.

[0075] After the FPGA obtains a stable pixel clock from the clock chip, it uses the generation module to generate a frame synchronization signal ( Figure 4 The phase difference between RefVs and GenVs is calculated by the phase detection module, and the phase difference is fed back to the MCU by interruption. The synchronization control module in the MCU calculates the pixel clock frequency of the next clock chip according to the phase difference, and then sends the pixel clock frequency of the next clock chip to the clock chip through the frequency control module, so that the clock chip adjusts the output of the pixel clock.

[0076] Since there will be errors when measuring the period of RefVs and there will be precision errors when configuring the clock chip, there will be small errors between RefVs and GenVs, and they cannot be exactly the same. Therefore, the clock chip cannot be configured only once, and the phase difference between RefVs and GenVs needs to be monitored in real time. The above process must be repeated to ensure that the phase difference between the period of RefVs and the period of GenVs is always within a small range, so as to achieve the purpose of synchronization between RefVs and GenVs.

[0077] For easier understanding, see Figure 5 , Figure 5 This is a flowchart for implementing frame synchronization provided by this application. Figure 5 As shown in the figure, the video processing device turns on the Genlock function, the FPGA obtains the cycle of RefVs, the MCU calculates the pixel clock frequency according to the current resolution, and configures the clock chip. The FPGA obtains a stable pixel clock frequency, turns on the FPGA phase detection, and calculates the phase difference between RefVs and GenVs. The FPGA feeds back the phase difference to the MCU through an interrupt. After receiving the interrupt, the MCU reads the phase difference and calculates the pixel clock frequency of the next clock chip based on the phase difference.

[0078] The fluctuation range of the RefVs cycle is preset. If the fluctuation of the RefVs cycle is greater than the preset value (such as 30%) determined by the phase difference, the automatic adjustment algorithm is executed to configure the clock frequency of the clock chip according to the pixel clock frequency of the next clock chip calculated. If the fluctuation of the RefVs cycle is less than or equal to the preset value determined by the phase difference, the FPGA is returned to the step of obtaining the RefVs cycle to continue the above process. After configuring the clock frequency of the clock chip, it is equivalent to the end of one adjustment, and the next interrupt is waited for.

[0079] In the above frame synchronization implementation, the generation of the GenVs cycle, phase detection, etc. are implemented in the FPGA, while the algorithm implementation that requires more operations (such as calculating the pixel clock frequency of the next clock chip based on the phase difference) and frequency control are implemented in the MCU. In other words, in this frame synchronization implementation, the MCU is required to cooperate in reading the phase difference in real time, and calculate the pixel clock frequency of the next clock chip based on the phase difference, and then configure the clock chip according to the pixel clock frequency of the next clock chip.

[0080] Due to the MCU device itself, it often does not respond in time when reading the phase difference and configuring the clock chip in real time, and the processing frequency is relatively slow, resulting in poor frame synchronization, long time consumption, and poor accuracy. For example, the FPGA can calculate the phase difference between RefVs and GenVs of each frame of the image in real time, and feed back each phase difference to the MCU in real time, but due to the device itself, the MCU cannot respond in time to each phase difference fed back by the FPGA in real time, and may respond only once after several or more than a dozen phase differences, which leads to the following problems when implementing GenLock.

[0081] On the one hand, the process from enabling the GenLock function to achieving the synchronous lock state takes a long time. For example, GenVs is generated based on the pixel clock, and the MCU cannot adjust the pixel clock frequency of the clock chip in time according to the phase difference fed back by the FPGA in real time, which results in a longer time to achieve synchronization between RefVs and GenVs.

[0082] On the other hand, after RefVs and GenVs reach the synchronous lock state, GenVs fluctuates widely around RefVs. For example, the MCU may calculate the pixel clock frequency once after several or dozens of phase differences, and the cycle of GenVs gets a chance to adjust once, resulting in RefVs sometimes being greater than the cycle of RefVs, and sometimes being less than the cycle of RefVs, with a large fluctuation range.

[0083] In view of the above problems, an embodiment of the present application provides a frame synchronization method, which obtains the current reference frequency through a logic module, generates the current output frequency based on the current pixel clock, and then determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency, and the target pixel clock frequency is used to adjust the current pixel clock. In this embodiment, obtaining the current reference frequency, generating the current output frequency based on the current pixel clock, and determining the target pixel clock frequency are all performed by the same logic module, and then adjusting the current pixel clock based on the target pixel clock frequency, thereby improving the accuracy of the pixel clock, avoiding the occurrence of error accumulation, and ensuring that the output field synchronization signal and the reference field synchronization signal are strictly the same frequency, so that the reference field synchronization signal and the output field synchronization signal are always in a synchronous locking state, thereby improving the performance of frame synchronization, and improving the effect and accuracy of frame synchronization.

[0084] The frame synchronization method provided in the embodiments of the present application is described in detail below in conjunction with the drawings in the specification.

[0085] See also Figure 6 , Figure 6 FIG. 1 is a schematic flow chart of a frame synchronization method provided by an exemplary embodiment of the present application. Figure 6 The frame synchronization method shown may include: S101-S103, which are specifically as follows:

[0086] S101: The logic module obtains the current reference frequency.

[0087] The reference frequency includes the frequency of the reference field synchronization signal.

[0088] Exemplarily, as a possible implementation manner, the logic module in the embodiment of the present application may be an independent chip, for example, the logic module may be an FPGA chip.

[0089] Optionally, as a possible implementation, the logic module in the embodiment of the present application may be a module integrated on a chip. For example, the logic module and the control module may be integrated on the same chip. The chip may be a multi-processor system on a chip (MPSoC).

[0090] It is worth mentioning that the logic module integrated on the MPSoC has the function of an FPGA chip, and the control module integrated on the MPSoC has the function of an MCU chip.

[0091] In this embodiment, the logic module is an FPGA chip as an example for description. Optionally, as a possible implementation, the FPGA chip is set in a video processing device, the GenLock function of the video processing device is turned on, and the FPGA chip automatically detects the frequency of the reference field synchronization signal.

[0092] For example, the FPGA chip may include a phase detection unit, and the video processing device is provided with an option to turn on or off the GenLock function. The user touches the option to turn on the GenLock function, thereby triggering the GenLock function of the video processing device to turn on. When the GenLock function is turned on, the phase detection unit in the FPGA chip automatically detects the frequency of the reference field synchronization signal. This is only an exemplary description and is not limited to this.

[0093] S102: The logic module generates a current output frequency based on the current pixel clock.

[0094] By way of example, in this embodiment, the logic module is an FPGA chip as an example for explanation. The FPGA chip may also include a generation unit, which generates a current output frequency using a current pixel clock. The output frequency includes the frequency of an output field synchronization signal. By way of example, the generation unit in the FPGA chip generates the frequency of the output field synchronization signal based on the timing parameters of the pixel clock and the video signal.

[0095] Optionally, as a possible implementation, when the clock chip is triggered to generate a pixel clock for the first time or a signal output parameter is updated, a pixel clock frequency is generated by a logic module, and the clock chip is triggered to generate a pixel clock based on the generated pixel clock frequency.

[0096] The signal output parameters may include resolution and / or refresh rate, and the signal output parameters are also factors that affect the pixel clock frequency.

[0097] Exemplarily, a control pin is provided on the clock chip, and the control pin of the clock chip is pre-connected to the FPGA chip. When the clock chip is triggered to generate a pixel clock for the first time, the FPGA chip generates a pixel clock frequency, and sends the generated pixel clock frequency to the clock chip through the control pin, so that the clock chip generates a corresponding pixel clock. Or, when the resolution and / or refresh rate is updated, the FPGA chip regenerates the pixel clock frequency, and sends the generated pixel clock frequency to the clock chip through the control pin, so that the clock chip generates a corresponding pixel clock.

[0098] It is worth noting that, in this embodiment, when the clock chip is not triggered for the first time to generate the pixel clock, the pixel clock frequency is also generated by the FPGA chip, and the clock chip is triggered to generate the pixel clock based on the generated pixel clock frequency.

[0099] In this implementation, the entire process is handled by the logic module, such as FPGA chip processing or MPSoC processing, which does not need to be connected to MCU, ARM and other chips, saving buses and resources. At the same time, it also does not need to interact with MCU, ARM and other chips, improving processing efficiency.

[0100] Optionally, as a possible implementation method, when the clock chip is triggered to generate a pixel clock for the first time or the signal output parameters are updated, the logic module obtains the pixel clock frequency from the control module and triggers the clock chip to generate a pixel clock based on the obtained pixel clock frequency, wherein the signal output parameters include resolution and / or refresh rate.

[0101] Exemplarily, the control module in the embodiment of the present application may be an independent chip, for example, the control module may be an MCU chip, ARM, etc. The control module in the embodiment of the present application may also be a module integrated on a certain chip. For example, the control module and the logic module may be a PS module and a PL module respectively integrated on an MPSoC chip, that is, the PS module implements the functions of the control module, and the PL module implements the functions of the logic module.

[0102] Exemplarily, when the logic module is an FPGA chip and the control module is an MCU chip, the clock chip is pre-connected to the FPGA chip. When the clock chip is triggered to generate a pixel clock for the first time or a signal output parameter is updated, the MCU chip calculates the first pixel clock frequency according to the resolution and / or refresh rate, and transmits the pixel clock frequency to the clock chip through the FPGA chip, and the clock chip generates a pixel clock based on the first pixel clock frequency obtained.

[0103] It is worth noting that in this embodiment, when the clock chip is not triggered for the first time to generate the pixel clock, the pixel clock frequency is generated by the FPGA chip, and the clock chip is triggered to generate the pixel clock based on the generated pixel clock frequency, without the participation of the MCU chip.

[0104] In this implementation, when the pixel clock frequency is determined for the first time or the output parameters are updated, the MCU chip assists in determining the pixel clock frequency, which can provide a basis and guarantee for the initial implementation of frame synchronization.

[0105] Optionally, as a possible implementation method, when the logic module and the control module are two modules integrated in the same chip, when the clock chip is triggered to generate the pixel clock for the first time or the signal output parameters are updated, the logic module obtains the pixel clock frequency from the control module based on the on-chip connection lines, and triggers the clock chip to generate the pixel clock based on the obtained pixel clock frequency.

[0106] For example, when the clock chip is triggered to generate a pixel clock for the first time or a signal output parameter is updated, the control module calculates the pixel clock frequency based on the resolution and / or refresh rate, the logic module sends the pixel clock frequency calculated by the control module to the clock chip, and the clock chip generates a pixel clock based on the first pixel clock frequency obtained.

[0107] S103: The logic module determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency.

[0108] Exemplarily, in this embodiment, the logic module is an FPGA chip as an example for explanation. The FPGA chip first calculates the phase difference between the reference frequency and the output frequency. Specifically, the FPGA chip may include a phase detection unit, which is used to calculate the phase difference between the reference field synchronization signal and the output field synchronization signal.

[0109] The FPGA chip may also include a synchronization control unit, which can calculate a target pixel clock frequency according to the phase difference. The target pixel clock frequency is used to adjust the current pixel clock, that is, the target pixel clock frequency is used to update the current pixel clock.

[0110] In this implementation, the current reference frequency is obtained through a logic module, the current output frequency is generated based on the current pixel clock, and then the target pixel clock frequency is determined according to the phase difference between the current reference frequency and the output frequency, and the target pixel clock frequency is used to adjust the current pixel clock. In this implementation, obtaining the current reference frequency, generating the current output frequency based on the current pixel clock, and determining the target pixel clock frequency are all performed by the same logic module, and then the current pixel clock is adjusted based on the target pixel clock frequency, thereby improving the accuracy of the pixel clock, avoiding the occurrence of error accumulation, and ensuring that the output field synchronization signal and the reference field synchronization signal are strictly the same frequency, so that the reference field synchronization signal and the output field synchronization signal are always in a synchronous locking state, thereby improving the performance of frame synchronization, and improving the effect and accuracy of frame synchronization.

[0111] As a possible implementation, the frame synchronization method can be applied to a video processing device, that is, the processor of the video processing device can be used as the execution subject of the method. It should be noted that the video processing device can be of various types, for example, it can be a terminal for processing video signals, or it can be a server for executing the function of processing video signals.

[0112] Optionally, in a possible implementation, the above S103 may include: S1031-S1032, which are specifically as follows:

[0113] S1031: Determine a phase adjustment value based on a proportional-integral-derivative controller (ie, a PID controller) and a phase difference.

[0114] S1032: Adjust the current pixel clock frequency based on the phase adjustment value to obtain a target pixel clock frequency.

[0115] Exemplarily, the phase difference between the reference frequency and the output frequency is first input into the PID controller, and the phase adjustment value is output from the PID controller.

[0116] The proportional-integral-differential PID controller includes a proportional unit (P), an integral unit (I) and a differential unit (D), which can form a control deviation according to a given value and an actual output value, and basically maintain variable stability. It is a controller with a simple algorithm, good robustness and high reliability. In this optional embodiment, by adding the control algorithm adopted by the PID controller, the logic module adjusts the pixel clock frequency through the calculation result of the control algorithm, thereby achieving the best locking state of the hardware. By adding the control algorithm of the PID controller, the accuracy of Genlock can be further improved.

[0117] Optionally, when determining the phase adjustment value corresponding to the phase difference through a PID controller, the following method can be used: adjusting the control coefficient of the PID controller, wherein the control coefficient includes: a proportional coefficient, an integral coefficient, and a differential coefficient; determining the phase adjustment value corresponding to the phase difference through the PID controller after adjusting the coefficient. Adjusting the control coefficient of the PID controller can balance the convergence speed and the overshoot amplitude, and obtain the core calculation formula of the algorithm. Determine the phase adjustment value corresponding to the phase difference through the PID controller after adjusting the coefficient, and obtain an accurate phase adjustment value, which provides a basis for obtaining an accurate target pixel clock frequency later.

[0118] As an optional embodiment, when the phase adjustment value corresponding to the phase difference is determined by a proportional integral differential PID controller, the phase adjustment value corresponding to the phase difference may be determined in the following manner:

[0119] incr_phase=KP*fresh_phase+KI*total_phase+KD*(fresh_phase-last_phase).

[0120] Among them, fresh_phase is the phase difference between the current reference frequency and the output frequency, total_phase is the cumulative sum of fresh_phase within the statistical number of historical pixel clock adjustments, last_phase is the phase difference between the reference frequency and the output frequency when the pixel clock was adjusted last time, incr_phase is the phase adjustment value, KP is the proportional coefficient, KI is the integral coefficient, and KD is the differential coefficient.

[0121] Exemplarily, the current pixel clock frequency is adjusted based on the determined phase adjustment value to obtain the target pixel clock frequency. Optionally, in a possible implementation, the frequency adjustment value can be determined based on the phase adjustment value; and the target pixel clock frequency is obtained based on the frequency adjustment value. It is worth noting that since the phase adjustment value has positive and negative signs, that is, it characterizes whether the output field synchronization signal is ahead or behind the reference field synchronization signal in phase; the frequency adjustment value also has positive and negative signs, that is, the value corresponding to the frequency adjustment value is added or subtracted from the current pixel clock frequency.

[0122] In the above implementation, determining the phase adjustment value based on the PID controller and the phase difference is conducive to obtaining a more accurate phase adjustment value, thereby making the pixel clock frequency obtained based on the phase adjustment value more accurate.

[0123] Optionally, in a possible implementation, adjusting the current pixel clock frequency based on the phase adjustment value may include: determining a percentage of the phase adjustment value in M ​​frame periods, where M is a positive integer; and adjusting the current pixel clock frequency according to the percentage.

[0124] The M frame periods represent the current phase value of the output frequency. It should be noted that the phase adjustment value and the M frame periods mentioned above can be expressed in a unified time unit, for example, both can be expressed in seconds or nanoseconds.

[0125] Exemplarily, the percentage of the phase adjustment value in M ​​frame periods is determined in the following manner.

[0126] incr_freq_percent=incr_phase / gen_vs_T.

[0127] Among them, incr_freq_percent is a percentage, incr_phase is a phase adjustment value, and gen_vs_phase is M frame periods. As mentioned above, the incr_phase and gen_vs_phase can be expressed in time with a unified unit. When the units are not unified, a formula conversion value can be added to the above formula. For example, when the unit of gen_vs_T is seconds and the unit of incr_phase is nanoseconds, gen_vs_T can be multiplied by 10 to the 9th power to obtain the value of gen_vs_T in nanoseconds, and then the percentage is calculated according to the formula.

[0128] Adjusting the current pixel clock frequency according to the percentage and the current pixel clock frequency may be achieved in the following manner: fresh_freq=last_freq*(1+incr_freq_percent), wherein fresh_freq is the adjusted pixel clock frequency, and last_freq is the current pixel clock frequency.

[0129] In the above implementation, the PID controller and phase difference are effectively utilized to determine the phase adjustment value, obtain an accurate phase adjustment value, and then determine the percentage of the phase adjustment value in M ​​frame periods. The current pixel clock frequency is adjusted according to the percentage and the current pixel clock frequency, thereby improving the accuracy of configuring the pixel clock frequency.

[0130] Optionally, in one possible implementation, the logic module determines the target pixel clock frequency based on the phase difference between the current reference frequency and the output frequency, which may include: when the absolute value of the phase difference is greater than a preset threshold and the reference frequency is greater than the output frequency, the logic module increases the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency.

[0131] Exemplarily, the preset threshold is set by the user according to the actual situation, such as the preset threshold can be 0.02, 0.5, 1, etc., which is not limited. The absolute value of the phase difference between the reference frequency and the output frequency is calculated, and the absolute value is compared with the preset threshold. If the absolute value is greater than the preset threshold, it is further determined whether the reference frequency is greater than the output frequency or the reference frequency is less than the output frequency. If the reference frequency is greater than the output frequency, the logic module increases the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency.

[0132] For example, the preset threshold is 1, the reference frequency is 120.00 Hz, the output frequency is 118 Hz, and the absolute value of the phase difference between the reference frequency and the output frequency is 2. Obviously, the absolute value 2 is greater than the preset threshold 1, and it is also determined that the reference frequency is greater than the output frequency, indicating that the current output frequency is less than the reference frequency. The logic module increases the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency. This ensures that the output frequency generated next time is increased, thereby ensuring that the reference frequency is synchronized with the output frequency.

[0133] In this embodiment, when the absolute value of the phase difference is greater than a preset threshold and the reference frequency is greater than the output frequency, the logic module increases the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency, so that when the output frequency is generated next time according to the adjusted pixel clock frequency, the output frequency generated next time is greater than the output frequency of this time, so that the output frequency generated next time is synchronized with the next reference frequency, thereby ensuring that the frame synchronization signal of the reference image and the frame synchronization signal of the output image are always in a synchronous locked state, thereby improving the performance of frame synchronization, shortening the time of frame synchronization, and improving the effect and accuracy of frame synchronization.

[0134] Optionally, in another possible implementation, the logic module determines the target pixel clock frequency based on the phase difference between the current reference frequency and the output frequency, which may include: when the absolute value of the phase difference is greater than a preset threshold and the reference frequency is less than the output frequency, the logic module reduces the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency.

[0135] Exemplarily, the absolute value of the phase difference between the reference frequency and the output frequency is calculated, and the absolute value is compared with a preset threshold. If the absolute value is greater than the preset threshold, it is further determined whether the reference frequency is greater than the output frequency or the reference frequency is less than the output frequency. If the reference frequency is less than the output frequency, the logic module reduces the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency.

[0136] For example, the preset threshold is 1, the reference frequency is 120.00 Hz, the output frequency is 122 Hz, and the absolute value of the phase difference between the reference frequency and the output frequency is 2. Obviously, the absolute value 2 is greater than the preset threshold 1, and it is also determined that the reference frequency is less than the output frequency, indicating that the current output frequency is greater than the reference frequency. Therefore, the next pixel clock frequency needs to be reduced, so as to ensure that the output frequency generated according to the adjusted pixel clock frequency is reduced next time, thereby ensuring the synchronization of the reference frequency and the output frequency.

[0137] In this embodiment, when the absolute value of the phase difference is greater than a preset threshold and the reference frequency is less than the output frequency, the logic module reduces the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency, so that when the output frequency is generated next time according to the adjusted pixel clock frequency, the output frequency generated next time is made lower than the output frequency of this time, so that the output frequency generated next time is synchronized with the next reference frequency, thereby ensuring that the frame synchronization signal of the reference image and the frame synchronization signal of the output image are always in a synchronous locked state, thereby improving the performance of frame synchronization, shortening the time of frame synchronization, and improving the effect and accuracy of frame synchronization.

[0138] Optionally, in another possible implementation, the logic module determines the target pixel clock frequency based on the phase difference between the current reference frequency and the output frequency, which may include: when the absolute value of the phase difference is less than or equal to a preset threshold, the logic module determines the current pixel clock frequency as the target pixel clock frequency.

[0139] Exemplarily, the absolute value of the phase difference between the reference frequency and the output frequency is calculated, and the absolute value is compared with a preset threshold value. If the absolute value is less than or equal to the preset threshold value, the logic module determines the current pixel clock frequency as the target pixel clock frequency.

[0140] For example, the preset threshold is 0.02, the reference frequency is 120.00 Hz, the output frequency is 120.01 Hz, and the absolute value of the phase difference between the reference frequency and the output frequency is 0.01. Obviously, the absolute value 0.01 is less than the preset threshold 0.02, indicating that the current output frequency is substantially the same as the reference frequency, and therefore, the current pixel clock frequency can be maintained, thus ensuring that the output frequency generated next time according to the adjusted pixel clock frequency is the same as the current output frequency, thereby ensuring that the reference frequency is synchronized with the output frequency.

[0141] For another example, the preset threshold is 0.02, the reference frequency is 120.00 Hz, the output frequency is 120.02 Hz, and the absolute value of the phase difference between the reference frequency and the output frequency is 0.02. Obviously, the absolute value 0.02 is equal to the preset threshold 0.02, indicating that the current output frequency is substantially the same as the reference frequency, and therefore, the current pixel clock frequency can be maintained, thus ensuring that the output frequency generated next time according to the adjusted pixel clock frequency is the same as the current output frequency, thereby ensuring that the reference frequency is synchronized with the output frequency.

[0142] In this embodiment, when the absolute value of the phase difference is less than or equal to a preset threshold value, the logic module determines the current pixel clock frequency as the target pixel clock frequency, so that when the output frequency is generated next time according to the adjusted pixel clock frequency, the output frequency generated next time is equal to the output frequency of this time, so that the output frequency generated next time is synchronized with the next reference frequency, thereby ensuring that the frame synchronization signal of the reference image and the frame synchronization signal of the output image are always in a synchronous locked state, thereby improving the performance of frame synchronization, shortening the time of frame synchronization, and improving the effect and accuracy of frame synchronization.

[0143] Optionally, in a possible implementation manner, after the above S103, the method may further include: a logic module triggering a clock chip to adjust a current pixel clock based on a target pixel clock frequency.

[0144] Exemplarily, the logic module generates configuration information according to the target pixel clock frequency; sends the configuration information to the clock chip, wherein the configuration information is used to configure the clock chip, that is, the clock chip generates a pixel clock according to the target pixel clock frequency, thereby adjusting the current pixel clock.

[0145] Optionally, in a possible implementation, the pixel clock may also be generated by a voltage-controlled oscillator (VCO), and the aforementioned clock chip may be replaced by the voltage-controlled oscillator.

[0146] An oscillating current is a current whose magnitude and direction change with the period, and a circuit that can generate an oscillating current is called an oscillating circuit. Optionally, in a possible implementation, the pixel clock can also be generated by a specific oscillating circuit. For example, the magnitude and direction of the oscillating current are adjusted according to actual needs to form a specific oscillating circuit, and then the pixel clock is generated by the specific oscillating circuit. This embodiment does not specifically limit the component that generates the pixel clock.

[0147] In this implementation, the pixel clock can be generated by different devices, which provides more possibilities for device combinations to achieve frame synchronization and also provides more choices for users. For example, a more economical device combination can be selected to achieve frame synchronization, thereby reducing the cost of achieving frame synchronization. Alternatively, a device combination with higher precision can be selected to achieve frame synchronization, thereby improving the accuracy and effect of frame synchronization.

[0148] Figure 6 In the process of realizing frame synchronization, the corresponding embodiment uses the frequency of the reference field synchronization signal and the frequency of the output field synchronization signal. Optionally, in a possible implementation, the frame synchronization method provided by the present application can also be realized by using the period of the reference field synchronization signal and the period of the output field synchronization signal.

[0149] For example, the logic module obtains a reference cycle, which includes the cycle of a reference field synchronization signal; the logic module generates a current output cycle based on the current pixel clock, and the output cycle includes the cycle of an output field synchronization signal; the logic module determines a target pixel clock frequency based on a phase difference between the current reference cycle and the output cycle, and the target pixel clock frequency is used to adjust the current pixel clock.

[0150] For the specific implementation process, please refer to Figure 6 The specific description of the corresponding embodiment is not repeated here. It can be understood that the period is inversely proportional to the frequency, and when the period is adopted, the part of the process of determining the target pixel clock frequency according to the phase difference between the reference period and the output period is opposite to the part of the process of determining the target pixel clock frequency according to the phase difference between the reference frequency and the output frequency.

[0151] For example, when it is determined that the absolute value of the phase difference between the reference period and the output period is greater than a preset threshold, and the reference period is greater than the output period, the logic module reduces the current pixel clock frequency based on the absolute value to obtain a target pixel clock frequency.

[0152] For another example, when it is determined that the absolute value of the phase difference between the reference period and the output period is greater than a preset threshold and the reference period is less than the output period, the logic module increases the current pixel clock frequency based on the absolute value to obtain a target pixel clock frequency.

[0153] For another example, when it is determined that the absolute value of the phase difference between the reference cycle and the output cycle is less than or equal to a preset threshold, the logic module determines the current pixel clock frequency as the target pixel clock frequency.

[0154] In this embodiment, obtaining the current reference period, generating the current output period based on the current pixel clock, and determining the target pixel clock frequency are all performed by the same logic module, and then adjusting the current pixel clock based on the target pixel clock frequency, thereby improving the accuracy of the pixel clock and avoiding error accumulation, ensuring that the output field synchronization signal and the reference field synchronization signal are strictly in the same frequency, so that the reference field synchronization signal and the output field synchronization signal are always in a synchronous locked state, thereby improving the performance of frame synchronization and improving the effect and accuracy of frame synchronization.

[0155] See also Figure 7 , Figure 7 Schematic diagram of a logic module provided by an embodiment of the present application. Figure 7 As shown, the logic module may include:

[0156] The phase detection unit 210 is used to obtain a current reference frequency, where the reference frequency includes a frequency of a reference field synchronization signal;

[0157] A generating unit 220, configured to generate a current output frequency based on a current pixel clock, wherein the output frequency includes a frequency of an output field synchronization signal;

[0158] The synchronization control unit 230 is used to determine a target pixel clock frequency according to a phase difference between a current reference frequency and an output frequency, and the target pixel clock frequency is used to adjust a current pixel clock.

[0159] Optionally, the logic module may further include:

[0160] The adjustment unit is used to trigger the clock chip to adjust the current pixel clock based on the target pixel clock frequency.

[0161] Optionally, the logic module may also include: a first pixel clock frequency processing unit (not shown in the figure), used to: generate a pixel clock frequency when the above-mentioned clock chip is triggered to generate a pixel clock for the first time or the signal output parameters are updated, and trigger the above-mentioned clock chip to generate a pixel clock based on the generated pixel clock frequency, wherein the above-mentioned signal output parameters include resolution and / or refresh rate.

[0162] Alternatively, optionally, the logic module may also include: a second pixel clock frequency processing unit (not shown in the figure), which is used to obtain the pixel clock frequency from the control module and trigger the clock chip to generate the pixel clock based on the obtained pixel clock frequency when the above-mentioned clock chip is triggered to generate the pixel clock for the first time or the signal output parameters are updated, wherein the above-mentioned signal output parameters include resolution and / or refresh rate.

[0163] Furthermore, the logic module and the control module are two independent chips respectively; or, the logic module and the control module are two modules integrated into the same chip respectively.

[0164] Optionally, the synchronization control unit 230 is further configured to: determine a phase adjustment value based on a proportional-integral-differential controller and the phase difference; and adjust a current pixel clock frequency based on the phase adjustment value to obtain a target pixel clock frequency.

[0165] Optionally, the synchronization control unit 230 is further used to: determine the percentage of the phase adjustment value in M ​​frame periods, where M is a positive integer; and adjust the current pixel clock frequency according to the percentage.

[0166] Optionally, the synchronization control unit 230 is further configured to: when the absolute value of the phase difference is greater than a preset threshold and the upper reference frequency is greater than the output frequency, increase the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency; or,

[0167] When the absolute value of the phase difference is greater than the preset threshold and the reference frequency is less than the output frequency, the current pixel clock frequency is reduced based on the absolute value to obtain the target pixel clock frequency; or,

[0168] When the absolute value of the phase difference is less than or equal to the preset threshold, the current pixel clock frequency is determined as the target pixel clock frequency.

[0169] See also Figure 8 , Figure 8 1 is a schematic diagram of a video processing device provided by another embodiment of the present application. The video processing device may include: a video processor, a video switcher or a video splicer, etc., which are used for video processing or control.

[0170] Specifically, Figure 8 As shown, the video processing device 3 of this embodiment includes: a processor 30, a memory 31, and a computer program 32 stored in the memory 31 and executable on the processor 30. When the processor 30 executes the computer program 32, the steps in the above-mentioned frame synchronization method embodiments are implemented, for example Figure 1 Alternatively, when the processor 30 executes the computer program 32, the functions of the modules in the above embodiments are realized, for example, Figure 7 The functions of units 210 to 230 are shown.

[0171] Exemplarily, the computer program 32 may be divided into one or more units, which are stored in the memory 31 and executed by the processor 30 to complete the present application. The one or more units may be a series of computer instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program 32 in the video processing device 3. For example, the computer program 32 may be divided into a phase detection unit, a generation unit, and a synchronization control unit, and the specific functions of each unit are as described above.

[0172] The video processing device 3 may include, but is not limited to, a processor 30 and a memory 31. It may also include more or fewer components, or a combination of certain components, or different components. For example, the video processing device 3 may also include input and output devices, network access devices, buses, etc.

[0173] The processor 30 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0174] The memory 31 may be an internal storage unit of the video processing device 3, such as a hard disk or memory of the video processing device 3. The memory 31 may also be an external storage terminal of the video processing device 3, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the video processing device 3. Further, the memory 31 may also include both an internal storage unit and an external storage terminal of the video processing device 3. The memory 31 is used to store the computer instructions and other programs and data required by the terminal. The memory 31 may also be used to temporarily store data that has been output or is to be output.

[0175] The embodiment of the present application further provides a computer storage medium, which may be non-volatile or volatile. The computer storage medium stores a computer program, which, when executed by a processor, implements the steps in the above-mentioned frame synchronization method embodiments.

[0176] The present application also provides a computer program product. When the computer program product runs on a video processing device, the video processing device executes the steps in the above-mentioned frame synchronization method embodiments.

[0177] An embodiment of the present application also provides a chip or integrated circuit, which includes: a processor, which is used to call and run a computer program from a memory, so that a device equipped with the chip or integrated circuit executes the steps in the above-mentioned frame synchronization method embodiments.

[0178] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0179] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0180] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0181] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A frame synchronization method, characterized in that: include: The logic module acquires a current reference frequency, wherein the reference frequency includes a frequency of a reference field synchronization signal; The logic module generates a current output frequency based on a current pixel clock, wherein the output frequency includes a frequency of an output field synchronization signal; The logic module determines a target pixel clock frequency according to a phase difference between a current reference frequency and an output frequency, and the target pixel clock frequency is used to adjust a current pixel clock; The logic module determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency, and then further includes: The logic module triggers the clock chip to adjust the current pixel clock based on the target pixel clock frequency; The method further comprises: When it is not the first time that the clock chip is triggered to generate a pixel clock or a signal output parameter is updated, the logic module generates a pixel clock frequency, and triggers the clock chip to generate a pixel clock based on the generated pixel clock frequency, wherein the signal output parameter includes a resolution and / or a refresh rate; When the clock chip is triggered to generate a pixel clock for the first time or the signal output parameters are updated, the control module generates a pixel clock frequency, and the logic module obtains the pixel clock frequency from the control module, and triggers the clock chip to generate a pixel clock based on the obtained pixel clock frequency, wherein the signal output parameters include resolution and / or refresh rate.

2. The frame synchronization method according to claim 1, characterized in that: The logic module and the control module are two independent chips respectively; Alternatively, the logic module and the control module are two modules integrated into the same chip.

3. The frame synchronization method according to claim 1 or 2, characterized in that: The logic module determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency, including: determining a phase adjustment value based on a proportional-integral-derivative controller and the phase difference; The current pixel clock frequency is adjusted based on the phase adjustment value to obtain a target pixel clock frequency.

4. The frame synchronization method according to claim 3, characterized in that: The adjusting the current pixel clock frequency based on the phase adjustment value comprises: Determine the percentage of the phase adjustment value in M ​​frame periods, where M is a positive integer; The current pixel clock frequency is adjusted according to the percentage.

5. The frame synchronization method according to claim 1 or 2, characterized in that: The logic module determines the target pixel clock frequency according to the phase difference between the current reference frequency and the output frequency, including: When the absolute value of the phase difference is greater than a preset threshold and the reference frequency is greater than the output frequency, the logic module increases the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency; or, When the absolute value of the phase difference is greater than the preset threshold and the reference frequency is less than the output frequency, the logic module reduces the current pixel clock frequency based on the absolute value to obtain the target pixel clock frequency; or, When the absolute value of the phase difference is less than or equal to the preset threshold, the logic module determines the current pixel clock frequency as the target pixel clock frequency.

6. A logic module, characterized in that: include: A phase detection unit, used to obtain a current reference frequency, wherein the reference frequency includes a frequency of a reference field synchronization signal; A generating unit, configured to generate a current output frequency based on a current pixel clock, wherein the output frequency includes a frequency of an output field synchronization signal; A synchronization control unit, used to determine a target pixel clock frequency according to a phase difference between a current reference frequency and an output frequency, wherein the target pixel clock frequency is used to adjust a current pixel clock; An adjustment unit, used for triggering the clock chip to adjust the current pixel clock based on the target pixel clock frequency; a first pixel clock frequency processing unit, configured to generate a pixel clock frequency by the logic module and trigger the clock chip to generate a pixel clock based on the generated pixel clock frequency when the clock chip is not triggered to generate a pixel clock for the first time or a signal output parameter is updated, wherein the signal output parameter includes a resolution and / or a refresh rate; A second pixel clock frequency processing unit is used to generate a pixel clock frequency by the control module when the clock chip is triggered to generate a pixel clock for the first time or a signal output parameter is updated, and the logic module obtains the pixel clock frequency from the control module and triggers the clock chip to generate a pixel clock based on the obtained pixel clock frequency, wherein the signal output parameters include resolution and / or refresh rate.

7. A video processing device, characterized in that: include: A processor and a memory, wherein the processor and the memory are coupled, the memory stores program instructions, and when the program instructions stored in the memory are executed by the processor, the method according to any one of claims 1 to 5 is executed.

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