Optical detection devices and electronic equipment

Abstract

This invention relates to a light detection device and an electronic device. The light detection device may include: a pixel configured to generate a pixel signal; and a comparator including: a first capacitor configured to receive the pixel signal; a second capacitor configured to receive a reference signal; a first node connected to the first and second capacitors; a first transistor having a gate connected to the first node; and a second transistor located between the first transistor and a first line provided with a first voltage, wherein the first transistor is located between the second transistor and a second line provided with a second voltage, the second voltage being different from the first voltage; wherein the first and second transistors have opposite polarities; wherein the gate of the second transistor is configured to receive a bias voltage; and wherein a first output signal is configured to be output from a second node between the first and second transistors.

Description

[0001] This application is a divisional application of patent application No. 201880011592.3, filed on February 19, 2018, entitled "Image Sensor, Method for Controlling Image Sensor and Electronic Device". Technical Field

[0002] This invention relates to image sensors, methods for controlling image sensors, and electronic devices, and more particularly to image sensors with reduced power consumption, methods for controlling image sensors, and electronic devices. Background Technology

[0003] In related technologies, there exists a CMOS image sensor that performs analog-to-digital (AD) conversion on a pixel signal by having a comparator compare an analog pixel signal with a reference signal having a linearly decreasing ramp waveform, and timing until the reference signal becomes smaller than the pixel signal (see, for example, Patent Document 1).

[0004] Reference List

[0005] Patent documents

[0006] [Patent Document 1]

[0007] JP 2009-124513A Summary of the Invention

[0008] Technical issues

[0009] Some traditional analog-to-digital converters (ADCs) used in image sensors suffer from high power consumption, a significant portion of which can be attributed to the ADC's comparator. Other types of ADCs used in image sensors exhibit the problem that the ADC's comparator introduces unwanted distortion into the output signal. Among other possible factors, this distortion can be attributed to artifacts that appear in the comparator's signal when performing an inversion operation.

[0010] Some embodiments of the invention are made in view of this situation and are adapted to reduce power consumption. Other embodiments of the invention are made in view of this situation and are adapted to reduce the formation of unwanted artifacts in the comparator signal when performing an inversion operation.

[0011] Solutions to technical problems

[0012] According to a first embodiment of the present invention, an imaging device is provided, comprising a pixel and a comparator, the pixel being configured to generate a pixel signal. The comparator comprises: a first capacitor configured to receive the pixel signal; a second capacitor configured to receive a reference signal; a node connected to the first capacitor and the second capacitor; a first transistor having a gate connected to the node; a second transistor connected to the first capacitor; and a third capacitor connected between the gate of the second transistor and a first line provided with a first voltage.

[0013] According to a second embodiment of the present invention, an imaging device is provided, comprising a pixel and a comparator, the pixel being configured to generate a pixel signal. The comparator comprises: a first capacitor configured to receive the pixel signal; a second capacitor configured to receive a reference signal; a node connected to the first capacitor and the second capacitor; a first transistor having a gate connected to the node; and a second transistor disposed between a first line provided with a first fixed voltage and the first transistor, wherein the first transistor is connected between the second transistor and a second line provided with a second fixed voltage different from the first fixed voltage, and wherein the gate of the second transistor is isolated from the node.

[0014] Beneficial effects of the present invention

[0015] According to the first and second embodiments of the present invention, power consumption can be reduced. According to the second embodiment, the formation of unwanted artifacts in the comparator signal during the inversion operation can be reduced.

[0016] Note that the effects described herein are not limiting and can be any of the desired effects described in this invention. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating an embodiment of an image sensor to which the present invention is applied.

[0018] Figure 2 This is a circuit diagram showing an example of a configuration per unit pixel.

[0019] Figure 3 It is shown Figure 1 Circuit diagram of the first embodiment of the comparator.

[0020] Figure 4 This is a timing diagram used to illustrate the operation of the comparator.

[0021] Figure 5 This is a diagram used to illustrate the operation of a comparator in related technologies.

[0022] Figure 6 It is used for explanation Figure 3 A diagram showing the effect of the comparator.

[0023] Figure 7 It is shown Figure 3 The circuit diagram of the first variant of the comparator shown.

[0024] Figure 8 It is shown Figure 3 The circuit diagram of the second variant of the comparator shown.

[0025] Figure 9 It is shown Figure 3 The circuit diagram of the third variant of the comparator shown is illustrated.

[0026] Figure 10 It is shown Figure 3 The circuit diagram of the fourth variant of the comparator shown is shown.

[0027] Figure 11 It is used for explanation Figure 10 The timing diagram of the comparator operation in the diagram.

[0028] Figure 12 It is shown Figure 3 The circuit diagram of the fifth variant of the comparator shown.

[0029] Figure 13 It is shown Figure 3 The circuit diagram of the sixth variant of the comparator shown.

[0030] Figure 14 It is shown Figure 3 The circuit diagram of the seventh variant of the comparator shown.

[0031] Figure 15 It is shown Figure 3 The circuit diagram of the eighth variant of the comparator shown is shown.

[0032] Figure 16 It is a graph used to illustrate the change of the reference signal input to the differential amplifier according to the input capacitance ratio.

[0033] Figure 17 It is shown Figure 15 The circuit diagram shows a first specific example of the comparator.

[0034] Figure 18 It is shown Figure 15 The circuit diagram shows a second specific example of the comparator.

[0035] Figure 19 It is shown Figure 3 The circuit diagram of the ninth variant of the comparator shown is shown.

[0036] Figure 20 It is shown Figure 1 The circuit diagram shows a second embodiment of the comparator.

[0037] Figure 21 It is used for explanation Figure 20 The timing diagram for the operation of the comparator is shown.

[0038] Figure 22 It is shown Figure 20 The circuit diagram of the first variant of the comparator shown.

[0039] Figure 23 It is shown Figure 20 The circuit diagram of the second variant of the comparator shown.

[0040] Figure 24 It is shown Figure 20 The circuit diagram of the third variant of the comparator shown is illustrated.

[0041] Figure 25 It is shown Figure 20 The circuit diagram of the fourth variant of the comparator shown is shown.

[0042] Figure 26 It is shown Figure 20 The circuit diagram of the fifth variant of the comparator shown.

[0043] Figure 27 It is shown Figure 20 The circuit diagram of the sixth variant of the comparator shown.

[0044] Figure 28 It is used for explanation Figure 27 The timing diagram for the operation of the comparator is shown.

[0045] Figure 29 It is shown Figure 20 The circuit diagram of the seventh variant of the comparator shown.

[0046] Figure 30 It is shown Figure 20 The circuit diagram of the eighth variant of the comparator shown is shown.

[0047] Figure 31 It is shown Figure 30 The circuit diagram shows a first specific example of the comparator.

[0048] Figure 32 It is shown Figure 30 The circuit diagram shows a second specific example of the comparator.

[0049] Figure 33 It is shown Figure 1 The circuit diagram shows a third embodiment of the comparator.

[0050] Figure 34 It is used for explanation Figure 33 The timing diagram for the operation of the comparator is shown.

[0051] Figure 35 It is shown Figure 1 The circuit diagram shows a variation of the third embodiment of the comparator shown.

[0052] Figure 36 It is used for explanation Figure 35 The timing diagram for the operation of the comparator is shown.

[0053] Figure 37 It is used for explanation Figure 35 The timing diagram for the operation of the comparator is shown.

[0054] Figure 38 It is used for explanation Figure 35 The timing diagram for the operation of the comparator is shown.

[0055] Figure 39 An example of the use of an image sensor is shown.

[0056] Figure 40 This is a block diagram illustrating an example configuration of an electronic device.

[0057] Figure 41 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0058] Figure 42 This is an explanatory diagram showing an example of the mounting positions of the vehicle exterior information detection unit and the imaging unit.

[0059] Figure 43 This is a schematic diagram illustrating an example configuration of a stacked solid-state imaging device to which the technology according to embodiments of the present invention can be applied.

[0060] Figure 44 This is a cross-sectional view showing a first configuration example of a stacked solid-state imaging device.

[0061] Figure 45 This is a cross-sectional view showing a second configuration example of a stacked solid-state imaging device.

[0062] Figure 46 This is a cross-sectional view showing a third configuration example of a stacked solid-state imaging device.

[0063] Figure 47 This is a cross-sectional view illustrating another configuration example of a stacked solid-state imaging device to which the technology according to embodiments of the present invention can be applied. Detailed Implementation

[0064] Hereinafter, embodiments for carrying out the present invention (hereinafter referred to as "embodiments") will be described in detail with reference to the accompanying drawings. The description will proceed in the following order.

[0065] 1. First Embodiment (Example of Differential Amplifier Used in Comparator)

[0066] 2. Variations of the first embodiment

[0067] 3. Second Embodiment (Example of a Single-Type Amplifier Used as a Comparator)

[0068] 4. Variations of the second embodiment

[0069] 5. Third embodiment

[0070] 6. Variations of the third embodiment

[0071] 7. Other variations

[0072] 8. Examples of Image Sensor Applications

[0073] <<1. First Embodiment>>

[0074] First, refer to Figures 1 to 6 The first embodiment of the present invention will be described.

[0075] <Image Sensor Configuration Example>

[0076] Figure 1 This is a block diagram illustrating an embodiment of the image sensor 100 to which the present invention is applied.

[0077] The image sensor 100 includes a pixel unit 101, a timing control circuit 102, a vertical scanning circuit 103, a digital-to-analog converter (DAC) 104, an analog-to-digital converter (ADC) group 105, a horizontal transmission scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108.

[0078] Unit pixels (hereinafter also simply referred to as pixels), including photoelectric conversion elements, are arranged in a matrix shape in pixel section 101. These photoelectric conversion elements convert incident light into electrical charge based on light intensity. (See below for further details.) Figure 2 The specific circuit configuration for each pixel is described. Furthermore, in the matrix-shaped pixel arrangement, for each row, the pixel driving line 109 is arranged in the left-right direction (pixel arrangement direction of the pixel row / horizontal direction) as shown in the figure, and for each column, the vertical signal line 110 is arranged in the up-down direction (pixel arrangement direction of the pixel column / vertical direction) as shown in the figure. One end of the pixel driving line 109 is connected to the output terminal corresponding to each row of the vertical scan circuit 103. Although in Figure 1Each pixel row shows one pixel driving line 109, but two or more pixel driving lines 109 can also be set for each pixel row.

[0079] The timing control circuit 102 includes a timing generator (not shown) configured to generate various timing signals. The timing control circuit 102 controls the driving of the vertical scan circuit 103, DAC 104, ADC group 105, horizontal transfer scan circuit 106, etc., based on various timing signals (which are generated by the timing generator based on control signals provided from the outside).

[0080] The vertical scan circuit 103 is formed by a shift register, an address decoder, etc. Although the specific configuration is omitted in the figure here, the vertical scan circuit 103 includes a read scan system and a clear scan system.

[0081] The readout scanning system performs selective scanning sequentially, unit by unit pixel of the signal being read. Simultaneously, for the time of the shutter speed prior to the readout scan, the clear scan system performs a clear scan to remove (reset) unwanted charges originating from the photoelectric conversion elements in the unit pixels of the readout row scanned by the readout scanning system. This process of removing (resetting) unwanted charges by the clear scan system constitutes what is known as electronic shutter operation. Here, electronic shutter operation means discarding the photoelectric charge of the photoelectric conversion elements and restarting exposure (starting the accumulation of photoelectric charge). The signal read by the readout scanning system through the readout operation corresponds to the intensity of light incident after the previous readout operation or the electronic shutter operation. The time interval from the readout moment of the previous readout operation or the clearing moment of the electronic shutter operation to the readout moment of this current readout operation is the photoelectric charge accumulation time (exposure time) in the unit pixel.

[0082] The pixel signal VSL output by each unit pixel in the pixel row selectively scanned by the vertical scanning circuit 103 is provided to the ADC group 105 via the vertical signal line 110 in each column.

[0083] DAC 104 generates a reference signal RAMP and provides the reference signal RAMP to ADC group 105. The reference signal RAMP is a signal with a linearly increasing ramp waveform.

[0084] ADC group 105 includes comparators 121-1 to 121-n, counters 122-1 to 122-n, and latches 123-1 to 123-n. In the following text, unless otherwise specified, comparators 121-1 to 121-n, counters 122-1 to 122-n, and latches 123-1 to 123-n will be simply referred to as comparator 121, counter 122, and latch 123.

[0085] A comparator 121, a counter 122, and a latch 123 are configured and form an ADC for each column of the pixel section 101. That is, an ADC is configured for each column of the pixel section 101 in the ADC group 105.

[0086] Comparator 121 compares the voltage of a signal with a predetermined reference voltage, which is obtained by adding the pixel signal VSL output by each pixel and the reference signal RAMP through a capacitor, and comparator 121 provides an output signal representing the comparison result to counter 122.

[0087] Based on the output signal of comparator 121, counter 122 converts the analog pixel signal into a digital pixel signal represented by a count value through timing. This timing continues until the signal obtained by adding the pixel signal VSL and the reference signal RAMP through a capacitor exceeds a predetermined reference voltage. Counter 122 provides the count value to latch 123.

[0088] Latch 123 holds the count value provided by counter 122. Latch 123 performs correlated double sampling (CDS) by acquiring the difference between the count value of the D phase of the pixel signal corresponding to the signal level and the count value of the P phase of the pixel signal corresponding to the reset level.

[0089] The horizontal transmission scan circuit 106 is formed by a shift register, an address decoder, etc., and sequentially and selectively scans the circuit sections corresponding to the pixel columns in the ADC group 105. The digital pixel signals held by the latch 123 are sequentially transmitted to the amplifier circuit 107 via the horizontal transmission line 111 through the horizontal transmission scan circuit 106 that performs selective scanning.

[0090] Amplifier circuit 107 amplifies the digital pixel signal provided by latch 123 and provides the digital pixel signal to signal processing circuit 108.

[0091] The signal processing circuit 108 performs predetermined signal processing on the digital pixel signals provided from the amplifier circuit 107 and generates two-dimensional image data. For example, the signal processing circuit 108 performs correction or signal clamping for vertical line defects and point defects, or performs digital signal processing such as parallel-to-serial conversion, compression, encoding, addition, averaging, and intermittent operations. The signal processing circuit 108 outputs the generated image data to a subsequent device.

[0092] <Pixel configuration example>

[0093] Figure 2 This is a circuit diagram showing an example configuration of the pixel 150 disposed in the pixel section 101.

[0094] Pixel 150 includes a photodiode 151 as a photoelectric conversion element, and includes four transistors as active elements for the photodiode 151, namely, a transmission transistor 152, an amplification transistor 154, a selection transistor 155, and a reset transistor 156.

[0095] Photodiode 151 performs photoelectric conversion on incident light, converting it into a charge (here, electrons) of a quantity corresponding to the light intensity.

[0096] The transfer transistor 152 is connected between the photodiode 151 and the floating diffuser (FD) 153. When the transfer transistor 152 is turned on by the drive signal TX provided by the vertical scanning circuit 103, the transfer transistor 152 transfers the charge accumulated in the photodiode 151 to the FD 153.

[0097] The gate of amplifying transistor 154 is connected to FD 153. Amplifying transistor 154 is connected to vertical signal line 110 via select transistor 155 and is formed as a source follower with a constant current source 157 outside the pixel portion 101. When select transistor 155 is turned on by the drive signal SEL provided from vertical scan circuit 103, amplifying transistor 154 amplifies the potential of FD 153 and outputs a pixel signal representing the voltage according to the potential to vertical signal line 110. Then, the pixel signal output from each pixel 150 is provided to each comparator 121 in ADC group 105 via vertical signal line 110.

[0098] The reset transistor 156 is connected between the power supply VDD and FD 153. When the reset transistor 156 is turned on by the drive signal RST provided by the vertical scanning circuit 103, the potential of FD 153 is reset to the potential of the power supply VDD.

[0099] <Comparator Configuration Example>

[0100] Figure 3 This shows the application to Figure 1 The circuit diagram shows an example configuration of comparator 200 for comparator 121.

[0101] Comparator 200 includes differential amplifier 201, capacitors C11 to C13, switch SW11, and switch SW12. Differential amplifier 201 includes PMOS transistor PT11, PMOS transistor PT12, and NMOS transistors NT11 to NT13.

[0102] The sources of PMOS transistors PT11 and PT12 are connected to power supply VDD1. The drain of PMOS transistor PT11 is connected to the gate of PMOS transistor PT11 and the drain of NMOS transistor NT11. The drain of PMOS transistor PT12 is connected to the drain of NMOS transistor NT12 and the output terminal T15 of output signal OUT1. The source of NMOS transistor NT11 is connected to the source of NMOS transistor NT12 and the drain of NMOS transistor NT13. The source of NMOS transistor NT13 is connected to ground GND1.

[0103] Furthermore, PMOS transistors PT11 and PT12 form a current mirror circuit. NMOS transistors NT11 to NT13 form a differential comparator unit. That is, NMOS transistor NT13 operates as a current source using a bias voltage VG input from the outside via input terminal T14, and NMOS transistors NT11 and NT12 operate as differential transistors.

[0104] Capacitor C11 is connected between the input terminal T11 of the pixel signal VSL and the gate of the NMOS transistor NT11, and serves as the input capacitance relative to the pixel signal VSL.

[0105] Capacitor C12 is connected between the input terminal T12 of the reference signal RAMP and the gate of the NMOS transistor NT11, and serves as the input capacitance relative to the reference signal RAMP.

[0106] Switch SW11 is connected between the drain and gate of NMOS transistor NT11, and is turned on or off by the drive signal AZSW1 input from timing control circuit 102 via input terminal T13.

[0107] Switch SW12 is connected between the drain and gate of NMOS transistor NT12, and is turned on or off by the drive signal AZSW1 input from timing control circuit 102 via input terminal T13.

[0108] Capacitor C13 is connected between the gate of NMOS transistor NT12 and ground line GND1.

[0109] In the following text, the connection point of capacitor C11, capacitor C12, and switch SW11 will be referred to as node HiZ. In the following text, the connection point of the gate of NMOS transistor NT12, capacitor C13, and switch SW12 will be referred to as node VSH.

[0110] <Comparator Operations>

[0111] Next, we will refer to Figure 4The timing diagram illustrates the operation of comparator 200. Figure 4 This is a timing diagram of the drive signal AZSW1, reference signal RAMP, pixel signal VSL, node VSH, node HiZ, and output signal OUT1.

[0112] At time t1, drive signal AZSW1 is set to high. Then, switches SW11 and SW12 are turned on, and the drain and gate of NMOS transistor NT11 and the drain and gate of NMOS transistor NT12 are connected. Reference signal RAMP is set to a predetermined reset level. Furthermore, FD 153 of pixel 150, the target pixel for reading, is reset, and pixel signal VSL is set to reset level.

[0113] In this way, the automatic zeroing operation of the differential amplifier 201 begins. That is, the drain and gate of NMOS transistor NT11 and the drain and gate of NMOS transistor NT12 converge at the same predetermined voltage (hereinafter referred to as the reference voltage). In this way, the voltages of nodes HiZ and VSH are set to the reference voltage.

[0114] Next, the drive signal AZSW1 is set low at time t2, and switches SW11 and SW12 become open. In this way, the auto-zeroing operation of the differential amplifier 201 ends. Since the pixel signal VSL and the reference signal RAMP remain unchanged, the voltage at node HiZ remains at the reference voltage. The voltage at node VSH remains at the reference voltage due to the charge accumulated in capacitor C13.

[0115] At time t3, the voltage of the reference signal RAMP decreases from the reset level by a predetermined value. In this way, the voltage of node HiZ decreases below the voltage of node VSH (the reference voltage), and the output signal OUT1 of the differential amplifier 201 goes low.

[0116] At time t4, the reference signal RAMP begins to increase linearly. Accordingly, the voltage at node HiZ also increases linearly. Furthermore, counter 122 begins counting.

[0117] Subsequently, when the voltage of node HiZ exceeds the voltage (reference voltage) of node VSH, the output signal OUT1 of differential amplifier 201 is inverted and becomes high. Then, when the output signal OUT1 is inverted to high, the count value of counter 122 is held in latch 123 as the value of pixel signal VSL of phase P (reset level).

[0118] At time t5, the voltage of the reference signal RAMP is set to the reset voltage. Furthermore, the transfer transistor 152 of pixel 150 is turned on, the charge accumulated in photodiode 151 during the exposure period is transferred to FD 153, and the pixel signal VSL is set to the signal level. In this way, the voltage of node HiZ decreases by a value corresponding to the signal level and becomes less than the voltage of node VSH (the reference voltage), and the output signal OUT1 of the differential amplifier 201 is inverted to a low level.

[0119] At time t6, the voltage of the reference signal RAMP decreases from the reset level by a predetermined value in the same manner as at time t3. In this way, the voltage of node HiZ decreases further.

[0120] At time t7, the reference signal RAMP begins to increase linearly in the same manner as at time t4. Accordingly, the voltage at node HiZ increases linearly. Furthermore, counter 122 begins counting.

[0121] Subsequently, when the voltage of node HiZ exceeds the voltage (reference voltage) of node VSH, the output signal OUT1 of differential amplifier 201 is inverted to a high level. Then, when the output signal OUT1 is inverted to a high level, the count value of counter 122 is held in latch 123 as the value of the pixel signal VSL of phase D (signal level). Latch 123 performs CDS by acquiring the difference between the pixel signal VSL of phase D and the pixel signal VSL of phase P read between time t4 and time t5. The AD conversion of pixel signal VSL is performed in this way.

[0122] After that, starting from time t8, repeat the same operations as those from time t1 to time t7.

[0123] In this way, by reducing the voltage of VDD1, the power consumption of the ADC group 105 can be reduced, and thus the power consumption of the image sensor 100 can be reduced.

[0124] For example, Figure 5 The figure above shows the configuration of the comparator used in reference 1, etc.

[0125] exist Figure 5 In the comparator shown, the reference signal RAMP, with a linearly decreasing ramp waveform, is input to one input terminal of the differential amplifier 201 (the gate of the NMOS transistor NT11) via capacitor C21. The pixel signal VSL is input to the other input terminal of the differential amplifier 201 (the gate of the NMOS transistor NT12) via capacitor C22.

[0126] Then, as Figure 5As shown in the figure below, the reference signal RAMP and the pixel signal VSL are compared, and the comparison result is output as the output signal OUT. When the output signal OUT is inverted, the input voltage of the differential amplifier 201 (the voltages of the reference signal RAMP and the pixel signal VSL) changes according to the voltage of the pixel signal VSL. Therefore, there are concerns that the input voltage of the differential amplifier 201 will exceed the input dynamic range of the comparator when the output signal OUT is inverted, and that if the voltage of the power supply VDD used to drive the comparator decreases, the linearity of the AD conversion cannot be guaranteed.

[0127] Meanwhile, as described above, the comparison result between the comparator 200 output signal voltage and the voltage of node VSH (reference voltage) is used as the output signal OUT1. This signal voltage is obtained by adding the pixel signal VSL and the reference signal RAMP (voltage of node HiZ) through the input capacitor. At this time, when the output signal OUT1 is reversed, the input voltage of the differential amplifier 201 (voltages of node HiZ and node VSH) does not change but becomes constant.

[0128] In the image sensor 100, the direction of change of the reference signal RAMP is related to... Figure 5 The comparator shown has a reference signal RAMP in the opposite direction, and the reference signal RAMP changes linearly in the direction opposite to the direction of the pixel signal VSL. Here, changing in the opposite direction to the pixel signal VSL means that as the signal component increases, the reference signal RAMP changes in the direction opposite to the direction in which the pixel signal VSL changes. For example, in this example, as the signal component increases, the pixel signal VSL changes in the negative direction, while the reference signal RAMP changes in the positive direction, which is the opposite direction. Therefore, the voltage at node HiZ (the input voltage of the differential amplifier 201) becomes... Figure 5 The voltage corresponding to the difference between the pixel signal VSL and the reference signal RAMP is reduced, and the amplitude decreases.

[0129] As described above, since the input voltage of the differential amplifier 201 becomes constant and the amplitude of the input voltage decreases when the output signal OUT1 is reversed, the input dynamic range of the differential amplifier 201 can be reduced.

[0130] Therefore, with Figure 5 Compared to the comparator in the image sensor 100, the voltage of the power supply VDD1 used to drive the comparator 200 can be reduced to reduce the power consumption of the ADC group 105, and thus reduce the power consumption of the image sensor 100.

[0131] <<2. Variations of the First Embodiment>>

[0132] Next, we will refer to Figures 7 to 19The following describes a variation of the first embodiment, particularly a variation of the comparator 200.

[0133] <First Variation>

[0134] Figure 7 This is a circuit diagram showing an example configuration of comparator 200a according to a first variant of comparator 200. In this diagram, with Figure 3 The components in comparator 200 are represented by the same reference numerals, and their descriptions will be omitted as appropriate.

[0135] The difference between comparator 200a and comparator 200 is that differential amplifier 211 is used instead of differential amplifier 201.

[0136] The differential amplifier 211 includes PMOS transistors PT31 to PT33, NMOS transistor NT31, and NMOS transistor NT32.

[0137] The sources of NMOS transistors NT31 and NT32 are connected to ground GND1. The drain of NMOS transistor NT31 is connected to its gate and the drain of PMOS transistor PT31. The drain of NMOS transistor NT32 is connected to the drain of PMOS transistor PT32 and the output terminal T15 of output signal OUT1. The source of PMOS transistor PT31 is connected to the source of PMOS transistor PT32 and the drain of PMOS transistor PT33. The source of PMOS transistor PT33 is connected to power supply VDD1.

[0138] NMOS transistors NT31 and NT32 form a current mirror circuit. Furthermore, PMOS transistors PT31 to PT33 form a differential comparator unit. That is, PMOS transistor PT33 operates as a current source using an externally input bias voltage VG via input terminal T14, and PMOS transistors PT31 and PT32 operate as differential transistors.

[0139] Capacitor C11 is connected between the input terminal T11 of the pixel signal VSL and the gate of the PMOS transistor PT31, and serves as the input capacitance relative to the pixel signal VSL.

[0140] Capacitor C12 is connected between the input terminal T12 of the reference signal RAMP and the gate of the PMOS transistor PT31, and serves as the input capacitance relative to the reference signal RAMP.

[0141] Switch SW11 is connected between the drain and gate of PMOS transistor PT31, and is turned on or off by the drive signal AZSW1 input from timing control circuit 102 via input terminal T13.

[0142] Switch SW12 is connected between the drain and gate of PMOS transistor PT32, and is turned on or off by the drive signal AZSW1 input from timing control circuit 102 via input terminal T13.

[0143] Capacitor C13 is connected between power supply VDD1 and the gate of PMOS transistor PT32.

[0144] Comparator 200a is designed such that the polarity of the transistor is opposite to that in comparator 200, and performs the same operation as comparator 200. Furthermore, by using comparator 200a, the voltage of the power supply VDD1 can be reduced in the same manner as when using comparator 200, thus achieving low power consumption.

[0145] <Second Variation>

[0146] Figure 8 This is a circuit diagram showing an example configuration of comparator 200b according to a second variation of comparator 200. In this diagram, with Figure 3 The components in comparator 200 are represented by the same reference numerals, and their descriptions will be omitted as appropriate.

[0147] The difference between comparator 200b and comparator 200 is that the drive signals are input to switches SW11 and SW12 respectively. Specifically, drive signal AZSW1A is input to switch SW11 from the timing control circuit 102 via input terminal T13A, and drive signal AZSW1B is input to switch SW12 from the timing control circuit 102 via input terminal T13B. In this way, for example, switches SW11 and SW12 are controlled independently, and the voltages of node HiZ and node VSH can be controlled independently during automatic zeroing operation.

[0148] <Third Variation>

[0149] Figure 9 This is a circuit diagram showing an example configuration of comparator 200c according to a third variation of comparator 200. In this diagram, with Figure 7 The components in comparator 200a are denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0150] The difference between comparator 200c and comparator 200a is that the drive signal is compared with... Figure 8The comparator 200b shown is input to switches SW11 and SW12 in the same manner. Specifically, drive signal AZSW1A is input to switch SW11 from timing control circuit 102 via input terminal T13A, and drive signal AZSW1B is input to switch SW12 from timing control circuit 102 via input terminal T13B. In this way, for example, switches SW11 and SW12 are controlled independently, and the voltages of node HiZ and node VSH can be controlled independently during automatic zeroing operation.

[0151] <Fourth Variation>

[0152] Figure 10 This is a circuit diagram showing an example configuration of comparator 200d according to a fourth variation of comparator 200. In this diagram, with Figure 3 The components in comparator 200 are represented by the same reference numerals, and their descriptions will be omitted as appropriate.

[0153] Comparator 200d is obtained by adding output amplifier 221 and capacitor C42 to comparator 200.

[0154] Output amplifier 221 serves as a buffer for the output signal OUT1 of differential amplifier 201, so as to output an output signal OUT1 at a level suitable for subsequent circuitry. That is, output amplifier 221 amplifies the output signal OUT1 of differential amplifier 201 with a predetermined gain and outputs the resulting output signal OUT2 from output terminal T42.

[0155] The output amplifier 221 includes a PMOS transistor PT41, an NMOS transistor NT41, a capacitor C41, and a switch SW41.

[0156] The source of PMOS transistor PT41 is connected to power supply VDD1, its gate is connected to the output of differential amplifier 201, and its drain is connected to the drain of PMOS transistor PT41 and output terminal T42. The source of NMOS transistor NT41 is connected to ground GND1, and its gate is connected to ground GND1 via capacitor C41. Switch SW41 is connected between the drain and gate of NMOS transistor NT41, and is turned on or off by the drive signal AZSW2 input from timing control circuit 102 via input terminal T41.

[0157] Capacitor C42 is connected between the power supply VDD1 and the drain of the PMOS transistor PT12 (the output of differential amplifier 201). Capacitor C42 removes high-frequency components from the output signal OUT1 of differential amplifier 201.

[0158] Next, we will refer to Figure 11The timing diagram shown illustrates the operation of comparator 200d. Figure 11 The timing diagrams for drive signal AZSW1, drive signal AZSW2, reference signal RAMP, pixel signal VSL, node VSH, node HiZ, output signal OUT1, and output signal OUT2 are shown.

[0159] At time t1, the drive signal AZSW1 is set to high level, the reference signal RAMP is set to reset level, and FD 153, which is used to read the target pixel 150, is connected to... Figure 4 At time t1, it is reset in the same way. In this way, the automatic zeroing operation of the differential amplifier 201 described above is performed.

[0160] Furthermore, the drive signal AZSW2 is set to a high level. Then, switch SW41 becomes on, and the drain and gate of PMOS transistor PT41 are connected.

[0161] In this way, the automatic zeroing operation of the output amplifier 221 is initiated. That is, the voltage of capacitor C41 becomes equal to the drain voltage of PMOS transistor PT41, and charge accumulates in capacitor C41.

[0162] At time t2, the drive signal AZSW2 is set to low. Then, switch SW41 turns off, and the automatic zeroing operation of output amplifier 221 is completed. Even after switch SW41 turns off, the voltage of capacitor C41 remains constant and is then applied to the gate of NMOS transistor NT41. Therefore, NMOS transistor NT41 acts as a current source, producing essentially the same current as when switch SW41 turns on.

[0163] From time t3 to time t8, execution and... Figure 4 The same operation is performed from time t2 to time t7. At this time, when the output signal OUT1 of differential amplifier 201 goes high, the PMOS transistor PT41 of output amplifier 221 is turned off, and the output signal OUT2 goes low. Simultaneously, when the output signal OUT1 of differential amplifier 201 goes low, the PMOS transistor PT41 of output amplifier 221 turns on, and the output signal OUT2 goes high. In other words, output amplifier 221 outputs the output signal OUT1 of differential amplifier 201 in a level-inverted manner.

[0164] After that, starting from time t9, repeat the same operations as those from time t1 to time t8.

[0165] <Fifth Variation>

[0166] Figure 12This is a circuit diagram showing an example configuration of comparator 200e according to a fifth variation of comparator 200. In this diagram, with Figure 7 The comparator 200a and Figure 10 The corresponding parts in comparator 200d are indicated by the same reference numerals, and their descriptions will be omitted appropriately.

[0167] Comparator 200e is obtained by adding output amplifier 231 and capacitor C42 to comparator 200a.

[0168] The output amplifier 231 includes a PMOS transistor PT51, an NMOS transistor NT51, a capacitor C51, and a switch SW51.

[0169] The source of NMOS transistor NT51 is connected to ground GND1, its gate is connected to the output of differential amplifier 211, and its drain is connected to the drain of PMOS transistor PT51 and output terminal T42. The source of PMOS transistor PT41 is connected to power supply VDD1, and its gate is connected to power supply VDD1 via capacitor C51. Switch SW51 is connected between the drain and gate of PMOS transistor PT51, and is turned on or off by the drive signal AZSW2 input from timing control circuit 102 via input terminal T41.

[0170] The output amplifier 231 is designed such that the polarity of the transistor is... Figure 10 The output amplifier 221 in the middle has the opposite polarity, and amplifies the output signal OUT1 of the differential amplifier 211 with a predetermined gain in the same manner as the output amplifier 221, and outputs the thus obtained output signal OUT2 from the output terminal T42.

[0171] <Sixth Variation>

[0172] Figure 13 This is a circuit diagram showing an example configuration of comparator 200f according to a sixth variation of comparator 200. In this diagram, with Figure 10 The components in comparator 200 are represented by the same reference numerals, and their descriptions will be omitted as appropriate.

[0173] The difference between comparator 200f and comparator 200d is that differential amplifier 201 and output amplifier 221 have separate power supplies.

[0174] Specifically, the source of the PMOS transistor PT41 of the output amplifier 221 is connected to a power supply VDD2, which is different from the power supply VDD1. The source of the NMOS transistor NT41 of the output amplifier 221 and one end of the capacitor C41 are connected to a ground line GND2, which is different from the ground line GND1.

[0175] In this way, for example, the drive voltage of the differential amplifier 201 and the drive voltage of the output amplifier 221 can be set to different values.

[0176] Furthermore, one end of capacitor C42 can be connected to power supply VDD2 instead of power supply VDD1.

[0177] <Seventh Variation>

[0178] Figure 14 This is a circuit diagram showing an example configuration of comparator 200g according to a seventh variation of comparator 200. In this diagram, with Figure 12 The components in comparator 200e are represented by the same reference numerals, and their descriptions will be omitted as appropriate.

[0179] The difference between comparator 200g and comparator 200e is that differential amplifier 211 and output amplifier 231 have separate power supplies.

[0180] Specifically, the source of the PMOS transistor PT51 of the output amplifier 231 and one end of the capacitor C51 are connected to a power supply VDD2, which is different from the power supply VDD1. In addition, the source of the NMOS transistor NT51 of the output amplifier 231 is connected to a ground line GND2, which is different from the ground line GND1.

[0181] In this way, the drive voltage of the differential amplifier 201 and the drive voltage of the output amplifier 231 can be set to different values.

[0182] Alternatively, one end of capacitor C42 can be connected to ground GND2 instead of ground GND1.

[0183] <Eighth Variation>

[0184] Figure 15 This is a circuit diagram showing an example configuration of comparator 200h according to the eighth variant of comparator 200. In this diagram, with Figure 3 The components in comparator 200 are represented by the same reference numerals, and their descriptions will be omitted as appropriate.

[0185] The difference between comparator 200h and comparator 200d is that variable capacitors C61 and C62 with variable capacitance are used instead of capacitors C11 and C12. That is, the pixel signal VSL is input to the gate of the NMOS transistor NT11 of the differential amplifier 201 via the variable capacitor C61, and the reference signal RAMP is input to the gate of the NMOS transistor NT11 of the differential amplifier 201 via the variable capacitor C62.

[0186] If we assume that the capacitance of variable capacitor C61 is C61 and the capacitance of variable capacitor C62 is C62, then the amplitude ΔVSL of the pixel signal VSL voltage in node Hiz is ΔVSL × C61 / (C61 + C62). Therefore, for example, if we assume that capacitance C61 = capacitance C62, the pixel signal VSL input to differential amplifier 201 attenuates to approximately half its original value. Consequently, the input reference noise increases. Therefore, by increasing the ratio of capacitance C61 (the input capacitance of the pixel signal VSL) to capacitance C62 (the input capacitance of the reference signal RAMP), the attenuation of the pixel signal VSL input to differential amplifier 201 and the input reference noise can be suppressed.

[0187] However, if the ratio of the input capacitance of the pixel signal VSL to the input capacitance of the reference signal RAMP increases, the attenuation of the reference signal RAMP input to the differential amplifier 201 will actually increase.

[0188] Figure 16 This is a graph showing a comparison of the reference signal RAMP input to the differential amplifier 201 as the ratio of the input capacitance of the pixel signal VSL to the input capacitance of the reference signal RAMP increases and decreases. Figure 16 The waveform represented by the dashed line represents the waveform of the reference signal RAMP input to the differential amplifier 201 when the ratio is increased, and the waveform represented by the solid line represents the waveform of the reference signal RAMP input to the differential amplifier 201 when the ratio is decreased.

[0189] In this way, if the ratio of the input capacitance of the pixel signal VSL to the input capacitance of the reference signal RAMP increases, the amplitude of the reference signal RAMP input to the differential amplifier 201 decreases. As a result, the dynamic range of the ADC is reduced.

[0190] Conversely, for example, it is thought that the reduction in the dynamic range of the ADC can be suppressed by increasing the amplitude of the reference signal RAMP output from DAC 104 to increase the amplitude of the reference signal RAMP input to differential amplifier 201.

[0191] However, the maximum amplitude of the reference signal RAMP is limited by the specifications of the DAC 104. Since the amplitude of the reference signal RAMP is set small in high-gain mode, it is possible to increase its amplitude. At the same time, since the amplitude of the reference signal RAMP is preset large in low-gain mode, it is difficult to further increase its amplitude in certain situations.

[0192] Therefore, it is considered to maximize the ratio of the input capacitance of the pixel signal VSL to the input capacitance of the reference signal RAMP, and to increase the amplitude of the reference signal RAMP in high-gain mode. In this way, the attenuation of the pixel signal VSL input to the differential amplifier 201 can be suppressed, and the influence of noise in high-gain mode, where the influence of noise tends to increase, can be suppressed.

[0193] Meanwhile, for example, it is assumed that the input capacitance of the reference signal RAMP and the input capacitance of the pixel signal VSL are set to similar values ​​in low gain mode.

[0194] Next, we will refer to Figure 17 This section provides specific configuration examples for variable capacitors C61 and C62.

[0195] Figure 17 This is a circuit diagram showing an example configuration of comparator 200ha.

[0196] In comparator 200ha, Figure 15 The variable capacitors C61 and C62 include capacitors C71 to C73, switch SW71, and switch SW72.

[0197] One end of capacitor C72 is connected to input terminal T11 and one end of capacitor C71 via switch SW71, and is also connected to input terminal T12 and one end of capacitor C73 via switch SW72. The other ends of capacitors C71 to C73 are connected to the gate of NMOS transistor NT11.

[0198] For example, the capacitances of capacitors C71 to C73 are set to the same value. Then, the ratio between the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP is controlled by controlling the states of switches SW71 and SW72.

[0199] Specifically, switches SW71 and SW72 are controlled so that at least one becomes open. When switch SW71 is on and switch SW72 is off, the ratio between the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP is 2:1, and the pixel signal VSL input to the differential amplifier 201 is attenuated to approximately 2 / 3. When switch SW71 is off and switch SW72 is on, the ratio between the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP is 1:2, and the pixel signal VSL input to the differential amplifier 201 is attenuated to approximately 1 / 3. When both switches SW71 and SW72 are off, the ratio between the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP is 1:1, and the pixel signal VSL input to the differential amplifier 201 is attenuated to approximately 1 / 2.

[0200] The number of arrays of capacitors can be set arbitrarily.

[0201] For example, such as Figure 18 The comparator shown is 200hb, and the five capacitors C71 to C75 can be connected in parallel.

[0202] Specifically, one end of capacitor C72 is connected to input terminal T11 and one end of capacitor C71 via switch SW71, and is also connected to one end of capacitor C73 via switch SW72. One end of capacitor C74 is connected to one end of capacitor C73 via switch SW73, and is also connected to input terminal T12 and one end of capacitor C75 via switch SW74. The other ends of capacitors C71 to C75 are connected to the gate of NMOS transistor NT11.

[0203] For example, capacitors C71 to C75 are capacitors with the same capacitance. The ratio between the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP is controlled by controlling the state of switches SW71 to SW74. Switches SW71 to SW74 are controlled so that at least one becomes open.

[0204] Even in other comparators, the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP can be set to be variable using the same method.

[0205] Alternatively, the ratio between the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP can be adjusted by fixing one of the input capacitances of the pixel signal VSL and the reference signal RAMP, and setting the other to be variable.

[0206] <Ninth Variation>

[0207] Figure 19 This is a circuit diagram showing an example configuration of comparator 200i according to a ninth variation of comparator 200. In this diagram, with Figure 17 The components in comparator 200ha are denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0208] Comparator 200i is obtained by removing capacitor C13 and switch SW12 from comparator 200ha and connecting the gate of NMOS transistor NT12 to input terminal T81. Therefore, in comparator 200i, the reference voltage is set by the bias voltage input from an external source through input terminal T81.

[0209] Even in other comparators, the reference voltage can be set by using an externally input bias voltage, using the same method.

[0210] <<3. Second Embodiment>>

[0211] Next, we will refer to Figure 20 and Figure 21 The second embodiment of the present invention will be described.

[0212] The second embodiment differs from the first embodiment in the configuration of the comparator. Specifically, in the second embodiment, a single-type amplifier is used in comparator 121, while in the first embodiment, a differential amplifier (differential amplifier 201 or differential amplifier 211) is used in the comparator.

[0213] <Comparator Configuration Example>

[0214] Figure 20 This illustrates the application of the second embodiment of the present invention. Figure 1 A circuit diagram illustrating an example configuration of comparator 300 in comparator 121 of the image sensor 100 shown.

[0215] Comparator 300 includes a single-type amplifier 301, capacitor C101, capacitor C102, and switch SW101. Amplifier 301 includes PMOS transistor PT101, PMOS transistor PT102, NMOS transistor NT101, and NMOS transistor NT102.

[0216] The source of PMOS transistor PT101 is connected to power supply VDD1, and its drain is connected to the source of PMOS transistor PT102. The drain of PMOS transistor PT102 is connected to the drain of NMOS transistor NT101 and the output terminal T104 of output signal OUT1. The drain of NMOS transistor NT102 is connected to the source of NMOS transistor NT101, and its source is connected to ground GND1.

[0217] PMOS transistors PT101 and PT102 form a current source.

[0218] In addition, PMOS transistor PT102 and NMOS transistor NT101 are used as cascode devices to prevent kickback from the output to the input of comparator 300. Cascode devices prevent kickback from affecting other ADCs through the reference signal RAMP line and prevent stripes. PMOS transistor PT102 and NMOS transistor NT101 can also be removed if performance degradation is permissible.

[0219] Capacitor C101 is connected between the input terminal T101 of the pixel signal VSL and the gate of the NMOS transistor NT102, and serves as the input capacitance relative to the pixel signal VSL.

[0220] Capacitor C102 is connected between the input terminal T102 of the reference signal RAMP and the gate of the NMOS transistor NT102, and serves as the input capacitance relative to the reference signal RAMP.

[0221] Switch SW101 is connected between the drain of NMOS transistor NT101 and the gate of NMOS transistor NT102, and is turned on or off by the drive signal AZSW1 input from timing control circuit 102 via input terminal T103.

[0222] In the following text, the connection point of capacitor C11, capacitor C12 and switch SW101 will be referred to as node HiZ.

[0223] <Comparator Operations>

[0224] Next, we will refer to Figure 21 The timing diagram in the diagram describes the operation of comparator 300. Figure 21 This is a timing diagram of the drive signal AZSW1, pixel signal VSL, reference signal RAMP, node HiZ, and output signal OUT1.

[0225] At time t1, FD 153 of pixel 150, which is the target pixel for reading, is reset, and the pixel signal VSL is set to the reset level. At this time, the reference signal RAMP is set to the predetermined reset level.

[0226] At time t2, the drive signal AZSW1 is set to high, and the amplifier 301 performs an automatic zeroing operation. Specifically, switch SW101 turns on, establishing a connection between node HiZ and output terminal T104, and short-circuiting the input and output of amplifier 301. In this way, the voltage at node HiZ and the voltage at output signal OUT1 converge to a voltage near the midpoint between the high and low levels of output signal OUT1. This converged voltage becomes the reference voltage. That is, if the voltage at node HiZ (the input voltage of amplifier 301) becomes greater than the reference voltage after switch SW101 turns off, the voltage at output signal OUT1 drops to low. Conversely, if the voltage at node HiZ (the input voltage of amplifier 301) becomes less than the reference voltage, the voltage at output signal OUT1 rises to high.

[0227] At time t3, drive signal AZSW1 is set to low, switch SW101 becomes open, and the automatic zeroing operation of amplifier 301 is completed. The voltage at node HiZ and the voltage of output signal OUT1 remain at the reference voltage.

[0228] At time t4, the voltage of the reference signal RAMP decreases from the reset level by a predetermined value. In this way, the voltage of node HiZ becomes less than the reference voltage, and the output signal OUT1 goes high.

[0229] At time t5, the reference signal RAMP begins to increase linearly. Accordingly, the voltage at node HiZ also increases linearly. Furthermore, counter 122 begins counting.

[0230] Subsequently, when the voltage of node HiZ exceeds the reference voltage, the voltage of output signal OUT1 is reversed to a low level. Then, when output signal OUT1 is reversed to a low level, the count value of counter 122 is held by latch 123 as the value of pixel signal VSL of phase P (reset level).

[0231] At time t6, the voltage of the reference signal RAMP is set to the reset voltage. In this way, the voltage of node HiZ returns to the reference voltage, and the voltage of the output signal OUT1 becomes substantially the same as the reference voltage.

[0232] At time t7, the transmission transistor 152 of pixel 150 turns on, and the charge accumulated in photodiode 151 during the exposure period is transferred to FD 153. In this way, the pixel signal VSL is set to the signal level, and the voltage of node HiZ decreases from the reference voltage by a value corresponding to the signal level. As a result, the output signal OUT1 goes high. However, when the signal level of pixel signal VSL is low, the voltage of output signal OUT1 may remain at approximately the same value as the reference voltage in some cases.

[0233] At time t8, the voltage of the reference signal RAMP decreases from the reset level by a predetermined value in the same manner as at time t4. This further decreases the voltage of node HiZ.

[0234] The reference signal RAMP begins to increase linearly at time t9 in the same manner as at time t5. Accordingly, the voltage at node HiZ also increases linearly. Furthermore, counter 122 begins counting.

[0235] Subsequently, when the voltage at node HiZ becomes greater than the reference voltage, the output signal OUT1 is inverted to a low level. Then, when the output signal OUT1 is inverted to a low level, the count value of counter 122 is held by latch 123 as the value of the pixel signal VSL of phase D (signal level). Latch 123 performs CDS by acquiring the difference between the pixel signal VSL of phase D and the pixel signal VSL of phase P read between time t5 and time t6. The AD conversion of the pixel signal VSL is performed in this way.

[0236] At time t10, the voltage of the reference signal RAMP is set to the reset voltage in the same manner as at time t6. In this way, the voltage of node HiZ returns to the reference voltage, and the voltage of the output signal OUT1 becomes substantially the same as the reference voltage.

[0237] After that, at time t11 and thereafter, the same operation as from time t1 to time t10 is repeated.

[0238] In comparator 300, by using a single-type amplifier 301, current consumption can be reduced to about half that of the case when using a differential amplifier, and power consumption can be reduced.

[0239] Furthermore, since amplifier 301 is source-grounded and the bias current is constant, the current variation is smaller compared to the case of using an inverter-type amplifier, and the generation of stripes is suppressed.

[0240] Furthermore, in comparator 300, the input voltage of amplifier 301 is... Figure 5 The voltage corresponding to the difference between the pixel signal VSL and the reference signal RAMP is shown, and the amplitude is related to... Figure 3 The comparator 200 shown is reduced in the same way. In this way, the input dynamic range of the amplifier 301 can be reduced. Therefore, the voltage of the power supply VDD1 used to drive the comparator 300 can be reduced, the power consumption of the ADC group 105 can be reduced, and thus the power consumption of the image sensor 100 can be reduced.

[0241] <<4. Variations of the Second Embodiment>>

[0242] Next, we will refer to Figures 22 to 32 The following describes a variation of the second embodiment, particularly a variation of the comparator 300.

[0243] <First Variation>

[0244] Figure 22 This is a circuit diagram showing an example configuration of comparator 300a according to a first variant of comparator 300. In this diagram, with Figure 20 The components in comparator 300 are denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0245] Comparator 300a differs from comparator 300 in the input position of amplifier 301. Specifically, capacitor C101 is connected between input terminal T101 and the gate of PMOS transistor PT101. Capacitor C102 is connected between input terminal T102 and the gate of PMOS transistor PT101. Switch SW101 is connected between the gate of PMOS transistor PT101 and the drain of PMOS transistor PT102.

[0246] Comparator 300a differs from comparator 300 only in the input position of amplifier 301, but performs the same operation as comparator 300.

[0247] In comparator 300a, NMOS transistors NT101 and NT102 form the current source of amplifier 301.

[0248] <Second Variation>

[0249] Figure 23 This is a circuit diagram showing an example configuration of comparator 300b according to a second variation of comparator 300. In this diagram, with Figure 20 The components in comparator 300 are denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0250] Comparator 300b is obtained by adding a clamping circuit formed by PMOS transistor PT111 to comparator 300. Specifically, the source of PMOS transistor PT111 is connected to output terminal T104, and its drain is connected to ground GND2.

[0251] For example, if the drain voltages of PMOS transistors P101 and PT102, which form the current source, rise and exceed a predetermined threshold, then PMOS transistor PT111 turns on, and the increase in the drain voltage of the current source is suppressed. In this way, the current change of the current source is suppressed, and thus the generation of stripes is suppressed.

[0252] Typically, ground wires GND1 and GND2 can be set.

[0253] <Third Variation>

[0254] Figure 24 This is a circuit diagram showing an example configuration of comparator 300c according to a third variation of comparator 300. In this diagram, with Figure 22 The components in comparator 300a are denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0255] Comparator 300c is obtained by adding a clamping circuit formed by an NMOS transistor NT111 to comparator 300a. Specifically, the source of the NMOS transistor NT111 is connected to the output terminal T104, and its drain is connected to the power supply VDD2.

[0256] For example, if the drain voltages of NMOS transistors NT101 and NT102, which form the current source, drop below a predetermined threshold, then NMOS transistor NT111 turns on, and the decrease in the drain voltage of the current source is suppressed. In this way, changes in the current of the current source are suppressed, and thus the generation of stripes is suppressed.

[0257] Typically, power supply VDD1 and power supply VDD2 can be set.

[0258] <Fourth Variation>

[0259] Figure 25 This is a circuit diagram showing an example configuration of comparator 300d according to a fourth variation of comparator 300. In this diagram, with Figure 23 The components in comparator 300b are denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0260] Comparator 300d is obtained by adding a sample and hold circuit formed by capacitor C121 and switch SW121 and a band-limited capacitor formed by capacitor C122 to comparator 300b.

[0261] Specifically, capacitor C121 is connected between power supply VDD1 and the gate of PMOS transistor PT101. Switch SW121 is connected between input terminal T121 and the gate of PMOS transistor PT101. Switch SW121 is turned on or off by the drive signal SHSW input from timing control circuit 102 via input terminal T122.

[0262] Even after switch SW121 is turned off, the bias voltage (gate voltage of PMOS transistor PT101) input from input terminal T121 via switch SW121 is maintained by capacitor C121. In this way, the gate of PMOS transistor PT101 is disconnected from other comparators 300d, and the generation of stripes and lateral noise is suppressed.

[0263] Capacitor C122 is connected between power supply VDD1 and output terminal T104. This capacitor C122 removes high-frequency components from the output signal OUT1.

[0264] <Fifth Variation>

[0265] Figure 26This is a circuit diagram showing an example configuration of comparator 300e according to a fifth variation of comparator 300. In this diagram, with Figure 24 The comparator 300c and Figure 25 The corresponding parts in comparator 300d are indicated by the same reference numerals, and their descriptions will be omitted appropriately.

[0266] With Figure 25 In the same manner as comparator 300d, comparator 300e is constructed by adding a sample and hold circuit formed by capacitor C121 and switch SW121, and a band-limiting capacitor formed by capacitor C122. Figure 24 It is obtained from comparator 300c in the middle.

[0267] Specifically, capacitor C121 is connected between the gate of NMOS transistor NT102 and ground GND2. Switch SW121 is connected between input terminal T121 and the gate of NMOS transistor NT102. Switch SW121 is turned on or off by the drive signal SHSW input from timing control circuit 102 via input terminal T122.

[0268] Even after switch SW121 is turned off, the bias voltage (gate voltage of NMOS transistor NT102) input from input terminal T121 via switch SW121 is maintained by capacitor C121. In this way, the gate of NMOS transistor NT102 is disconnected from other comparators 300e, and the generation of stripes and lateral noise is suppressed.

[0269] Typically, ground wires GND1 and GND2 can be set.

[0270] <Sixth Variation>

[0271] Figure 27 This is a circuit diagram showing an example configuration of comparator 300f according to a sixth variation of comparator 300. In this diagram, with Figure 25 The components in comparator 300d are represented by the same reference numerals, and their descriptions will be omitted as appropriate.

[0272] Comparator 300f is obtained by adding output amplifier 311 to comparator 300d. Output amplifier 311 has the same characteristics as... Figure 10 It has the same circuit configuration as the output amplifier 221 and has the same function as the output amplifier 221.

[0273] Specifically, the output amplifier 311 includes a PMOS transistor PT131, an NMOS transistor NT131, a capacitor C131, and a switch SW131.

[0274] The source of PMOS transistor PT131 is connected to power supply VDD2, its gate is connected to the output of amplifier 301, and its drain is connected to the drain of NMOS transistor NT131 and output terminal T132. The source of NMOS transistor NT131 is connected to ground GND2, and its gate is connected to ground GND2 via capacitor C131. Switch SW131 is connected between the drain and gate of NMOS transistor NT131, and is turned on or off by the drive signal AZSW2 input from timing control circuit 102 via input terminal T131.

[0275] Capacitor C122 is connected between power supply VDD2 and the gate of PMOS transistor PT131.

[0276] Next, we will refer to Figure 28 The timing diagram illustrates the operation of comparator 300f. Figure 28 This is a timing diagram of drive signals SHSW, AZSW1, AZSW2, pixel signal VSL, reference signal RAMP, node HiZ, output signal OUT1, and output signal OUT2.

[0277] At time t1, with Figure 21 At time t1, FD153, which is the target pixel 150, is reset in the same way.

[0278] At time t2, drive signals SHSW, AZSW1, and AZSW2 are set to high level.

[0279] In this way, the bias voltage is input from the input terminal T122 to the gate of the PMOS transistor T101, and the charge corresponding to the bias voltage accumulates in the capacitor C121.

[0280] In addition, with Figure 21 At time t2, the amplifier 301 performs the automatic zeroing operation in the same way.

[0281] In addition, with Figure 11 At time t1, the amplifier 311 performs the automatic zeroing operation in the same way.

[0282] At time t3, the drive signal SHSW is set to low. In this way, the input of the bias voltage from the input terminal T122 is stopped, and the bias voltage is input to the gate of the PMOS transistor PT101 through the charge accumulated in the capacitor C121.

[0283] At time t4, the drive signal AZSW2 is set to low level, and the automatic zeroing operation of the output amplifier 311 is completed.

[0284] Subsequently, execution will take place from time t5 to time t12. Figure 21 The operation from time t3 to time t10 is the same. At this time, the output signal OUT2 output from the output terminal T132 of the output amplifier 311 is obtained by inverting and amplifying the output signal OUT1 of the amplifier 301.

[0285] Subsequently, at time t13, the same operation as that from time t1 to time t12 is repeated.

[0286] Typically, power supply VDD1 and power supply VDD2 can be set. Also, ground wire GND1 and ground wire GND2 can typically be set.

[0287] <Seventh Variation>

[0288] Figure 29 This is a circuit diagram showing an example configuration of comparator 300g according to a seventh variation of comparator 300. In this diagram, with Figure 26 The comparator 300e and Figure 27 The corresponding parts in comparator 300f are indicated by the same reference numerals, and their descriptions will be omitted as appropriate.

[0289] By means of Figure 27 The output amplifier 311 is added in the same way as the comparator 300f in the middle. Figure 26 Comparator 300e is used to obtain comparator 300g.

[0290] Specifically, the output of amplifier 301 is connected to the gate of PMOS transistor PT131 of output amplifier 311. Capacitor C122 is connected between power supply VDD2 and the gate of PMOS transistor PT131.

[0291] Typically, power supply VDD1 and power supply VDD2 can be set. Also, ground wire GND1 and ground wire GND2 can typically be set.

[0292] <Eighth Variation>

[0293] Figure 30 This is a circuit diagram showing an example configuration of comparator 300h according to the eighth variant of comparator 300. In this diagram, with Figure 20 The components in comparator 300 are denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0294] Comparator 300h is designed to make the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP equal to... Figure 15The comparator 200h is variable in the same way. Specifically, the variable capacitor C141 is connected between the input terminal T101 and the gate of the NMOS transistor NT102. The variable capacitor C142 is connected between the input terminal T102 and the gate of the NMOS transistor NT102.

[0295] In this way, through with Figure 15 The input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP are adjusted in the same way as the comparator 200h to suppress input reference noise.

[0296] Figure 31 and Figure 32 It shows Figure 30 Specific configuration examples of variable capacitors C141 and C142 are provided.

[0297] Specifically, in Figure 31 In the comparator 300ha, variable capacitors C141 and C142 are connected by... Figure 17 The circuit in the comparator 200ha is the same circuit formed.

[0298] In other words, one end of capacitor C152 is connected to input terminal T101 and one end of capacitor C151 via switch SW151, and is also connected to input terminal T102 and one end of capacitor C153 via switch SW152. The other ends of capacitors C151 to C153 are connected to the gate of NMOS transistor NT102.

[0299] exist Figure 32 In comparator 300hb, variable capacitors C141 and C142 are connected to... Figure 18 The circuitry in the comparator 200hb is the same as that in the circuitry.

[0300] In other words, one end of capacitor C152 is connected to the input terminal T101 and one end of capacitor C151 via switch SW151, and is also connected to one end of capacitor C153 via switch SW152. One end of capacitor C154 is connected to one end of capacitor C153 via switch SW153, and is also connected to the input terminal T102 and one end of capacitor C155 via switch SW154. The other ends of capacitors C151 to C155 are connected to the gate of NMOS transistor NT102.

[0301] Even in other comparators according to the second embodiment, the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP can be set to be variable in the same manner.

[0302] <<5. Third Embodiment>>

[0303] exist Figure 1 In the image sensor 100 shown, an ADC is provided for each pixel column in the pixel unit 101. That is, the same ADC performs AD conversion on the pixel signal VSL of the pixel 150 in the same pixel column, and different ADCs perform AD conversion on the pixel signal VSL of the pixel 150 in different pixel columns. Therefore, if the input capacitance of the pixel signal VSL of the comparator 121 forming the ADC of each pixel column (e.g., ...) is... Figure 3 The capacitor C11 in the reference signal RAMP has an input capacitance (e.g., Figure 3 If there is a mismatch (difference) between capacitors C12 in the image, the gain of the ADC (hereinafter referred to as AD conversion gain) of each pixel column will also be mismatched (difference). There is a concern that the mismatch of AD conversion gain between pixel columns will cause vertical stripes in the image data.

[0304] For example, when switch SW71 of comparator 200ha becomes on and switch SW72 becomes off, including Figure 17 The AD conversion gain of the ADC of the comparator 200ha shown is represented by the following expression (1).

[0305] Mathematical Expression 1

[0306]

[0307] In expression (1), C71 to C73 represent the statistical values ​​(ideal capacitances) of the capacitances of capacitors C71 to C73, respectively. ΔC71 to ΔC73 represent the errors in the capacitances of capacitors C71 to C73 relative to the statistical values. Therefore, the actual capacitance of capacitor C71 is C71 + ΔC71, the actual capacitance of capacitor C72 is C72 + ΔC72, and the actual capacitance of capacitor C73 is C73 + ΔC73.

[0308] Here, if the errors ΔC71 to ΔC73 vary between pixel columns and create a mismatch between the capacitances of capacitors C71 to C73, then an AD conversion gain mismatch will occur between the ADCs of the individual arrays. There is concern that this mismatch in AD conversion gain between pixel columns will result in vertical stripes in the image data.

[0309] The third embodiment is used to suppress the appearance of vertical stripes in image data.

[0310] <Comparator Configuration Example>

[0311] Figure 33 This illustrates the application of the third embodiment of the present invention. Figure 1A circuit diagram illustrating an example configuration of comparator 400 in comparator 121 of the image sensor 100 shown.

[0312] The comparator 400 includes a comparator circuit 401, capacitors C201 to C203, and switches SW201 to SW203.

[0313] Although simply shown in the figure, the comparator circuit 401 is formed by the nodes HiZ of the comparators 200 to 200i or 300 to 300hb and the circuit after the nodes HiZ.

[0314] Terminal 1 of switch SW201 is connected to input terminal T201, and terminal 3 of switch SW202 is connected to input terminal T202. Terminal 1 of switch SW202 is connected to input terminal T201, and terminal 3 of switch SW203 is connected to input terminal T201, and terminal 3 of switch SW203 is connected to input terminal T202.

[0315] For example, the states of switches SW201 to SW203 are controlled by timing control circuit 102.

[0316] Capacitor C201 is connected between terminal 0 of switch SW201 and node HiZ. Capacitor C202 is connected between terminal 0 of switch SW202 and node HiZ. Capacitor C203 is connected between terminal 0 of switch SW203 and node HiZ.

[0317] Ideally, the capacitances of capacitors C201 through C203 should be set to the same value, but in practice, differences arise due to capacitance tolerances. Specifically, the capacitance of capacitor C201 is C201 + ΔC201, the capacitance of capacitor C202 is C202 + ΔC202, and the capacitance of capacitor C203 is C203 + ΔC203. C201 through C203 represent the design values ​​of the capacitances of capacitors C201 through C203, respectively, and satisfy C201 = C202 = C203. ΔC201 through ΔC203 represent the tolerances of capacitors C201 through C203, and these tolerances exist between the capacitors.

[0318] In comparator 400, by using with Figure 17 The comparator 200ha and Figure 31 The comparator 300ha controls the state of switches SW201 to SW203 in the same way to control the ratio between the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP.

[0319] like Figure 34 As shown, for example, the appearance of vertical stripes in image data can be suppressed by controlling the states of switches SW201 to SW203.

[0320] When performing AD conversion on the pixel signal VSL of pixel 150 in the 3n-2th row (row 1, row 4, row 7, ...) of pixel section 101, the states of switches SW201 to SW203 are as follows: Figure 34 As shown in diagram A. That is, capacitor C201 is connected to terminal T201 via switch SW201, capacitor C202 is connected to terminal T201 via switch SW202, and capacitor C203 is connected to terminal T202 via switch SW203.

[0321] In this way, the input capacitance of the pixel signal VSL is formed by capacitors C201 and C202, and the input capacitance of the reference signal RAMP is formed by capacitor C203. The AD conversion gain of the ADC including comparator 400 is then expressed by the following expression (2).

[0322] Mathematical Expression 2

[0323]

[0324] When performing AD conversion on the pixel signal VSL of pixel 150 in the (3n-1)th row (2nd row, 5th row, 8th row, ...) of pixel section 101, the states of switches SW201 to SW203 are as follows: Figure 34 The setup is shown in Figure B. That is, capacitor C201 is connected to terminal T201 via switch SW201, capacitor C202 is connected to terminal T202 via switch SW202, and capacitor C203 is connected to terminal T201 via switch SW203.

[0325] In this way, the input capacitance of the pixel signal VSL is formed by capacitors C201 and C203, and the input capacitance of the reference signal RAMP is formed by capacitor C202. The AD conversion gain of the ADC including comparator 400 is represented by the following expression (3).

[0326] Mathematical Expression 3

[0327]

[0328] When performing AD conversion on the pixel signal VSL of pixel 150 in the 3nth row (3rd row, 6th row, 9th row, ...) of pixel unit 101, the states of switches SW201 to SW203 are as follows: Figure 34The configuration is shown in Figure C. That is, capacitor C201 is connected to terminal T202 via switch SW201, capacitor C202 is connected to terminal T201 via switch SW202, and capacitor C203 is connected to terminal T201 via switch SW203.

[0329] In this way, the input capacitance of the pixel signal VSL is formed by capacitors C202 and C203, and the input capacitance of the reference signal RAMP is formed by capacitor C201. The AD conversion gain of the ADC including comparator 400 is then represented by the following expression (4).

[0330] Mathematical Expression 4

[0331]

[0332] As described above, each time the pixel row in the pixel section 101, which is the target of the AD conversion of the pixel signal VSL, is switched, the combination of capacitors for the input capacitor of the pixel signal VSL (hereinafter referred to as the capacitors for the pixel signal) and the combination of capacitors for the input capacitor of the reference signal RAMP (hereinafter referred to as the capacitors for the reference signal) are changed. Since the ratio between the number of capacitors for the pixel signal and the number of capacitors for the reference signal remains constant at this time, the AD conversion gain remains substantially constant.

[0333] Meanwhile, due to the variation in the combination of capacitors used for the pixel signal and the combination of capacitors used for the reference signal for each pixel row, the capacitance error of capacitors C201 to C203 for each pixel row causes an AD conversion gain mismatch between pixel columns. Thus, because the AD conversion gain mismatch between pixel columns is dispersed and becomes uneven, the appearance of vertical stripes in the image data is suppressed.

[0334] In image sensors of related technologies, a strategy of increasing the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP is employed in some cases to suppress vertical stripes in the image data caused by the mismatch in the AD conversion gain. However, since capacitive elements often do not benefit from the fine processing in integrated circuit technology and have low area efficiency, there are concerns that this will increase the size of the image sensor.

[0335] At the same time, without increasing the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP in the comparator 400, the increase in the size of the image sensor 100 can be suppressed.

[0336] The number of capacitors arranged in the comparator 400 is not limited to three, and can be set to two, four or more.

[0337] The design values ​​of all capacitors in comparator 400 do not need to be set to be equal. The combination of capacitors used for the pixel signal and the combination of capacitors used for the reference signal are changed so that even if the design values ​​of the individual capacitors are not constant, the ratio between the input capacitance of the pixel signal VSL and the input capacitance of the reference signal RAMP remains essentially constant.

[0338] Although examples of changing the combination of capacitors for the pixel signal and the combination of capacitors for the reference signal for each pixel column have been described above, the effect of suppressing the appearance of vertical stripes in the image data can also be achieved by changing said combinations at least once or more in the middle of the pixel column. For example, the combination of capacitors for the pixel signal and the combination of capacitors for the reference signal can be changed for every two or more pixel columns. However, as the number of times the combination of capacitors for the pixel signal and the combination of capacitors for the reference signal is changed increases, the dispersion of the A / D conversion gain mismatch between pixel columns increases, and the vertical stripes appearing in the image data are further suppressed.

[0339] For example, one of the capacitor combinations used for pixel signals and the capacitor combinations used for reference signals can be changed, while the other remains fixed. For instance, the capacitor combination used for pixel signals can be changed by sequentially selecting two of the three capacitors, while the capacitor used for the reference signal remains fixed.

[0340] <<6. Variations of the Third Embodiment>>

[0341] Next, we will refer to Figures 35 to 38 A variation of the third embodiment is described.

[0342] In this variant, two adjacent pixel arrays share comparator 400-1 (included in the ADC) and comparator 400-2 (included in the ADC).

[0343] Specifically, comparator 400-1 and comparator 400-2 have the same characteristics as... Figure 33 The comparator 400 shown has the same configuration. In the figure, for each part of comparator 400-1, "-1" or "1" is added to the end of the reference numeral, and for each part of comparator 400-2, "-2" or "2" is added to the end of the reference numeral.

[0344] and Figure 33 Compared to the configuration shown, switches SW211-1 and SW211-2 have been added.

[0345] Terminal 0 of switch SW211-1 is connected to terminal 1 of switches SW201-1 to SW203-1, terminal 1 is connected to terminal T201-1, and terminal 3 is connected to terminal T201-2.

[0346] Terminal 0 of switch SW211-2 is connected to terminal 1 of switches SW201-2 to SW203-2, terminal 1 is connected to terminal T201-1, and terminal 3 is connected to terminal T201-2.

[0347] For example, the states of switches SW211-1 and SW211-2 are controlled by timing control circuit 102.

[0348] Terminal T202 is connected to terminals 3 of switches SW201-1 to SW203-2 and terminals 3 of switches SW201-2 to SW203-2.

[0349] For example, the pixel signal VSL1 of each pixel 150 in the first column of the pixel unit 101 is input to the terminal T201-1, and, for example, the pixel signal VSL2 of each pixel 150 in the second column of the pixel unit 101 is input to the terminal T201-2.

[0350] Then, with Figure 33 The comparator 400 shown controls the ratio between the input capacitance of pixel signal VSL1 and the input capacitance of reference signal RAMP, and the ratio between the input capacitance of pixel signal VSL2 and the input capacitance of reference signal RAMP, by controlling the states of switches SW201-1 to SW203-1 and switches SW201-2 to SW203-2.

[0351] For example, such as Figures 36 to 38 As shown, vertical stripes appearing in image data are suppressed by controlling the states of switches SW201-1 to SW203-1, switches SW202-2 to SW203-2, switch SW211-1, and switch SW211-2.

[0352] For example, when performing AD conversion on pixel signals VSL1 and VSL2 in the 6n-5th rows (first row, seventh row, thirteenth row, ...) of pixel section 101, each switch is set as follows: Figure 36 The state shown in A.

[0353] In other words, capacitor C201-1 is connected to terminal 202 via switch SW201-1. Capacitor C202-1 is connected to terminal T201-2 via switches SW202-1 and SW211-1. Capacitor C203-1 is connected to terminal T201-2 via switches SW203-1 and SW211-1. In this way, the input capacitance of pixel signal VSL2 is formed by capacitors C202-1 and C203-1, and the input capacitance of reference signal RAMP is formed by capacitor C201-1.

[0354] Furthermore, capacitor C201-2 is connected to terminal T202 via switch SW201-2. Capacitor C202-2 is connected to terminal T201-1 via switches SW202-2 and SW211-2. Capacitor C203-2 is connected to terminal T201-1 via switches SW203-2 and SW211-2. In this way, the input capacitance of pixel signal VSL1 is formed by capacitors C202-2 and C203-2, and the input capacitance of reference signal RAMP is formed by capacitor C201-2.

[0355] When performing AD conversion on pixel signals VSL1 and VSL2 in the 6n-4th row (second row, eighth row, fourteenth row, ...) of pixel section 101, each switch is set as follows: Figure 36 The state shown in B.

[0356] In other words, capacitor C201-1 is connected to terminal T201-2 via switches SW201-1 and SW211-1. Capacitor C202-1 is connected to terminal T202 via switch SW202-1. Capacitor C203-1 is connected to terminal T201-2 via switches SW203-1 and SW211-1. In this way, the input capacitance of pixel signal VSL2 is formed by capacitors C201-1 and C203-1, and the input capacitance of reference signal RAMP is formed by capacitor C202-1.

[0357] Furthermore, capacitor C201-2 is connected to terminal T201-1 via switches SW201-2 and SW211-2. Capacitor C202-2 is connected to terminal T202 via switch SW202-2. Capacitor C203-2 is connected to terminal T201-1 via switches SW203-2 and SW211-2. In this way, the input capacitance of pixel signal VSL1 is formed by capacitors C201-2 and C203-2, and the input capacitance of reference signal RAMP is formed by capacitor C202-2.

[0358] When performing AD conversion on pixel signals VSL1 and VSL2 in the 6n-3rd row (3rd row, 9th row, 15th row, ...) of pixel section 101, each switch is set as follows: Figure 37 The state shown in C.

[0359] In other words, capacitor C201-1 is connected to terminal T201-2 via switches SW201-1 and SW211-1. Capacitor C202-1 is connected to terminal T201-2 via switches SW202-1 and SW211-1. Capacitor C203-1 is connected to terminal T202 via switch SW203-1. In this way, the input capacitance of pixel signal VSL2 is formed by capacitors C201-1 and C202-1, and the input capacitance of reference signal RAMP is formed by capacitor C203-1.

[0360] Furthermore, capacitor C201-2 is connected to terminal T201-1 via switches SW201-2 and SW211-2. Capacitor C202-2 is connected to terminal T201-1 via switches SW202-2 and SW211-2. Capacitor C203-2 is connected to terminal T202 via switch SW203-2. In this way, the input capacitance of pixel signal VSL1 is formed by capacitors C201-2 and C202-2, and the input capacitance of reference signal RAMP is formed by capacitor C203-2.

[0361] When performing AD conversion on pixel signals VSL1 and VSL2 in the 6n-2th row (4th row, 10th row, 16th row, ...) of pixel section 101, each switch is set as follows: Figure 37 The state shown by D.

[0362] In other words, capacitor C201-1 is connected to terminal T202 via switch SW201-1. Capacitor C202-1 is connected to terminal T202-1 via switches SW202-1 and SW211-1. Capacitor C203-1 is connected to terminal T201-1 via switches SW203-1 and SW211-1. In this way, the input capacitance of pixel signal VSL1 is formed by capacitors C202-1 and C203-1, and the input capacitance of reference signal RAMP is formed by capacitor C201-1.

[0363] Furthermore, capacitor C201-2 is connected to terminal T202 via switch SW201-2. Capacitor C202-2 is connected to terminal T201-2 via switches SW202-2 and SW211-2. Capacitor C203-2 is connected to terminal T201-2 via switches SW203-2 and SW211-2. In this way, the input capacitance of pixel signal VSL2 is formed by capacitors C202-2 and C203-2, and the input capacitance of reference signal RAMP is formed by capacitor C201-2.

[0364] When performing AD conversion on pixel signals VSL1 and VSL2 in the 6n-1th row (5th row, 11th row, 17th row, ...) of pixel section 101, each switch is set as follows: Figure 38 The state shown in E.

[0365] In other words, capacitor C201-1 is connected to terminal T201-1 via switches SW201-1 and SW211-1. Capacitor C202-1 is connected to terminal T202 via switch SW202-1. Capacitor C203-1 is connected to terminal T201-1 via switches SW203-1 and SW211-1. In this way, the input capacitance of pixel signal VSL1 is formed by capacitors C201-1 and C203-1, and the input capacitance of reference signal RAMP is formed by capacitor C202-1.

[0366] Furthermore, capacitor C201-2 is connected to terminal T201-2 via switches SW201-2 and SW211-2. Capacitor C202-2 is connected to terminal T202 via switch SW202-2. Capacitor C203-2 is connected to terminal T201-2 via switches SW203-2 and SW211-2. In this way, the input capacitance of pixel signal VSL2 is formed by capacitors C201-2 and C203-2, and the input capacitance of reference signal RAMP is formed by capacitor C202-2.

[0367] When performing AD conversion on pixel signals VSL1 and VSL2 in the 6nth row (sixth row, twelfth row, eighteenth row, ...) of pixel section 101, each switch is set as follows: Figure 38 The state shown by F.

[0368] In other words, capacitor C201-1 is connected to terminal T201-1 via switches SW201-1 and SW211-1. Capacitor C202-1 is connected to terminal T201-1 via switches SW202-1 and SW211-1. Capacitor C203-1 is connected to terminal T202 via switch SW203-1. In this way, the input capacitance of pixel signal VSL1 is formed by capacitors C201-1 and C202-1, and the input capacitance of reference signal RAMP is formed by capacitor C203-1.

[0369] Furthermore, capacitor C201-2 is connected to terminal T201-2 via switches SW201-2 and SW211-2. Capacitor C202-2 is connected to terminal T201-2 via switches SW202-2 and SW211-2. Capacitor C203-2 is connected to terminal T202 via switch SW203-2. In this way, the input capacitance of pixel signal VSL2 is formed by capacitors C201-2 and C202-2, and the input capacitance of reference signal RAMP is formed by capacitor C203-2.

[0370] In this way, by sharing two ADCs (comparator 400) between the two pixel arrays and switching the combination of the pixel column and the ADC in the middle of the pixel column, the patterns of the capacitor combinations for the pixel signal and the capacitor combinations for the reference signal are increased. Therefore, the dispersion of the mismatch in AD conversion gain between pixel columns is further increased, and the appearance of vertical stripes in the image data is further suppressed.

[0371] Furthermore, three or more ADCs (comparator 400) can be shared by three or more pixel columns.

[0372] Furthermore, by changing the combination of the middle pixel column and the ADC at least once or multiple times, the appearance of vertical stripes in the image data can be suppressed. However, as the number of changes to the combination of pixel column and ADC increases, the dispersion of the AD conversion gain mismatch between pixel columns increases, thus further suppressing the appearance of vertical stripes in the image data.

[0373] Furthermore, for example, by changing only the combination of the pixel array and the ADC without changing the combination of the capacitors for the pixel signal and the capacitors for the reference signal in the comparator 400, it is possible to suppress the appearance of vertical stripes in the image data.

[0374] <<7. Other variations>>

[0375] In the following text, variations of the above embodiments of the present invention will be described.

[0376] In addition to the aforementioned image sensors, embodiments of the present invention can also generally be applied to image sensors that perform AD conversion on pixel signals by using pixel signals and a reference signal with a ramp waveform.

[0377] Furthermore, the 150 pixel configuration is not limited to Figure 2 The configuration shown is available and can be changed arbitrarily.

[0378] Although an example of setting an ADC for each pixel column in pixel section 101 has been described above, the unit for setting the ADC can be changed arbitrarily. For example, an ADC can be set for each pixel 150, an ADC can be set for every two or more pixel columns, or an ADC can be set for each predetermined area in pixel section 101.

[0379] <<8. Examples of Image Sensor Applications>>

[0380] The following will describe application examples of the image sensor that utilizes embodiments of the present invention.

[0381] <Examples of image sensor usage>

[0382] Figure 39 An example of the use of the above image sensor is shown.

[0383] For example, the image sensor described above can be used to detect various types of light, such as visible light, infrared light, ultraviolet light, or X-rays.

[0384] - Devices used for appreciating captured images, such as digital cameras and portable devices with camera functions.

[0385] - Devices used in transportation, such as vehicle sensors that capture images of the front and rear of a car, the surrounding environment, the interior of the car, etc., surveillance cameras that monitor moving vehicles and roads, and distance sensors that measure the distance between vehicles, etc., are used for safe driving (e.g., automatic stopping), identifying the driver's condition, etc.

[0386] - Devices used for home appliances (such as televisions, refrigerators, and air conditioners) to capture images of the user's gestures and perform appliance operations based on those gestures.

[0387] - Devices used in medical care and healthcare, such as endoscopes and devices that perform angiography by receiving infrared light.

[0388] - Devices used for security, such as surveillance cameras for crime prevention and cameras for personal authentication.

[0389] - Devices used for beauty care, such as skin measurement devices that take images of the skin and microscopes that take images of the scalp.

[0390] - Devices used for sports, such as action cameras and wearable cameras for sports.

[0391] - Equipment used in agriculture, such as cameras used to monitor the condition of fields and crops.

[0392] <Application Examples of Electronic Devices Using Image Sensors>

[0393] Figure 40 This is a diagram illustrating a configuration example of an electronic device 500 that utilizes an image sensor.

[0394] Electronic device 500 includes imaging devices such as digital still cameras or video cameras, or mobile terminal devices such as smartphones or tablets.

[0395] exist Figure 40 In this device, electronic device 500 includes a lens 501, an image sensor 502, a DSP circuit 503, a frame memory 504, a display unit 505, a recording unit 506, an operation unit 507, and a power supply unit 508. In electronic device 500, the DSP circuit 503, frame memory 504, display unit 505, recording unit 506, operation unit 507, and power supply unit 508 are interconnected via a bus 509.

[0396] in addition, Figure 1 The image sensor 100 shown can be applied to the image sensor 502.

[0397] DSP circuit 503 is a signal processing circuit that processes signals provided from image sensor 502. DSP circuit 503 outputs image data obtained by processing signals from image sensor 502. Frame memory 504 temporarily stores the image data processed by DSP circuit 503 in units of frames.

[0398] The display unit 505 is formed by a panel display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays video images or still images captured by the image sensor 502. The recording unit 506 records the image data of the video images or still images captured by the image sensor 502 in a recording medium such as a semiconductor memory or a hard disk.

[0399] The operation unit 507 responds to user operations by outputting operation commands for various functions of the electronic device 500. The power supply unit 508 appropriately supplies various power sources, which serve as the operating power for the DSP circuit 503, frame memory 504, display unit 505, recording unit 506, and operation unit 507, to these power supply targets.

[0400] <Application Examples of Moving Objects>

[0401] For example, the technology according to embodiments of the invention is implemented as a device mounted on any type of moving object, such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, and robot.

[0402] Figure 41 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to embodiments of the present invention can be applied.

[0403] The vehicle control system 12000 includes multiple electronic control units connected via a communication network 12001. Figure 41 In the example shown, the vehicle control system 12000 includes a driveline control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0404] The driveline control unit 12010 controls the operation of equipment related to the vehicle's driveline according to various programs. For example, the driveline control unit 12010 is used as a control device for the following devices: a drive force generating device (e.g., an internal combustion engine or drive motor) that generates vehicle driving force, a drive force transmission mechanism that transmits driving force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates vehicle braking force, etc.

[0405] The body system control unit 12020 controls the operation of various devices connected to the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power window devices, or various lights (such as headlights, reverse lights, brake lights, hazard lights, or fog lights). In this case, the body system control unit 12020 can receive radio waves or signals from various switches transmitted from a portable device in place of a key. The body system control unit 12020 receives these radio waves or signals and controls the door locking devices, power window devices, lights, etc.

[0406] The exterior information detection unit 12030 detects information about the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, road symbols, etc., based on the received images.

[0407] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal based on the amount of light received. The imaging unit 12031 can output the electrical signal as an image or distance measurement information. Furthermore, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0408] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 may include, for example, a camera that images the driver. The in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver state detection unit 12041.

[0409] For example, the microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive line control unit 12010. For example, the microcomputer 12051 can perform cooperative control to execute functions of advanced driver assistance systems (ADAS), including vehicle collision avoidance, impact reduction, distance-based following, constant speed driving, vehicle collision warning, lane departure warning, etc.

[0410] Furthermore, the microcomputer 12051 can control the drive force generating device, steering mechanism, braking device, etc., based on information about the area around the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040. Therefore, regardless of the driver's operation, coordinated control can be performed to achieve autonomous driving, etc.

[0411] In addition, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the vehicle in front or oncoming vehicles detected by the external information detection unit 12030, and can perform cooperative control for anti-glare, such as switching from high beam to low beam.

[0412] The audio and image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying passengers of the vehicle or the exterior of the vehicle. Figure 41 In the example, audio speaker 12061, display unit 12062, and device panel 12063 are illustrated as output devices. For example, display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0413] Figure 42 This is a diagram showing an example of the mounting position of the imaging unit 12031.

[0414] exist Figure 42 In the vehicle 12100, imaging units 12101, 12102, 12103, 12104 and 12105 are imaging units 12031.

[0415] Imaging units 12101, 12102, 12103, 12104, and 12105 are located, for example, on the upper part of the windshield in the front nose, rearview mirrors, rear bumper, rear door, and passenger compartment of vehicle 12100. Imaging unit 12101 attached to the front nose and imaging unit 12105 attached to the upper part of the windshield in the passenger compartment primarily acquire images of the area in front of vehicle 12100. Imaging units 12102 and 12103 attached to the rearview mirrors primarily acquire images of the side areas of vehicle 12100. Imaging unit 12104 attached to the rear bumper or rear door primarily acquires images of the rear area of ​​vehicle 12100. The front images acquired by imaging units 12101 and 12105 are mainly used for detecting vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0416] in addition, Figure 42Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 attached to the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 attached to the rearview mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 attached to the rear bumper or rear door. For example, superimposing the image data captured by imaging units 12101 to 12104 can provide a top-down view of the vehicle 12100.

[0417] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including multiple image sensors, or may be an image sensor including pixels for phase difference detection.

[0418] For example, based on distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can extract a three-dimensional object traveling at a predetermined speed (e.g., above 0 km / h) in substantially the same direction as vehicle 12100 as the preceding vehicle by acquiring the distances of each three-dimensional object within the imaging range 12111 to 12114 and the time-varying distances (relative speed to vehicle 12100). Specifically, it can use the closest three-dimensional object on the road on which vehicle 12100 is traveling. Furthermore, microcomputer 12051 can pre-set a guaranteed distance to the preceding vehicle and execute automatic braking control (including follow-stop control) or automatic acceleration control (including follow-oscillation control). In this way, cooperative control for autonomous driving, etc., can be performed, allowing the vehicle to drive autonomously without considering any driver input.

[0419] For example, the microcomputer 12051 can classify and extract three-dimensional object data about a three-dimensional object into other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles based on distance information obtained from imaging units 12101 to 12104, and can use these other three-dimensional objects to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that can be observed by the driver of vehicle 12100 and obstacles that are difficult to observe. Then, the microcomputer 12051 can determine the collision risk representing the danger of collision with each obstacle, and output a warning to the driver via audio speaker 12061 or display unit 12062 if the collision risk is set to be equal to or greater than a set value and a collision is possible, or perform collision-assisted driving by performing forced deceleration or avoidance steering via drive line control unit 12010.

[0420] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. For example, a pedestrian can be identified by the following steps: extracting feature points from the captured images of the imaging units 12101 to 12104, which are used as infrared cameras, and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether a pedestrian exists. The microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104. When a pedestrian is identified, the audio and image output unit 12052 controls the display unit 12062 to overlay a rectangular outline for emphasis on the identified pedestrian. In addition, the audio and image output unit 12052 controls the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0421] Examples of vehicle control systems to which the technology according to embodiments of the present invention can be applied have been described above. Embodiments of the technology according to the present invention can be applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The image sensor 100 shown can be applied to the imaging unit 12031. By applying the technology according to an embodiment of the present invention to the imaging unit 12031, the power consumption of the imaging unit 12031 can be reduced, and thus the power consumption of the vehicle can be reduced.

[0422] <Configuration examples of stacked solid-state imaging devices to which the technology according to embodiments of the present invention can be applied>

[0423] Figure 43 This is a diagram illustrating an overview of a configuration example of a stacked solid-state imaging device to which the technology according to embodiments of the present invention can be applied.

[0424] Figure 43 Figure A illustrates a schematic configuration example of a non-stacked solid-state imaging device. Figure 43 As shown in Figure A, the solid-state imaging device 23010 includes a wafer (semiconductor substrate) 23011. Pixel regions 23012 with pixels arranged in an array, control circuitry 23013 performing pixel driving and various other controls, and logic circuitry 23014 for signal processing are disposed on the wafer 23011.

[0425] Figure 43 Figures B and C illustrate schematic configuration examples of stacked solid-state imaging devices. Figure 43 As shown in B and C, the solid-state imaging device 23020 includes two wafers having a sensor wafer 23021 and a logic wafer 23024, which are stacked and electrically connected to each other and configured as a single semiconductor chip.

[0426] exist Figure 43 In B, pixel region 23012 and control circuit 23013 are disposed on sensor chip 23021, and logic circuit 23014 including signal processing circuit for performing signal processing is disposed on logic chip 23024.

[0427] exist Figure 43 In C, pixel region 23012 is disposed on sensor chip 23021, and control circuit 23013 and logic circuit 23014 are disposed on logic chip 23024.

[0428] Figure 44 This is a cross-sectional view showing a first configuration example of the stacked solid-state imaging device 23020.

[0429] A photodiode (PD), a floating diffuser (FD), a MOSFET constituting a pixel used as pixel region 23012, and a control circuit 23013 are formed on the sensor wafer 23021. Furthermore, a wiring layer 23101 comprising multiple layers (i.e., three layers of wiring 23110 in this example) is formed on the sensor wafer 23021. The control circuit 23013 (used as MOSFET) can be configured on a logic wafer 23024 instead of the sensor wafer 23021.

[0430] The Tr constituting the logic circuit 23014 is formed on the logic wafer 23024. Furthermore, a wiring layer 23161 comprising multiple layers (i.e., three layers of wiring 23170 in this example) is formed on the logic wafer 23024. Moreover, in the logic wafer 23024, contact holes 23171 are formed on their inner wall surfaces, and the contact holes 23171 are filled with connection conductors 23173 that connect to the wiring 23170, etc.

[0431] Sensor chip 23021 and logic chip 23024 are attached to each other such that wiring layers 23101 and 23161 face each other, thus forming a stacked solid-state imaging device 23020 in which sensor chip 23021 and logic chip 23024 are stacked. A film 23191, such as a protective film, is formed on the surface on which sensor chip 23021 and logic chip 23024 are attached.

[0432] A contact hole 23111 is formed in the sensor chip 23021, extending from the rear side (the side where light is incident on the PD) (top side), passing through the sensor chip 23021, and reaching the uppermost layer wiring 23170 of the logic chip 23024. Furthermore, in the sensor chip 23021, a contact hole 23121 is formed near the contact hole 23111, extending from the rear side of the sensor chip 23021 and reaching the first layer wiring 23110. An insulating film 23112 is formed on the inner wall surface of the contact hole 23111, and an insulating film 23122 is formed on the inner wall surface of the contact hole 23121. Furthermore, contact holes 23111 and 23121 are filled with connecting conductors 23113 and 23123, respectively. Connecting conductors 23113 and 23123 are electrically connected to each other on the back side of sensor chip 23021, so sensor chip 23021 and logic chip 23024 are electrically connected to each other via wiring layer 23101, contact hole 23121, contact hole 23111 and wiring layer 23161.

[0433] Figure 45 This is a cross-sectional view showing a second configuration example of the stacked solid-state imaging device 23020.

[0434] In a second configuration example of the solid-state imaging device 23020, the sensor chip 23021 (wiring layer 23101 (wiring 23110)) and the logic chip 23024 (wiring layer 23161 (wiring 23170)) are electrically connected to each other through a contact hole 23211 formed in the sensor chip 23021.

[0435] In other words, in Figure 45 In this configuration, contact hole 23211 extends from the rear side of sensor chip 23021, passes through sensor chip 23021, reaches the uppermost wiring 23170 of logic chip 23024, and reaches the uppermost wiring 23110 of sensor chip 23021. An insulating film 23212 is formed on the inner wall surface of contact hole 23211, and contact hole 23211 is filled with connecting conductor 23213. Figure 44 In the process, the sensor chip 23021 and the logic chip 23024 are electrically connected to each other via two contact holes 23111 and 23121, while... Figure 45 In this circuit, the sensor chip 23021 and the logic chip 23024 are electrically connected to each other via a contact hole 23211.

[0436] Figure 46 This is a cross-sectional view showing a third configuration example of the stacked solid-state imaging device 23020.

[0437] Figure 46 Solid-state imaging device 23020 and Figure 44 The difference between the solid-state imaging device 23020 (in which a film 23191, such as a protective film, is formed on the surface on which the sensor chip 23021 and the logic chip 23024 are attached to each other) is that no film 23191, such as a protective film, is formed on the surface on which the sensor chip 23021 and the logic chip 23024 are attached to each other.

[0438] Figure 46 The solid-state imaging device 23020 is configured such that the sensor chip 23021 and the logic chip 23024 overlap, such that the wirings 23110 and 23170 are in direct contact with each other, and the wirings 23110 and 23170 are directly bonded by heating while the necessary weight is applied.

[0439] Figure 47 This is a cross-sectional view illustrating another configuration example of a stacked solid-state imaging device to which the technology according to embodiments of the present invention can be applied.

[0440] exist Figure 47 In the solid-state imaging device 23401, there is a three-layer stacked structure, which includes three wafer stacks: sensor wafer 23411, logic wafer 23412, and memory wafer 23413.

[0441] The memory chip 23413 includes, for example, memory circuitry that stores data temporarily needed in signal processing performed by the logic chip 23412.

[0442] exist Figure 47 Although the logic chip 23412 and the memory chip 23413 are stacked under the sensor chip 23411 in the described order, the logic chip 23412 and the memory chip 23413 can be stacked in the reverse order, that is, the memory chip 23413 and the logic chip 23412 can be stacked under the sensor chip 23411 in the described order.

[0443] exist Figure 47 In the sensor chip 23411, the source / drain regions of the PD and the pixel Tr, which are used as pixel photoelectric conversion units, are formed on the sensor chip 23411.

[0444] A gate electrode is formed around the PD, a gate insulating film is placed between the PD and the gate electrode, and pixels Tr 23421 and Tr 23422 are formed by a pair of source / drain regions formed through the gate electrode.

[0445] The pixel Tr 23421 adjacent to PD is the transmission Tr, and one of the pair of source / drain regions constituting pixel Tr 23421 is FD.

[0446] An interlayer insulating film is formed on the sensor wafer 23411, and contact holes are formed in the interlayer insulating film. A connection conductor 23431 connecting to pixels Tr 23421 and Tr 23422 is formed in the contact holes.

[0447] In addition, a wiring layer 23433, including a multilayer wiring 23432 connected to the connecting conductor 23431, is formed in the sensor chip 23411.

[0448] Aluminum pads 23434, serving as electrodes for external connections, are formed on the bottom layer of wiring layer 23433 of sensor chip 23411. In other words, in sensor chip 23411, aluminum pads 23434 are formed closer to the bonding surface 23440 of logic chip 23412 than wiring 23432. Aluminum pads 23434 serve as one end of wiring associated with input and output of external signals.

[0449] In addition, contacts 23441 for electrical connection with logic chip 23412 are formed on sensor chip 23411. Contact 23441 is connected to contact 23451 of logic chip 23412 and also to aluminum pad 23442 of sensor chip 23411.

[0450] In sensor chip 23411, pad hole 23443 is formed to extend from the rear (upper) side of sensor chip 23411 and reach aluminum pad 23442.

[0451] The techniques described in the embodiments of the present invention can be applied to the above-described solid-state imaging devices.

[0452] Furthermore, the embodiments of the present invention are not limited to the above embodiments, and various changes can be made as long as they are within the scope of the present invention.

[0453] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations can be made according to design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

[0454] Alternatively, the present invention can also be configured as follows.

[0455] (1) An imaging device, comprising:

[0456] Pixels, which are configured to generate pixel signals; and

[0457] A comparator, comprising:

[0458] A first capacitor configured to receive a pixel signal; a second capacitor configured to receive a reference signal; a node connected to the first capacitor and the second capacitor; a first transistor having a gate connected to the node; a second transistor connected to the first transistor; and a third capacitor connected between the gate of the second transistor and a first line provided with a first voltage.

[0459] (2) The imaging device according to (1), wherein the first capacitor and the second capacitor are connected to the terminal of the first transistor via a first switch, and wherein the third capacitor is connected to the terminal of the second transistor via a second switch.

[0460] (3) The imaging device according to (2), wherein the terminal of the first transistor is a drain and the terminal of the second transistor is a drain.

[0461] (4) The imaging device according to (2), wherein the first switch and the second switch are controlled by the same drive signal.

[0462] (5) The imaging device according to (2), wherein the first switch and the second switch are controlled by different drive signals.

[0463] (6) The imaging device according to (1), wherein the comparator further includes a third transistor and a fourth transistor, the third transistor being connected to the first transistor and a second line provided with a second voltage different from the first voltage, and the fourth transistor being connected to the second transistor and the second line.

[0464] (7) The imaging device according to (1), wherein the comparator includes a multi-stage amplifier.

[0465] (8) The imaging device according to (7), wherein the comparator further includes a third transistor having a gate connected to the second transistor.

[0466] (9) The imaging device according to (8), wherein the third transistor is connected to a third line provided with a third voltage different from the first voltage and the second voltage.

[0467] (10) The imaging device according to (1), wherein the first capacitor and the second capacitor are variable capacitors.

[0468] (11) An imaging device comprising:

[0469] Pixels, which are configured to generate pixel signals; and

[0470] A comparator, comprising:

[0471] The first capacitor is configured to receive pixel signals;

[0472] The second capacitor is configured to receive a reference signal;

[0473] A node that is connected to the first capacitor and the second capacitor;

[0474] A first transistor having a gate connected to the node;

[0475] A second transistor is disposed between a first line provided with a first fixed voltage and the first transistor;

[0476] Wherein, the first transistor is connected between the second transistor and a second line provided with a second fixed voltage different from the first fixed voltage, and

[0477] The gate of the second transistor is isolated from the node.

[0478] (12) The imaging device according to (11), wherein the comparator further includes a third transistor connected to a third line provided with a third fixed voltage and the node.

[0479] (13) The imaging device according to (12), wherein the third transistor is connected to the node via a switch.

[0480] (14) The imaging device according to (12), wherein the third fixed voltage is equal to the second fixed voltage.

[0481] (15) The imaging device according to (12), wherein the comparator further includes a third capacitor that connects the third transistor to the first line.

[0482] (16) The imaging device according to (11), wherein the comparator includes a multi-stage amplifier.

[0483] (17) The imaging device according to (16), wherein the comparator further includes a third transistor having a gate connected to the second transistor.

[0484] (18) The imaging device according to (17), wherein the third transistor is connected to a third line provided with a third fixed voltage different from the first voltage and the second voltage.

[0485] (19) The imaging device according to (11), wherein the first capacitor and the second capacitor are variable capacitors.

[0486] (20) The imaging device according to (11), wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

[0487] (21) An image sensor, comprising:

[0488] A pixel section, configured to include a plurality of pixels arranged therein; and

[0489] An AD conversion unit is configured to perform analog-to-digital (AD) conversion on a pixel signal based on a comparison between a first voltage of the signal and a second voltage used as a reference. The first voltage is obtained by adding the pixel signal of the pixel to a reference signal that varies linearly in the opposite direction to the pixel signal through a capacitor.

[0490] (22) The image sensor according to (1),

[0491] The AD conversion unit includes a comparator configured to compare the first voltage with the second voltage and output an output signal representing the comparison result.

[0492] (23) Based on the image sensor described in (2),

[0493] The comparator includes a first amplifier configured to provide a first voltage input to the first input and output an output signal.

[0494] (24) The image sensor according to (3) further includes:

[0495] First capacitor; and

[0496] Second capacitor,

[0497] The pixel signal is input to the first input through the first capacitor, and

[0498] The reference signal is input to the first input through the second capacitor.

[0499] (25) The image sensor according to (4),

[0500] In this embodiment, at least one of the first capacitor and the second capacitor is variable.

[0501] (26) The image sensor according to (5),

[0502] In this process, at least one of the combinations of capacitors used for the first capacitor and the combinations of capacitors used for the second capacitor is variable.

[0503] (27) The image sensor according to (6),

[0504] Specifically, an AD conversion unit is set for each pixel column in the pixel section, and

[0505] The image sensor also includes a control unit configured to, when each AD conversion unit performs an AD conversion, change one or more of the combination of capacitors for a first capacitor and the combination of capacitors for a second capacitor once or more in the middle of the pixel column.

[0506] (28) The image sensor according to (7),

[0507] In this case, multiple pixel columns share multiple AD conversion units, and

[0508] The control unit changes the combination of the pixel column and the AD conversion unit once or multiple times in the middle of the pixel column.

[0509] (29) The image sensor according to any one of (3) to (8),

[0510] The first amplifier is a differential amplifier and provides a second voltage input to the second input.

[0511] (30) The image sensor according to (9) further includes:

[0512] A capacitor is configured to be connected between the second input and the power supply or between the second input and the ground.

[0513] (31) The image sensor according to any one of (3) to (8),

[0514] The first amplifier is a single-type amplifier.

[0515] (32) The image sensor according to (11),

[0516] The first amplifier is a source-grounded amplifier.

[0517] (33) The image sensor according to (12),

[0518] When the first input and output of the first amplifier are short-circuited, the second voltage is set to the voltage of the first input.

[0519] (34) The image sensor according to (12) or (13) further includes:

[0520] A clamping circuit is configured to be connected to the output of the first amplifier.

[0521] (35) The image sensor according to any one of (12) to (14) further comprises:

[0522] A transistor configured to form a current source for the first amplifier; and

[0523] A sample and hold circuit is configured to hold a bias voltage applied to the gate of the transistor.

[0524] (36) The image sensor according to any one of (3) to (15) further comprises:

[0525] A second amplifier is configured to amplify the output of the first amplifier.

[0526] (37) The image sensor according to any one of (2) to (16),

[0527] The AD conversion unit further includes a counter configured to acquire a count value after the comparison between the first voltage and the second voltage begins, until the output signal is inverted.

[0528] (38) The image sensor according to any one of (1) to (17),

[0529] The AD conversion unit is provided for each pixel column in the pixel section.

[0530] (39) A method for controlling an image sensor, the method comprising:

[0531] Analog-to-digital (AD) conversion is performed on the pixel signal based on a comparison between a first voltage and a second voltage used as a reference. The first voltage is obtained by adding the pixel signal and a reference signal that varies linearly in the opposite direction to the pixel signal through a capacitor.

[0532] (40) An electronic device comprising:

[0533] Image sensors; and

[0534] A signal processing unit is configured to process the signal output from the image sensor.

[0535] The image sensor includes:

[0536] A pixel section, configured to include a plurality of pixels arranged therein; and

[0537] An AD conversion unit is configured to perform analog-to-digital (AD) conversion on a pixel signal based on a comparison between a first voltage of the signal and a second voltage used as a reference. The first voltage is obtained by adding the pixel signal of the pixel to a reference signal that varies linearly in the opposite direction to the pixel signal through a capacitor.

[0538] Cross-references to related applications

[0539] This application claims the benefit of Japanese priority patent application JP2017-117453, filed on June 15, 2017, the entire contents of which are incorporated herein by reference.

[0540] List of reference numerals

[0541] 100 Image Sensor

[0542] 101 pixels

[0543] 102 Timing Control Circuit

[0544] 103 Vertical Scanning Circuit

[0545] 104 DAC

[0546] 105 ADC group

[0547] 106 Horizontal Transmission Scanning Circuit

[0548] Comparators 121-1 to 121-n

[0549] Counters 122-1 to 122-n

[0550] 123-1 to 123-n latches

[0551] 200 to 200i comparators

[0552] 201,211 Differential Amplifier

[0553] 221, 231 Output Amplifiers

[0554] 300 to 300 Hz comparator

[0555] 301 Amplifier

[0556] 311 Output Amplifier

[0557] 400, 400-1, 400-2 comparators

[0558] 401, 401-1, 401-2 Comparator Circuits

[0559] C11 to C51 capacitors

[0560] C61, C62 Variable Capacitors

[0561] C71 to C131 capacitors

[0562] C141, C142 Variable Capacitors

[0563] C151 to C203 capacitors

[0564] NT11 to NT131 NMOS transistors

[0565] PT11 to PT131 PMOS transistors

[0566] SW11 to SW203 switches

Claims

1. A light detection device, comprising: Pixels, which are configured to generate pixel signals; as well as A comparator, comprising: A first capacitor is configured to receive the pixel signal; The second capacitor is configured to receive a reference signal; The first node is connected to the first capacitor and the second capacitor; A first transistor having a gate connected to the first node; The second transistor has its drain connected to the drain of the first transistor, and its source connected to a first line supplied with a first voltage. In this configuration, the source of the first transistor is connected to a second line that provides a second voltage, which is different from the first voltage. In this configuration, the first transistor and the second transistor have opposite polarities. Wherein, the gate of the second transistor is configured to receive a bias voltage, and Wherein, the first output signal is configured to be output from a second node between the drain of the first transistor and the drain of the second transistor; and A switch is connected between the first node and the second node.

2. The optical detection device according to claim 1, wherein the bias voltage is different from the first voltage and the second voltage.

3. The optical detection device according to claim 1, wherein, The gate of the second transistor is configured to receive the bias voltage via a switch.

4. The optical detection device according to claim 1, wherein, The third capacitor is connected to the gate of the first line and the second transistor.

5. The optical detection device according to claim 1, wherein, The first capacitor and the second capacitor are variable.

6. The optical detection device according to claim 1, wherein, The third transistor is connected in series with the first transistor and the second transistor.

7. The optical detection device according to claim 6, wherein, The gate of the third transistor is isolated from the first node.

8. The optical detection device according to claim 1, wherein, The comparator includes a third transistor connected to a third line provided with a third voltage, the gate of the third transistor being configured to receive the first output signal.

9. The optical detection device according to claim 8, wherein, The third voltage is equal to the second voltage.

10. The optical detection device according to claim 8, wherein, The third voltage is equal to the first voltage.

11. The optical detection device according to claim 8, wherein, The comparator includes a fourth transistor connected to the third transistor and a switch connected between the gate and drain of the fourth transistor.

12. The optical detection device according to claim 11, wherein, One end of the third capacitor is connected to the gate of the fourth transistor, and the other end of the third capacitor receives the first voltage.

13. The optical detection device according to claim 11, wherein, The second output signal is configured to be output from the node between the third transistor and the fourth transistor.

14. An electronic device comprising a light detection device as claimed in any one of claims 1-13.

Images