Wafer exposure processing method, device and storage medium

Abstract

The disclosure provides a processing method, device and storage medium for exposure. The disclosure relates to the technical field of semiconductors. The processing method comprises: a to-be-exposed surface, the to-be-exposed surface is provided with N adjacent exposure units, wherein N is a positive integer greater than or equal to 2; a pattern of each exposure unit is exposed and spliced by using at least one first mask and at least one second mask; wherein the at least one second mask comprises a first pattern and a second pattern; the first pattern and the second pattern are projected on two adjacent exposure units in an exposure process, respectively. The processing method optimizes the exposure process. When applied to wafer exposure, after the exposure units on the to-be-exposed surface of the wafer are determined, the first mask and the second mask are matched to expose the corresponding exposure units on the wafer according to a certain arrangement rule, which not only saves the use amount of masks, but also reduces the number of exposures, thereby improving the wafer exposure efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a wafer exposure processing method and device and storage medium. BACKGROUND

[0002] In the related art, as shown in FIG. 1, Figure 1 Figure 1 is a Chip-on-Wafer-on-Substrate (CoWoS) structure schematic diagram in the related art. Traditional Two-and-a-half-dimension (2.5D) Integrated Circuit (IC) integrates memory / logic / small chips in a single package to achieve better performance and lower power consumption, and a TSV Si Interposer (TSI) 2 can serve as an interconnection between a chip 1, a substrate 3, and a Printed circuit boards (PCB) 4. The TSV Si Interposer 2 includes Through Silicon Vias (TSV) and multi-layer ReDistribution Layer (RDL). In the wafer-level packaging design, when processing a large-size TSV Si Interposer 2, multiple masks need to be stitched to expand the mask size limit. As a result, a large number of masks are used, and the number of exposure times is also large, which leads to waste of mask materials and a more complicated exposure process. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] The present disclosure provides a wafer exposure processing method, device and storage medium to at least solve the above problems.

[0005] In a first aspect of the present disclosure, a wafer exposure processing method is provided, the exposure method comprising:

[0006] determining a to-be-exposed surface, the to-be-exposed surface being pre-configured with N adjacent exposure units, wherein N is a positive integer greater than or equal to 2;

[0007] the pattern of each exposure unit is exposed and spliced using at least one first type mask and at least one second type mask; wherein at least one second type mask includes a first pattern and a second pattern; the first pattern and the second pattern are respectively projected on two adjacent exposure units in the exposure process.

[0008] ​According to some embodiments of the present disclosure, the pattern of each of the exposure units is formed by exposure and splicing using at least one first type mask and at least one second type mask, comprising:

[0009] The full-size mask exposure area of the first exposure unit of the two adjacent exposure units is exposed using at least one of the first type masks;

[0010] The full-size mask exposure area of the second exposure unit of the two adjacent exposure units is exposed using at least one of the first type masks;

[0011] The adjusted-size mask exposure area of the first exposure unit and the adjusted-size mask exposure area of the second exposure unit are jointly exposed using at least one of the second type masks; wherein the first pattern is projected on the adjusted-size mask exposure area of the first exposure unit during exposure, and the second pattern is projected on the adjusted-size mask exposure area of the second exposure unit during exposure.

[0012] According to some embodiments of the present disclosure, the second type mask further comprises a third pattern between the first pattern and the second pattern;

[0013] The pattern of each of the exposure units is formed by exposure and splicing using at least one first type mask and at least one second type mask, further comprising:

[0014] The third pattern is projected between the two adjacent exposure units during exposure to form a cutting path.

[0015] According to some embodiments of the present disclosure,

[0016] The first end of the first exposure unit of the two adjacent exposure units is exposed using a first mask, wherein the first end of the first exposure unit is an end away from the second exposure unit and comprises the full-size mask exposure area;

[0017] The second end of the second exposure unit of the two adjacent exposure units is exposed using a third mask, wherein the second end of the second exposure unit is an end away from the first exposure unit and comprises the full-size mask exposure area;

[0018] The second end of the first exposure unit and the first end of the second exposure unit of the two adjacent exposure units are jointly exposed using a fifth mask; wherein the second end of the first exposure unit is an end close to the second exposure unit and comprises the adjusted-size mask exposure area, and the first end of the second exposure unit is an end close to the first exposure unit and comprises the adjusted-size mask exposure area,

[0019] The first mask and the third mask are the first type of mask, and the fifth mask is the second type of mask.

[0020] According to some embodiments of the present disclosure, the third mask is obtained by adjusting the first mask according to a preset rule.

[0021] According to some embodiments of the present disclosure,

[0022] The upper part of the first end of the first exposure unit of the two adjacent exposure units is exposed using a first mask, and the lower part of the first end of the first exposure unit is exposed using a second mask. The first end of the first exposure unit is an end away from the second exposure unit.

[0023] The upper part of the second end of the second exposure unit of the two adjacent exposure units is exposed using a third mask, and the lower part of the second end of the second exposure unit is exposed using a fourth mask. The second end of the second exposure unit is an end away from the first exposure unit.

[0024] A fifth mask is arranged between the exposure projections of the first mask and the third mask on the surface to be exposed, and a sixth mask is arranged between the exposure projections of the second mask and the fourth mask on the surface to be exposed.

[0025] Based on the first mask, the second mask, the third mask, the fourth mask, the fifth mask, and the sixth mask, exposure is performed to obtain the corresponding exposure areas in the first exposure unit and the second exposure unit.

[0026] Similarly, the corresponding exposure areas in N exposure units are obtained.

[0027] The first mask, the second mask, the third mask, and the fourth mask are the first type of mask, and the fifth mask and the sixth mask are the second type of mask.

[0028] According to some embodiments of the present disclosure, the processing method further comprises:

[0029] The third mask is obtained by adjusting the first mask according to a preset rule, and the fourth mask is obtained by adjusting the second mask according to the preset rule; or

[0030] The third mask is obtained by adjusting the second mask according to a preset rule, and the fourth mask is obtained by adjusting the first mask according to the preset rule.

[0031] According to some embodiments of the present disclosure, based on the first mask, the second mask, the third mask, the fourth mask, the fifth mask and the sixth mask, exposure is performed to obtain the corresponding exposure area in the first exposure unit and the second exposure unit, including:

[0032] Exposure is performed once for each mask to obtain the corresponding exposure area in the first exposure unit and the second exposure unit.

[0033] According to some embodiments of the present disclosure, the fifth mask includes a first area covering the first exposure unit and a second area covering the second exposure unit; the sixth mask includes a third area covering the first exposure unit and a fourth area covering the second exposure unit; the processing method further includes:

[0034] Based on the area exposed according to the first mask, the first area after exposure, the area exposed according to the second mask and the third area after exposure, the exposure area corresponding to the first exposure unit is obtained;

[0035] Based on the area exposed according to the third mask, the second area after exposure, the area exposed according to the fourth mask and the fourth area after exposure, the exposure area corresponding to the second exposure unit is obtained.

[0036] According to some embodiments of the present disclosure, the preset rule includes:

[0037] Rotating 180 degrees or mirroring.

[0038] According to some embodiments of the present disclosure, the first pattern is the same as the second pattern.

[0039] According to some embodiments of the present disclosure, the first type of mask includes a full-size mask; and the second type of mask includes an adjusted-size mask.

[0040] According to some embodiments of the present disclosure, any two adjacent masks among the first mask, the second mask, the third mask, the fourth mask, the fifth mask and the sixth mask include an overlapping area.

[0041] According to some embodiments of the present disclosure, the overlapping width of the overlapping area ranges from 5 to 30 microns.

[0042] A second aspect of the present disclosure provides a processing device for wafer exposure, the processing device comprising:

[0043] A determination module configured to determine, according to an exposure area, adjacent N exposure units on the wafer, wherein N is a positive integer greater than or equal to 2.

[0044] an exposure module configured to expose the N exposure units m times based on at least one first type of mask and at least one second type of mask to obtain the exposure area on each of the exposure units, wherein m is a positive integer less than N*4, the first type of mask comprises a first preset size, and the second type of mask comprises a second preset size. According to some embodiments of the present disclosure, the size of the exposure unit is 50*55 mm 2 , the size of the first type of mask is 26*33 mm 2 , and the size of the second type of mask is 26*33 mm 2 .

[0045] In a third aspect of the present disclosure, a wafer exposure processing device is provided, and the wafer exposure processing device comprises:

[0046] a processor;

[0047] a memory for storing processor-executable instructions;

[0048] The processor is configured to execute the processing method according to the embodiments of the present disclosure.

[0049] In a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, and when the instructions in the storage medium are executed by a processor of a device, the device is enabled to execute the processing method according to the embodiments of the present disclosure.

[0050] Beneficial effects: The embodiments of the present disclosure provide a wafer exposure processing method, which optimizes the exposure processing process. When applied to wafer exposure, after the exposure unit on the wafer is determined, the corresponding exposure unit on the wafer is exposed according to a certain arrangement rule based on the cooperation of the first type of mask and the second type of mask, which not only saves the use amount of masks, but also reduces the number of exposures, thereby improving the wafer exposure efficiency.

[0051] Other aspects can become apparent from the following detailed description, taken in conjunction with the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. In these drawings, like reference numerals are used to represent similar elements throughout. The accompanying drawings are of some embodiments of the present disclosure, not all embodiments. Other drawings can be derived from these drawings by one skilled in the art without paying creative labor.

[0053] Figure 1is a schematic diagram of a wafer level packaging structure in the related art;

[0054] Figure 2 is a schematic diagram of a mask with a size of 22x22mm 2 is a schematic diagram of exposure of a mask;

[0055] Figure 3 is a schematic diagram of a mask with a size of 26x33mm 2 is a schematic diagram of exposure of a mask;

[0056] Figure 4 is a schematic diagram of a mask with a size of 26x33mm 2 is a schematic diagram of the number of times of exposure of a mask;

[0057] Figure 5 is a schematic diagram of a mask with a size of 26x33mm 2 is a schematic diagram of multi-row and multi-column exposure of a mask;

[0058] Figure 6 is a flowchart of a wafer exposure processing method according to an exemplary embodiment;

[0059] Figure 7 is a schematic diagram of exposure of a surface to be exposed according to an exemplary embodiment;

[0060] Figure 8 is a schematic diagram of an exposure flow of N exposure units according to an exemplary embodiment;

[0061] Figure 9 is a schematic diagram of a mask with a size of 26x33mm 2 is a schematic diagram of exposure of a mask to two exposure units;

[0062] Figure 10 is a schematic diagram of a mask with a size of 26x33mm 2 is a schematic diagram of the number of times of exposure of a mask to two exposure units;

[0063] Figure 11 is a schematic diagram of a mask with a size of 26x33mm 2 is a schematic diagram of multi-row and multi-column exposure of a mask;

[0064] Figure 12 is a schematic diagram of a wafer exposure processing device according to an exemplary embodiment;

[0065] Figure 13 is a schematic diagram of a wafer exposure processing device according to an exemplary embodiment.

[0066] Reference Signs:

[0067] 1. Chip; 2. Silicon interposer; 3. Substrate; 4. Printed circuit board; 10', First-size mask 1; 20', First-size mask 2; 30', First-size mask 3; 40', First-size mask 4; A', First-size mask overlap area; B', First-size mask exposure area; 100', Second-size mask 1; 200', Second-size mask 2; 300', Second-size mask 3; 400', Second-size mask 4; 500', Second-size mask 5; 600', Second-size mask 6; 700', Second-size mask 7; 800', Second-size mask 8; M1', Exposure unit 1; M2', Exposure unit 2; M3', Exposure unit 3; M4', Exposure unit 4; M5', Exposure unit 5; M6', Exposure unit 6; M7', Exposure unit 7; M8', Exposure unit 8;

[0068] 100, First mask; 200, Second mask; 300, Third mask; 400, Fourth mask; 500, Fifth mask; 600, Sixth mask; A, Overlapping area; B, Exposure area of ​​the first exposure unit;

[0069] M1, First Exposure Unit; M2, Second Exposure Unit; M3, Third Exposure Unit; M4, Fourth Exposure Unit; M5, Fifth Exposure Unit; M6, Sixth Exposure Unit; M7, Seventh Exposure Unit; M8, Eighth Exposure Unit. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0071] In related technologies, in wafer-level packaging design, the mask is selected for exposure processing based on the size of the silicon interposer (wafer product). Figure 2 The related technology uses a size of 22×22mm. 2 A schematic diagram of mask exposure. (e.g.) Figure 2 As shown, a first-size mask 10', a first-size mask 20', a first-size mask 30', and a first-size mask 40' can be successively exposed to form a first-size mask exposure area B', wherein a first-size mask overlap area A' is formed. Figure 3The related technology uses a size of 26×33mm. 2 A schematic diagram of mask exposure is shown below. Figure 3 As shown, based on the second-size mask 1 100', second-size mask 2 200', second-size mask 3 300', second-size mask 4 400', second-size mask 5 500', second-size mask 6 600', second-size mask 7 700', and second-size mask 8 800', according to... Figure 3 As shown, successive exposures can be performed. Figure 3 The exposure method shown requires the following number of exposures: Figure 4 As shown, each exposure unit requires 4 exposures, and two adjacent exposure units require 8 exposures. Similarly, based on... Figure 2 The exposure method shown requires the following number of exposures: Figure 4 As shown, each exposure unit requires 4 exposures, and adjacent exposure units require 8 exposures. When the wafer area to be exposed is large, multi-row and multi-column exposure is required. The number of exposures and the exposure positions are as follows: Figure 5 As shown, eight exposure units are obtained: exposure unit 1 M1', exposure unit 2 M2', exposure unit 3 M3', exposure unit 4 M4', exposure unit 5 M5', exposure unit 6 M6', exposure unit 7 M7', and exposure unit 8 M8'. Each exposure unit requires four exposures. This results in a large number of masks being used, and consequently, a large number of exposures, leading to a waste of mask material and a more complicated exposure process.

[0072] Based on this, the present disclosure provides a wafer exposure processing method that optimizes the wafer exposure process by using a first type of mask and a second type of mask in combination. First, exposure units are determined on the wafer according to the exposure area. Then, the first type of mask and the second type of mask are used on the wafer according to a certain arrangement rule to expose the corresponding exposure units. The wafer exposure processing method in this disclosure can, on the one hand, save on the amount of mask used, reducing production costs; on the other hand, it can also reduce the number of exposures, improving wafer exposure efficiency.

[0073] An exemplary embodiment of this disclosure provides an exposure processing method applicable to wafer processing. For example... Figure 6 As shown, Figure 6 This is a flowchart illustrating a wafer exposure process according to an exemplary embodiment. The exposure method includes:

[0074] Step S101: Determine the surface to be exposed. The surface to be exposed has N adjacent exposure units, where N is a positive integer greater than or equal to 2.

[0075] The pattern of each exposure unit is exposed and spliced using at least one first mask and at least one second mask; wherein the at least one second mask comprises a first pattern and a second pattern; the first pattern and the second pattern are projected on two adjacent exposure units in the exposure process, respectively.

[0076] In the present exemplary embodiment, considering that the area of the surface to be exposed on the wafer is large, and the area projected by the exposure device on the surface to be exposed on the wafer at a time is limited, the wafer can be divided into small exposure units according to the area required by the core particles with corresponding functions, and exposure processing can be performed in combination with masks with appropriate sizes. It should be noted that the division of the exposure unit can be a physical division, that is, the division based on a separation line or the like; or a virtual division defined by the exposure device in the exposure processing.

[0077] To improve the efficiency of the exposure processing, the exposure is generally performed with the largest mask size, and at this time, the size of the exposure unit and the size of the mask can not match, such as the length and width of the exposure unit are not an integer multiple of the length and width of the mask (under the premise that the edge allowance of the exposure unit, the mask and the mask overlap are considered). Based on this, the wafer exposure processing method in the present exemplary embodiment uses a first mask and a second mask in combination to perform exposure processing on the wafer. Among them, the first mask based on the first preset size can be projected on one exposure unit by the exposure device to perform exposure on it; the second mask based on the second preset size can project the first pattern and the second pattern of the second mask on two adjacent exposure units in the exposure process, and synchronously expose the two adjacent exposure units, that is, when the unexposed area on the exposure unit cannot be adapted to a complete first mask for exposure, the exposure position of the first mask is reasonably adjusted, and then the second mask is used to expose the part of the two adjacent exposure units that cannot be adapted to a complete first mask, thereby realizing the exposure process of exposing two adjacent exposure units at a time. The wafer exposure processing method in the present exemplary embodiment maximizes the use of the exposure unit on the one hand; on the other hand, it saves the amount of mask used and reduces the number of exposures, thereby improving the exposure efficiency.

[0078] In some exemplary embodiments, the pattern of each exposure unit is exposed and spliced using at least one first mask and at least one second mask, comprising:

[0079] The full-size mask exposure area of the first exposure unit in the two adjacent exposure units is exposed using at least one first mask;

[0080] exposure region of the second exposure unit of the two adjacent exposure units is exposed using at least one first type mask;

[0081] The adjusted size mask exposure region of the first exposure unit and the adjusted size mask exposure region of the second exposure unit are jointly exposed using at least one second type mask; wherein the first pattern is projected on the adjusted size mask exposure region of the first exposure unit during the exposure process, and the second pattern is projected on the adjusted size mask exposure region of the second exposure unit during the exposure process.

[0082] In the present exemplary embodiment, the full size mask exposure region on the surface to be exposed is exposed using the first type mask, and the adjusted size mask exposure region on the surface to be exposed is exposed using the second type mask, so that the number of exposure times can be saved, and the maximum rational use of the wafer is realized. It should be noted that the full size mask exposure region refers to the region corresponding to the full size mask (a standard size specification mask made in actual production) projected on the surface to be exposed; the adjusted size mask exposure region refers to the region corresponding to the adjusted size mask (a non-standard size specification mask made in actual production, which can be designed in multiple sizes according to actual needs, and can be used in combination with the standard size specification mask) projected on the surface to be exposed.

[0083] Considering that the area of the surface to be exposed of the wafer is large, after determining the plurality of exposure units, a cutting path is formed to divide it, which can be realized by designing a corresponding pattern on the second type mask. Exemplarily, the second type mask further includes a third pattern located between the first pattern and the second pattern. At this time, the pattern of each exposure unit is exposed and spliced using at least one first type mask and at least one second type mask, and further includes that the third pattern is projected between the two adjacent exposure units to form a cutting path during the exposure process.

[0084] In some exemplary embodiments, considering that the number of the first type mask and the second type mask can be reasonably used according to actual needs to complete the exposure process of the surface to be exposed, the implementation process of one row of exposure process on the surface to be exposed is described below. At this time, one first type mask is used on the full size mask exposure region of the surface to be exposed, and one second type mask is used on the adjusted size mask exposure region of the surface to be exposed as an example for description.

[0085] As Figure 7 shown, Figure 7is a schematic diagram of the exposure of the surface to be exposed according to an exemplary embodiment. The first end of the first exposure unit in the two adjacent exposure units is exposed using the first mask 100, wherein the first end of the first exposure unit is the end away from the second exposure unit, including a full-size mask exposure area. The second end of the second exposure unit in the two adjacent exposure units is exposed using the third mask 300, wherein the second end of the second exposure unit is the end away from the first exposure unit, including a full-size mask exposure area. In the two adjacent exposure units, the second end of the first exposure unit and the first end of the second exposure unit are jointly exposed using the fifth mask, wherein the second end of the first exposure unit is the end close to the second exposure unit, including an adjusted-size mask exposure area; the first end of the second exposure unit is the end close to the first exposure unit, including an adjusted-size mask exposure area. The first mask 100 and the third mask 300 are the first type of mask; the fifth mask 500 is the second type of mask, which has a first pattern 501 for exposing the second end of the first exposure unit and a second pattern 502 for exposing the first end of the second exposure unit. It should be noted that, since the functions of the first exposure unit and the second exposure unit can be the same, the third mask 300 can be obtained by adjusting the first mask 100 according to a preset rule.

[0086] In some exemplary embodiments, as shown in Figure 8 Figure 8 is a schematic diagram of the exposure process of N exposure units according to an exemplary embodiment. At this time, the implementation process of performing two-row exposure processing on the surface to be exposed of the wafer is described. At this time, the pattern of each exposure unit is exposed and spliced using at least one first type of mask and at least one second type of mask, including:

[0087] Step S201, the upper part of the first end of the first exposure unit in the two adjacent exposure units is exposed using the first mask 100; the lower part of the first end of the first exposure unit is exposed using the second mask 200; wherein the first end of the first exposure unit is the end away from the second exposure unit;

[0088] Step S202, the upper part of the second end of the second exposure unit in the two adjacent exposure units is exposed using the third mask 300, and the lower part of the second end of the second exposure unit is exposed using the fourth mask 400; the second end of the second exposure unit is the end away from the first exposure unit;

[0089] Step S203, the fifth mask 500 is arranged between the exposure projections of the first mask 100 and the third mask 300 on the surface to be exposed, and the sixth mask 600 is arranged between the exposure projections of the second mask 200 and the fourth mask 400 on the surface to be exposed;

[0090] ​Step S204, based on the first mask 100, the second mask 200, the third mask 300, the fourth mask 400, the fifth mask 500 and the sixth mask 600, exposure is carried out to obtain the corresponding exposure area in the first and second exposure units;

[0091] Similarly, the corresponding exposure area in the N exposure units is obtained;

[0092] Among them, the first mask 100, the second mask 200, the third mask 300 and the fourth mask 400 are the first type of mask; the fifth mask 500 and the sixth mask 600 are the second type of mask.

[0093] In the present exemplary embodiment, it is taken as an example that the length of the exposure unit is greater than the length of one mask and less than the length of two masks, and the width of the exposure unit corresponds to the width of two masks. Based on four first type masks, the corresponding area of the four corners of the rectangle composed of two adjacent masks is exposed, and based on two second type masks, the middle area of the two exposure units which is not exposed is exposed.

[0094] Next, taking two rows of exposure processing on two adjacent exposure units as an example, it is illustrated as follows. Figure 9 As shown in Figure 9 According to an exemplary embodiment, a mask with a size of 26x33mm 2 The schematic diagram of the mask exposing two exposure units.

[0095] As can be seen from Figure 9 In the first exposure unit, the first end of the first exposure unit is exposed by two first type masks, that is, the upper part of the first end of the first exposure unit is exposed by the first mask 100, and the lower part of the first end of the first exposure unit is exposed by the second mask 200; similarly, in the second exposure unit, the second end of the second exposure unit is arranged by two first type masks, that is, the upper part of the second end of the second exposure unit is exposed by the third mask 300, and the lower part of the second end of the second exposure unit is exposed by the fourth mask 400.

[0096] For the adjacent part between the first exposure unit and the second exposure unit, the fifth mask 500 and the sixth mask 600 can be used for exposure, that is, the unexposed part between the first mask 100 and the third mask 300 (including the upper part of the end of the first exposure unit close to the second exposure unit, and the upper part of the end of the second exposure unit close to the first exposure unit) is exposed by the fifth mask 500, and the unexposed part between the second mask 200 and the fourth mask 400 (including the lower part of the end of the first exposure unit close to the second exposure unit, and the lower part of the end of the second exposure unit close to the first exposure unit) is exposed by the sixth mask 600.

[0097] AsFigure 10 As shown, Figure 10 According to an example embodiment, a wafer exposure method is provided, which is used for exposing a wafer with a size of 26*33mm 2 As shown in FIG. 1, the wafer exposure method includes the following steps. In the step S101, a first mask 100 is provided. The first mask 100 includes a first area 110 and a second area 120. The first area 110 covers a first exposure unit, and the second area 120 covers a second exposure unit. In the step S102, the first mask 100 is exposed to a first exposure unit. In the step S103, a second mask 200 is provided. The second mask 200 includes a third area 210 and a fourth area 220. The third area 210 covers the first exposure unit, and the fourth area 220 covers the second exposure unit. In the step S104, the second mask 200 is exposed to the first exposure unit. In the step S105, a third mask 300 is provided. The third mask 300 includes a fifth area 310 and a sixth area 320. The fifth area 310 covers the second exposure unit, and the sixth area 320 covers the first exposure unit. In the step S106, the third mask 300 is exposed to the second exposure unit. In the step S107, a fourth mask 400 is provided. The fourth mask 400 includes a seventh area 410 and an eighth area 420. The seventh area 410 covers the second exposure unit, and the eighth area 420 covers the first exposure unit. In the step S108, the fourth mask 400 is exposed to the second exposure unit. In the step S109, a fifth mask 500 is provided. The fifth mask 500 includes a ninth area 510 and a tenth area 520. The ninth area 510 covers the first exposure unit, and the tenth area 520 covers the second exposure unit. In the step S110, the fifth mask 500 is exposed to the first exposure unit. In the step S111, a sixth mask 600 is provided. The sixth mask 600 includes an eleventh area 610 and a twelfth area 620. The eleventh area 610 covers the first exposure unit, and the twelfth area 620 covers the second exposure unit. In the step S112, the sixth mask 600 is exposed to the first exposure unit. Figure 4 As shown in FIG. 1, the wafer exposure method includes the following steps. In the step S101, a first mask 100 is provided. The first mask 100 includes a first area 110 and a second area 120. The first area 110 covers a first exposure unit, and the second area 120 covers a second exposure unit. In the step S102, the first mask 100 is exposed to a first exposure unit. In the step S103, a second mask 200 is provided. The second mask 200 includes a third area 210 and a fourth area 220. The third area 210 covers the first exposure unit, and the fourth area 220 covers the second exposure unit. In the step S104, the second mask 200 is exposed to the first exposure unit. In the step S105, a third mask 300 is provided. The third mask 300 includes a fifth area 310 and a sixth area 320. The fifth area 310 covers the second exposure unit, and the sixth area 320 covers the first exposure unit. In the step S106, the third mask 300 is exposed to the second exposure unit. In the step S107, a fourth mask 400 is provided. The fourth mask 400 includes a seventh area 410 and an eighth area 420. The seventh area 410 covers the second exposure unit, and the eighth area 420 covers the first exposure unit. In the step S108, the fourth mask 400 is exposed to the second exposure unit. In the step S109, a fifth mask 500 is provided. The fifth mask 500 includes a ninth area 510 and a tenth area 520. The ninth area 510 covers the first exposure unit, and the tenth area 520 covers the second exposure unit. In the step S110, the fifth mask 500 is exposed to the first exposure unit. In the step S111, a sixth mask 600 is provided. The sixth mask 600 includes an eleventh area 610 and a twelfth area 620. The eleventh area 610 covers the first exposure unit, and the twelfth area 620 covers the second exposure unit. In the step S112, the sixth mask 600 is exposed to the first exposure unit.

[0098] In some example embodiments, based on the first mask 100, the second mask 200, the third mask 300, the fourth mask 400, the fifth mask 500, and the sixth mask 600, exposure is performed to obtain corresponding exposure areas in the first exposure unit and the second exposure unit, including: exposing each mask once to obtain corresponding exposure areas in the first exposure unit and the second exposure unit. The fifth mask 500 includes a first area covering the first exposure unit and a second area covering the second exposure unit. The sixth mask 600 includes a third area covering the first exposure unit and a fourth area covering the second exposure unit.

[0099] After the above exposure operation, the exposure area B of the first exposure unit can be obtained based on the area exposed by the first mask 100, the first area after exposure, the area exposed by the second mask 200, and the third area after exposure. The corresponding exposure area of the second exposure unit can be obtained based on the area exposed by the third mask 300, the second area after exposure, the area exposed by the fourth mask, and the fourth area after exposure. For example, if the structure and function of the first exposure unit and the second exposure unit are the same, the fourth mask 400 can be obtained by rotating the first mask 100 by 180 degrees, the third mask 300 can be obtained by rotating the second mask by 180 degrees, and the sixth mask 600 can be obtained by adjusting the fifth mask 500, for example, by rotating the fifth mask 500 by 180 degrees to obtain the sixth mask 600. The structure and function of the first area of the fifth mask 500 and the fourth area of the sixth mask 600 are the same, and the structure and function of the second area of the fifth mask 500 and the third area of the sixth mask 600 are the same.

[0100] In some example embodiments, considering that there is a case where the exposure requirements of two adjacent exposure units are partially the same in the wafer exposure process, the exposure of the two adjacent exposure units can be realized by adjusting the positions of the masks. For example, the processing method further comprises: the third mask 300 is obtained by adjusting the first mask 100 according to a preset rule, and the fourth mask 400 is obtained by adjusting the second mask 200 according to a preset rule; or, the third mask 300 is obtained by adjusting the second mask 200 according to a preset rule, and the fourth mask 400 is obtained by adjusting the first mask 100 according to a preset rule.

[0101] Optionally, in the case where the exposure requirements of two adjacent exposure units are completely the same in the wafer exposure process, the processing method further comprises: the sixth mask 600 is obtained by adjusting the fifth mask 500 according to a preset rule. Based on this, the first exposure unit and the second exposure unit obtained have the same functional structure. When the wafer is exposed, the wafer exposure processing method has fewer exposure times and further saves the number of masks compared with the traditional wafer exposure method.

[0102] In some example embodiments, the preset rule comprises: rotating 180 degrees or mirroring. For example: in the exposure process, first, the first mask 100 and the second mask 200 are used in sequence to expose the first exposure unit; then, the fifth mask 500 is used to expose the first exposure unit and the second exposure unit, and the sixth mask 600 (which can be obtained by rotating the fifth mask 500 by 180 degrees or mirroring) is used to expose the first exposure unit and the second exposure unit; finally, the first mask 100 and the second mask 200 are mirrored to obtain the third mask 300 and the fourth mask 400 (or, the first mask 100 and the second mask 200 are rotated by 180 degrees to obtain the fourth mask 400 and the third mask 300), and the second exposure unit on the surface to be exposed is exposed.

[0103] It should be noted that when the rotation of 180 degrees is adopted, the third mask 300 is obtained by rotating the second mask 200 by 180 degrees, and the fourth mask 400 is obtained by rotating the first mask 100 by 180 degrees; when the mirror image is adopted, the third mask 300 is obtained by mirroring the first mask 100, and the fourth mask 400 is obtained by mirroring the second mask 200. In addition, in order to ensure that the functional structures of the first exposure unit and the second exposure unit in the two adjacent exposure units are consistent, the third mask 300, the fourth mask 400 and the sixth mask 600 need to be obtained in the same way. Since the first mask 100, the second mask 200 and the fifth mask 500 can be adjusted in practice, they can be used directly as the third mask 300, the fourth mask 400 and the sixth mask 600, that is, after being adjusted in the mirror image mode, the first mask 100 and the third mask 300 are physically the same mask; the second mask 200 and the fourth mask 400 are physically the same mask; and the fifth mask 500 and the sixth mask 600 are physically the same mask. In this way, the number of masks can be saved, and the cost can be controlled.

[0104] In some example embodiments, the first type of mask includes a full-size mask; and the second type of mask includes an adjusted-size mask. In the process of exposing the wafer, the first exposure unit and the second exposure unit in the two adjacent exposure units are exposed by using the full-size mask, and the regions in the two adjacent exposure units that cannot match the full-size mask are exposed by using the adjusted-size mask, thereby reducing the number of masks and the number of exposures. The processing method for exposing the wafer not only saves the cost, but also improves the exposure efficiency.

[0105] In some example embodiments, the size of the larger exposure unit is generally 50*55mm 2 . For example, a first type of mask with a size of 26*33mm 2 may be selected, and a second type of mask with a size of 26*33mm 2 may be used in cooperation. It should be noted that the size of the second type of mask can be the same as that of the first type of mask, or can be different from that of the first type of mask. In order to meet the exposure processing of exposure units with different sizes, the size of the second type of mask can be prepared according to actual needs. If the size of the first type of mask is the same as that of the second type of mask, as shown in Figure 9 and Figure 10 , the sizes of the six masks are the same, and when the fifth mask 500 and the sixth mask 600 are used to expose the middle regions of two adjacent exposure units, if the sixth mask 600 is obtained by rotating the fifth mask 500 by 180 degrees, the first region of the fifth mask 500 and the fourth region of the sixth mask 600 have the same functional structure, and the second region of the fifth mask 500 and the third region of the sixth mask 600 have the same functional structure.

[0106] In some example embodiments, there is an overlapping area A between any two adjacent masks among the first mask 100, the second mask 200, the third mask 300, the fourth mask 400, the fifth mask 500 and the sixth mask 600. During the exposure of the wafer, the two adjacent exposure units are exposed by the masks one by one. Based on this, the first mask 100 is used to expose the first exposure unit first; then the second mask 200 is used to expose the first exposure unit, and the second mask 200 is moved to a preset position so that the second mask 200 and the first mask 100 form an overlapping area A with a preset width. At this time, the projection area of the second mask 200 on the first exposure unit also maintains an overlapping area A with the corresponding width between the area exposed by the first mask 100. After the first exposure unit is exposed based on the second mask 200, the area exposed by the second mask 200 can intersect with the area exposed by the first mask 100, which can ensure that the second mask 200 and the first mask 100 can be aligned and exposed on the first exposure unit, and can also realize the maximum utilization of the exposure area of the wafer.

[0107] In the example embodiment, if the sizes of the first type of mask and the second type of mask are equal, such as both being 26x33mm 2 , the long sides of the two adjacent masks (the side of the mask with a length of 33mm) correspond to each other, and the first preset overlapping width is formed after the two long sides overlap; the short sides of the two adjacent masks (the side of the mask with a length of 26mm) correspond to each other, and the second preset overlapping width is formed after the two short sides overlap. At this time, the first preset overlapping width and the second preset overlapping width formed between the two adjacent masks can be the same. For example, the first preset overlapping width ranges from 5 to 30 microns; the second preset overlapping width ranges from 5 to 30 microns.

[0108] It should be noted that the overlapping area A between other two adjacent masks is similar to the above-mentioned manner of exposure to form the overlapping area A, which will not be described here.

[0109] In some example embodiments, as shown in FIG. 6, Figure 11 Figure 11 is a schematic diagram of a mask with a size of 26x33mm 2 ​A schematic diagram of the mask performing multi-row and multi-column exposure. For each row of exposure units, exposure of two adjacent exposure units in the above manner can obtain the first exposure unit M1, the second exposure unit M2, the third exposure unit M3, the fourth exposure unit M4, the fifth exposure unit M5, the sixth exposure unit M6, the seventh exposure unit M7, and the eighth exposure unit M8. The exposure process is not described here. Based on this, it can be known that the number of exposures required when the wafer is exposed by the processing method of the wafer exposure in the example embodiment is greatly reduced compared with the number of exposures required by the traditional exposure method. In addition, it should be noted that when the number of exposure units in each row is odd, one separate exposure unit will be left. At this time, exposure can be performed according to the conventional method in the related art.

[0110] The present disclosure provides a wafer exposure processing device, as shown in Figure 12 Figure 12 is a structural schematic diagram of a wafer exposure processing device according to an example embodiment. The processing device comprises:

[0111] A determination module 1001 configured to determine, according to an exposure area, N adjacent exposure units on a wafer, where N is a positive integer greater than or equal to 2.

[0112] An exposure module 1002 configured to perform m exposures on the N exposure units based on at least one first type of mask and at least one second type of mask to obtain an exposure area on each exposure unit, where m is a positive integer less than N*4; the first type of mask comprises a first preset size, and the second type of mask comprises a second preset size.

[0113] In some example embodiments, the size of the exposure unit is 50*55mm 2 , the size of the first type of mask is 26*33mm 2 , and the size of the second type of mask is 26*33mm 2 .

[0114] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0115] Figure 13 is a block diagram of a wafer exposure processing device, i.e., a computer device, according to an example embodiment. The device can be the processing device in the example embodiments of the present disclosure, for example, the computer device can be provided as a terminal device. Referring to Figure 13 ​The computer device includes a processor 2001, and the number of the processor can be set to one or more according to the needs. The computer device also includes a memory 2002 for storing instructions, such as an application program, executable by the processor 2001. The number of the memory can be set to one or more according to the needs. The stored application program can be one or more. The processor 2001 is configured to execute the instructions to perform the above method.

[0116] Those skilled in the art will appreciate that embodiments of the present disclosure can be provided as methods, apparatus (devices), or computer program products. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure can take the form of a computer program product on one or more computer-usable storage media (including volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data) embodying computer readable instructions, other data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. In addition, it should be understood that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Further, those skilled in the art will appreciate that functions can be embodied in one or more processors, either in a single device or distributed among several devices.

[0117] In an exemplary embodiment, a non-transitory computer readable storage medium including instructions, such as the memory 2002 including instructions, is provided, which can be executed by the processor 2001 of the apparatus to complete the above method. For example, the non-transitory computer readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0118] In an exemplary embodiment of the present disclosure, a non-transitory computer readable storage medium is provided, which, when the instructions in the storage medium are executed by the processor of the determining apparatus, enables the determining apparatus to perform the method provided by the exemplary embodiment of the present disclosure.

[0119] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0120] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0121] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0122] In this disclosure, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the identified element.

[0123] While the preferred embodiments of the disclosure have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the foregoing description. Therefore, the appended claims are intended to encompass within their scope all possible variations and modifications of the preferred embodiments.

[0124] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

1. A method of processing an exposure, characterized by, The processing method comprises: determining a surface to be exposed, the surface to be exposed being provided with N adjacent exposure units, wherein N is a positive integer greater than or equal to 2; a pattern of each exposure unit is exposed and spliced using at least one first mask and at least one second mask, wherein the at least one second mask comprises a first pattern, a second pattern and a third pattern between the first pattern and the second pattern; the first pattern and the second pattern are projected on two adjacent exposure units respectively during exposure, and the two adjacent exposure units are synchronously exposed; the pattern of each exposure unit is exposed and spliced using at least one first mask and at least one second mask, comprising: the third pattern is projected between two adjacent exposure units during exposure to form a cutting path.

2. The processing method of exposure according to claim 1, wherein The pattern of each exposure unit is exposed and spliced using at least one first mask and at least one second mask, further comprising: exposing a full-size mask exposure area of a first exposure unit in the two adjacent exposure units using at least one first mask; exposing a full-size mask exposure area of a second exposure unit in the two adjacent exposure units using at least one first mask; exposing an adjusted-size mask exposure area of the first exposure unit and an adjusted-size mask exposure area of the second exposure unit using at least one second mask; wherein the first pattern is projected on the adjusted-size mask exposure area of the first exposure unit during exposure, and the second pattern is projected on the adjusted-size mask exposure area of the second exposure unit during exposure.

3. The processing method of exposure according to claim 2, wherein: exposing a first end of a first exposure unit in the two adjacent exposure units using a first mask, wherein the first end of the first exposure unit is an end away from the second exposure unit and comprises the full-size mask exposure area; exposing a second end of a second exposure unit in the two adjacent exposure units using a third mask, wherein the second end of the second exposure unit is an end away from the first exposure unit and comprises the full-size mask exposure area; exposing a second end of the first exposure unit and a first end of the second exposure unit in the two adjacent exposure units using a fifth mask; wherein the second end of the first exposure unit is an end close to the second exposure unit and comprises the adjusted-size mask exposure area, and the first end of the second exposure unit is an end close to the first exposure unit and comprises the adjusted-size mask exposure area, wherein the first mask and the third mask are the first masks, and the fifth mask is a second mask.

4. The processing method of exposure according to Claim 3, wherein The third mask is obtained by adjusting the first mask according to a preset rule.

5. The processing method of exposure according to claim 2, wherein: exposure is performed on the upper part of the first end of the first exposure unit using a first mask; exposure is performed on the lower part of the first end of the first exposure unit using a second mask; The first end of the first exposure unit is an end away from the second exposure unit; exposure is performed on the upper part of the second end of the second exposure unit using a third mask; exposure is performed on the lower part of the second end of the second exposure unit using a fourth mask; The second end of the second exposure unit is an end away from the first exposure unit; A fifth mask is arranged between the exposure projections of the first mask and the third mask on the surface to be exposed; a sixth mask is arranged between the exposure projections of the second mask and the fourth mask on the surface to be exposed; Based on the first mask, the second mask, the third mask, the fourth mask, the fifth mask and the sixth mask, exposure is performed to obtain the corresponding exposure areas in the first exposure unit and the second exposure unit; Similarly, the corresponding exposure areas in N exposure units are obtained; The first mask, the second mask, the third mask and the fourth mask are first-type masks; the fifth mask and the sixth mask are second-type masks.

6. The processing method of exposure according to claim 5, wherein The processing method further comprises: The third mask is obtained by adjusting the first mask according to a preset rule; the fourth mask is obtained by adjusting the second mask according to the preset rule; or The third mask is obtained by adjusting the second mask according to a preset rule; the fourth mask is obtained by adjusting the first mask according to the preset rule.

7. The method of processing an exposure according to claim 5, wherein Based on the first mask, the second mask, the third mask, the fourth mask, the fifth mask and the sixth mask, exposure is performed to obtain the corresponding exposure areas in the first exposure unit and the second exposure unit, comprising: Each mask is exposed once to obtain the corresponding exposure areas in the first exposure unit and the second exposure unit.

8. The processing method of exposure according to one of claim 4 or 6, wherein The preset rule comprises: Rotating 180 degrees or mirroring.

9. The processing method of exposure according to claim 8, wherein The first pattern is the same as the second pattern.

10. The method of processing an exposure according to claim 1, wherein The first-type masks comprise full-size masks; the second-type masks comprise size-adjusted masks.

11. The method of processing an exposure according to claim 5, wherein Any two adjacent masks among the first mask, the second mask, the third mask, the fourth mask, the fifth mask and the sixth mask comprise an overlapping area.

12. An exposure processing apparatus of a processing method of performing the exposure of any one of claims 1 through 11, characterized by The processing device comprises: A partition module configured to preset N adjacent exposure units, wherein N is a positive integer greater than or equal to 2; An exposure module configured to expose the N adjacent exposure units, wherein the pattern of each exposure unit is exposed and spliced using at least one first-type mask and at least one second-type mask; at least one second-type mask contains a first pattern and a second pattern, and the first pattern and the second pattern are projected on adjacent two exposure units during exposure, respectively, to perform synchronous exposure on the two adjacent exposure units.

13. An exposure processing apparatus characterized by comprising: The processing device comprises: A processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the processing method of any one of claims 1-11.

14. A non-transitory computer-readable storage medium that, when instructions in the storage medium are executed by a processor of an apparatus, enable the apparatus to perform the processing method of any one of claims 1-11.

Images